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#ifndef CPU_H |
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#define CPU_H |
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/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu.h,v 1.62 2006/02/09 22:40:27 debug Exp $ |
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* |
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* CPU-related definitions. |
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*/ |
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#include <sys/types.h> |
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#include <inttypes.h> |
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#include <sys/time.h> |
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/* This is needed for undefining 'mips', 'ppc' etc. on weird systems: */ |
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#include "../../config.h" |
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/* |
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* Dyntrans misc declarations, used throughout the dyntrans code. |
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*/ |
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#define DYNTRANS_MISC_DECLARATIONS(arch,ARCH,addrtype) struct \ |
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arch ## _instr_call { \ |
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void (*f)(struct cpu *, struct arch ## _instr_call *); \ |
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size_t arg[ARCH ## _N_IC_ARGS]; \ |
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}; \ |
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\ |
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/* Translation cache struct for each physical page: */ \ |
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struct arch ## _tc_physpage { \ |
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struct arch ## _instr_call ics[ARCH ## _IC_ENTRIES_PER_PAGE+1];\ |
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uint32_t next_ofs; /* (0 for end of chain) */ \ |
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int flags; \ |
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addrtype physaddr; \ |
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}; \ |
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\ |
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struct arch ## _vpg_tlb_entry { \ |
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uint8_t valid; \ |
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uint8_t writeflag; \ |
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addrtype vaddr_page; \ |
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addrtype paddr_page; \ |
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unsigned char *host_page; \ |
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int64_t timestamp; \ |
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}; |
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/* |
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* Dyntrans "Instruction Translation Cache": |
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* |
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* cur_physpage is a pointer to the current physpage. (It _HAPPENS_ to |
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* be the same as cur_ic_page, because all the instrcalls should be placed |
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* first in the physpage struct!) |
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* |
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* cur_ic_page is a pointer to an array of xxx_IC_ENTRIES_PER_PAGE |
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* instruction call entries. |
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* |
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* next_ic points to the next such instruction call to be executed. |
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* |
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* combination_check, when set to non-NULL, is executed automatically after |
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* an instruction has been translated. (It check for combinations of |
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* instructions; low_addr is the offset of the translated instruction in the |
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* current page, NOT shifted right.) |
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*/ |
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#define DYNTRANS_ITC(arch) struct arch ## _tc_physpage *cur_physpage; \ |
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struct arch ## _instr_call *cur_ic_page; \ |
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struct arch ## _instr_call *next_ic; \ |
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void (*combination_check)(struct cpu *, \ |
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struct arch ## _instr_call *, int low_addr); |
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/* |
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* Virtual -> physical -> host address translation TLB entries: |
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* ------------------------------------------------------------ |
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* |
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* Regardless of whether 32-bit or 64-bit address translation is used, the |
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* same TLB entry structure is used. |
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*/ |
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#define VPH_TLBS(arch,ARCH) \ |
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struct arch ## _vpg_tlb_entry \ |
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vph_tlb_entry[ARCH ## _MAX_VPH_TLB_ENTRIES]; |
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/* |
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* 32-bit dyntrans emulated Virtual -> physical -> host address translation: |
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* ------------------------------------------------------------------------- |
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* |
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* This stuff assumes that 4 KB pages are used. 20 bits to select a page |
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* means just 1 M entries needed. This is small enough that a couple of |
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* full-size tables can fit in virtual memory on modern hosts (both 32-bit |
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* and 64-bit hosts). :-) |
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* |
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* Usage: e.g. VPH32(arm,ARM,uint32_t,uint8_t) |
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* or VPH32(sparc,SPARC,uint64_t,uint16_t) |
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* |
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* The vph_tlb_entry entries are cpu dependent tlb entries. |
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* |
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* The host_load and host_store entries point to host pages; the phys_addr |
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* entries are uint32_t or uint64_t (emulated physical addresses). |
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* |
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* phys_page points to translation cache physpages. |
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* |
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* phystranslation is a bitmap which tells us whether a physical page has |
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* a code translation. |
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* |
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* vaddr_to_tlbindex is a virtual address to tlb index hint table. |
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* The values in this array are the tlb index plus 1, so a value of, say, |
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* 3 means tlb index 2. A value of 0 would mean a tlb index of -1, which |
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* is not a valid index. (I.e. no hit.) |
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*/ |
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#define N_VPH32_ENTRIES 1048576 |
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#define VPH32(arch,ARCH,paddrtype,tlbindextype) \ |
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unsigned char *host_load[N_VPH32_ENTRIES]; \ |
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unsigned char *host_store[N_VPH32_ENTRIES]; \ |
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paddrtype phys_addr[N_VPH32_ENTRIES]; \ |
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struct arch ## _tc_physpage *phys_page[N_VPH32_ENTRIES]; \ |
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uint32_t phystranslation[N_VPH32_ENTRIES/32]; \ |
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tlbindextype vaddr_to_tlbindex[N_VPH32_ENTRIES]; |
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/* |
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* 64-bit dyntrans emulated Virtual -> physical -> host address translation: |
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* ------------------------------------------------------------------------- |
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* |
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* Usage: e.g. VPH64(alpha,ALPHA,uint8_t) |
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* or VPH64(sparc,SPARC,uint16_t) |
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* |
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* TODO |
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*/ |
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#define VPH64(arch,ARCH,tlbindextype) \ |
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int dummy; |
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dpavlin |
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#include "cpu_alpha.h" |
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#include "cpu_arm.h" |
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#include "cpu_avr.h" |
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#include "cpu_hppa.h" |
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#include "cpu_i960.h" |
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#include "cpu_ia64.h" |
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#include "cpu_m68k.h" |
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#include "cpu_mips.h" |
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#include "cpu_ppc.h" |
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#include "cpu_sh.h" |
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#include "cpu_sparc.h" |
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#include "cpu_x86.h" |
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struct cpu; |
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struct emul; |
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struct machine; |
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struct memory; |
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struct cpu_family { |
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struct cpu_family *next; |
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int arch; |
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/* These are filled in by each CPU family's init function: */ |
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char *name; |
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int (*cpu_new)(struct cpu *cpu, struct memory *mem, |
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struct machine *machine, |
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int cpu_id, char *cpu_type_name); |
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void (*list_available_types)(void); |
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void (*register_match)(struct machine *m, |
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char *name, int writeflag, |
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uint64_t *valuep, int *match_register); |
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int (*disassemble_instr)(struct cpu *cpu, |
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unsigned char *instr, int running, |
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uint64_t dumpaddr, int bintrans); |
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void (*register_dump)(struct cpu *cpu, |
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int gprs, int coprocs); |
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int (*run)(struct emul *emul, |
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struct machine *machine); |
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void (*dumpinfo)(struct cpu *cpu); |
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void (*show_full_statistics)(struct machine *m); |
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void (*tlbdump)(struct machine *m, int x, |
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int rawflag); |
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int (*interrupt)(struct cpu *cpu, uint64_t irq_nr); |
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int (*interrupt_ack)(struct cpu *cpu, |
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uint64_t irq_nr); |
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void (*functioncall_trace)(struct cpu *, |
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uint64_t f, int n_args); |
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}; |
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/* |
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* More dyntrans stuff: |
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* |
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* The translation cache begins with N_BASE_TABLE_ENTRIES uint32_t offsets |
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* into the cache, for possible translation cache structs for physical pages. |
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*/ |
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/* Physpage flags: */ |
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#define TRANSLATIONS 1 |
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#define COMBINATIONS 2 |
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#define DYNTRANS_CACHE_SIZE (16*1048576) |
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#define DYNTRANS_CACHE_MARGIN 300000 |
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#define N_BASE_TABLE_ENTRIES 32768 |
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#define PAGENR_TO_TABLE_INDEX(a) ((a) & (N_BASE_TABLE_ENTRIES-1)) |
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dpavlin |
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#ifdef DYNTRANS_BACKEND |
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/* TODO: convert this into a fixed-size array? Might increase performace. */ |
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struct dtb_fixup { |
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struct dtb_fixup *next; |
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int type; /* Fixup type [optional] */ |
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void *addr; /* Address of the instruction |
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(in host memory) */ |
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size_t data; /* Emulation data. */ |
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}; |
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struct translation_context { |
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/* Current address of where to emit host instructions: */ |
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/* (NULL means no translation is currently being done.) */ |
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void *p; |
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/* index of the instr_call of the first translated instruction: */ |
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void *ic_page; |
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int start_instr_call_index; |
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/* Fixups needed after first translation pass: */ |
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struct dtb_fixup *fixups; |
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int n_simple; |
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/* translation_buffer should have room for max_size bytes, |
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plus some margin. */ |
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unsigned char *translation_buffer; |
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size_t cur_size; |
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}; |
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#define DTB_TRANSLATION_SIZE_MAX 3072 |
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#define DTB_TRANSLATION_SIZE_MARGIN 1024 |
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void cpu_dtb_add_fixup(struct cpu *cpu, int type, void *addr, size_t data); |
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void cpu_dtb_do_fixups(struct cpu *cpu); |
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void dtb_host_cacheinvalidate(void *p, size_t len); |
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int dtb_function_prologue(struct translation_context *ctx, size_t *sizep); |
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int dtb_function_epilogue(struct translation_context *ctx, size_t *sizep); |
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int dtb_generate_fcall(struct cpu *cpu, struct translation_context *ctx, |
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size_t *sizep, size_t f, size_t instr_call_ptr); |
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int dtb_generate_ptr_inc(struct cpu *cpu, struct translation_context *ctx, |
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size_t *sizep, void *ptr, int amount); |
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#endif /* DYNTRANS_BACKEND */ |
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dpavlin |
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/* |
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* The generic CPU struct: |
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*/ |
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struct cpu { |
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/* Pointer back to the machine this CPU is in: */ |
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struct machine *machine; |
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int byte_order; |
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int running; |
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int dead; |
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int bootstrap_cpu_flag; |
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int cpu_id; |
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dpavlin |
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int is_32bit; /* 0 for 64-bit, 1 for 32-bit */ |
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dpavlin |
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char *name; |
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struct memory *mem; |
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int (*memory_rw)(struct cpu *cpu, |
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struct memory *mem, uint64_t vaddr, |
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unsigned char *data, size_t len, |
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int writeflag, int cache_flags); |
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int (*translate_address)(struct cpu *, uint64_t vaddr, |
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uint64_t *return_addr, int flags); |
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dpavlin |
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void (*update_translation_table)(struct cpu *, |
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uint64_t vaddr_page, unsigned char *host_page, |
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int writeflag, uint64_t paddr_page); |
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dpavlin |
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void (*invalidate_translation_caches)(struct cpu *, |
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dpavlin |
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uint64_t paddr, int flags); |
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void (*invalidate_code_translation)(struct cpu *, |
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uint64_t paddr, int flags); |
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dpavlin |
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void (*useremul_syscall)(struct cpu *cpu, uint32_t code); |
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dpavlin |
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uint64_t pc; |
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dpavlin |
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#ifdef TRACE_NULL_CRASHES |
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/* TODO: remove this, it's MIPS only */ |
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dpavlin |
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int trace_null_index; |
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dpavlin |
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uint64_t trace_null_addr[TRACE_NULL_N_ENTRIES]; |
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#endif |
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dpavlin |
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int trace_tree_depth; |
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/* |
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* Dynamic translation: |
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*/ |
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int running_translated; |
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int n_translated_instrs; |
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unsigned char *translation_cache; |
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size_t translation_cache_cur_ofs; |
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dpavlin |
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#ifdef DYNTRANS_BACKEND |
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struct translation_context translation_context; |
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#endif |
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dpavlin |
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/* |
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* CPU-family dependent: |
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*/ |
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dpavlin |
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union { |
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dpavlin |
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struct alpha_cpu alpha; |
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dpavlin |
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struct arm_cpu arm; |
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dpavlin |
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struct avr_cpu avr; |
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struct hppa_cpu hppa; |
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struct i960_cpu i960; |
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dpavlin |
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struct ia64_cpu ia64; |
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struct m68k_cpu m68k; |
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dpavlin |
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struct mips_cpu mips; |
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struct ppc_cpu ppc; |
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dpavlin |
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struct sh_cpu sh; |
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dpavlin |
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struct sparc_cpu sparc; |
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dpavlin |
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struct x86_cpu x86; |
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} cd; |
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}; |
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/* cpu.c: */ |
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struct cpu *cpu_new(struct memory *mem, struct machine *machine, |
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int cpu_id, char *cpu_type_name); |
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void cpu_show_full_statistics(struct machine *m); |
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void cpu_tlbdump(struct machine *m, int x, int rawflag); |
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void cpu_register_match(struct machine *m, char *name, |
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int writeflag, uint64_t *valuep, int *match_register); |
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void cpu_register_dump(struct machine *m, struct cpu *cpu, |
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int gprs, int coprocs); |
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int cpu_disassemble_instr(struct machine *m, struct cpu *cpu, |
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unsigned char *instr, int running, uint64_t addr, int bintrans); |
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int cpu_interrupt(struct cpu *cpu, uint64_t irq_nr); |
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int cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr); |
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dpavlin |
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void cpu_functioncall_trace(struct cpu *cpu, uint64_t f); |
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void cpu_functioncall_trace_return(struct cpu *cpu); |
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void cpu_create_or_reset_tc(struct cpu *cpu); |
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void cpu_run_init(struct machine *machine); |
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dpavlin |
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int cpu_run(struct emul *emul, struct machine *machine); |
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dpavlin |
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void cpu_run_deinit(struct machine *machine); |
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dpavlin |
4 |
void cpu_dumpinfo(struct machine *m, struct cpu *cpu); |
363 |
|
|
void cpu_list_available_types(void); |
364 |
dpavlin |
10 |
void cpu_show_cycles(struct machine *machine, int forced); |
365 |
dpavlin |
4 |
struct cpu_family *cpu_family_ptr_by_number(int arch); |
366 |
|
|
void cpu_init(void); |
367 |
|
|
|
368 |
|
|
|
369 |
dpavlin |
14 |
#define JUST_MARK_AS_NON_WRITABLE 1 |
370 |
|
|
#define INVALIDATE_ALL 2 |
371 |
|
|
#define INVALIDATE_PADDR 4 |
372 |
|
|
#define INVALIDATE_VADDR 8 |
373 |
dpavlin |
22 |
#define INVALIDATE_VADDR_UPPER4 16 /* useful for PPC emulation */ |
374 |
dpavlin |
14 |
|
375 |
dpavlin |
18 |
#define TLB_CODE 0x02 |
376 |
dpavlin |
14 |
|
377 |
dpavlin |
18 |
|
378 |
dpavlin |
12 |
#define CPU_FAMILY_INIT(n,s) int n ## _cpu_family_init( \ |
379 |
|
|
struct cpu_family *fp) { \ |
380 |
|
|
/* Fill in the cpu_family struct with valid data for this arch. */ \ |
381 |
|
|
fp->name = s; \ |
382 |
|
|
fp->cpu_new = n ## _cpu_new; \ |
383 |
|
|
fp->list_available_types = n ## _cpu_list_available_types; \ |
384 |
|
|
fp->register_match = n ## _cpu_register_match; \ |
385 |
|
|
fp->disassemble_instr = n ## _cpu_disassemble_instr; \ |
386 |
|
|
fp->register_dump = n ## _cpu_register_dump; \ |
387 |
|
|
fp->run = n ## _cpu_run; \ |
388 |
|
|
fp->dumpinfo = n ## _cpu_dumpinfo; \ |
389 |
dpavlin |
20 |
fp->interrupt = n ## _cpu_interrupt; \ |
390 |
|
|
fp->interrupt_ack = n ## _cpu_interrupt_ack; \ |
391 |
|
|
fp->functioncall_trace = n ## _cpu_functioncall_trace; \ |
392 |
|
|
return 1; \ |
393 |
|
|
} |
394 |
|
|
|
395 |
|
|
#define CPU_OLD_FAMILY_INIT(n,s) int n ## _cpu_family_init( \ |
396 |
|
|
struct cpu_family *fp) { \ |
397 |
|
|
/* Fill in the cpu_family struct with valid data for this arch. */ \ |
398 |
|
|
fp->name = s; \ |
399 |
|
|
fp->cpu_new = n ## _cpu_new; \ |
400 |
|
|
fp->list_available_types = n ## _cpu_list_available_types; \ |
401 |
|
|
fp->register_match = n ## _cpu_register_match; \ |
402 |
|
|
fp->disassemble_instr = n ## _cpu_disassemble_instr; \ |
403 |
|
|
fp->register_dump = n ## _cpu_register_dump; \ |
404 |
dpavlin |
22 |
fp->run = n ## _OLD_cpu_run; \ |
405 |
dpavlin |
20 |
fp->dumpinfo = n ## _cpu_dumpinfo; \ |
406 |
dpavlin |
12 |
fp->show_full_statistics = n ## _cpu_show_full_statistics; \ |
407 |
|
|
fp->tlbdump = n ## _cpu_tlbdump; \ |
408 |
|
|
fp->interrupt = n ## _cpu_interrupt; \ |
409 |
|
|
fp->interrupt_ack = n ## _cpu_interrupt_ack; \ |
410 |
|
|
fp->functioncall_trace = n ## _cpu_functioncall_trace; \ |
411 |
|
|
return 1; \ |
412 |
|
|
} |
413 |
|
|
|
414 |
|
|
|
415 |
dpavlin |
4 |
#endif /* CPU_H */ |