/[gxemul]/upstream/0.4.4/src/include/cop0.h
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revision 4 by dpavlin, Mon Oct 8 16:18:00 2007 UTC revision 32 by dpavlin, Mon Oct 8 16:20:58 2007 UTC
# Line 2  Line 2 
2  #define COP0_H  #define COP0_H
3    
4  /*  /*
5   *  Copyright (C) 2003-2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2003-2006  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cop0.h,v 1.6 2005/01/18 06:22:58 debug Exp $   *  $Id: cop0.h,v 1.12 2006/10/02 08:03:16 debug Exp $
32   *   *
33   *  Misc. definitions for coprocessor 0.   *  Misc. definitions for coprocessor 0.
34   */   */
35    
36    
37  /*  TODO:  Coproc registers are actually CPU dependant, so an R4000  /*  TODO:  Coproc registers are actually CPU dependent, so an R4000
38          has other bits/registers than an R3000...          has other bits/registers than an R3000...
39      TODO 2: CPUs like the R10000 are probably even a bit more different.  */      TODO 2: CPUs like the R10000 are probably even a bit more different.  */
40    
# Line 85  Line 85 
85  #define COP0_PAGEMASK           5  #define COP0_PAGEMASK           5
86  #define    PAGEMASK_MASK            0x01ffe000  #define    PAGEMASK_MASK            0x01ffe000
87  #define    PAGEMASK_SHIFT           13  #define    PAGEMASK_SHIFT           13
88  #define    PAGEMASK_MASK_R4100      0x0007f800          /*  TODO: At least VR4131, how about others?  */  #define    PAGEMASK_MASK_R4100      0x0007f800  /*  TODO: At least VR4131,  */
89                                                    /*  how about others?  */
90  #define    PAGEMASK_SHIFT_R4100     11  #define    PAGEMASK_SHIFT_R4100     11
91  #define COP0_WIRED              6  #define COP0_WIRED              6
92  #define COP0_RESERV7            7  #define COP0_RESERV7            7
# Line 94  Line 95 
95  #define COP0_ENTRYHI            10  #define COP0_ENTRYHI            10
96  /*  R4000 ENTRYHI:  */  /*  R4000 ENTRYHI:  */
97  #define    ENTRYHI_R_MASK           0xc000000000000000ULL  #define    ENTRYHI_R_MASK           0xc000000000000000ULL
98    #define    ENTRYHI_R_XKPHYS         0x8000000000000000ULL
99  #define    ENTRYHI_R_SHIFT          62  #define    ENTRYHI_R_SHIFT          62
100  #define    ENTRYHI_VPN2_MASK_R10K   0x00000fffffffe000ULL  #define    ENTRYHI_VPN2_MASK_R10K   0x00000fffffffe000ULL
101  #define    ENTRYHI_VPN2_MASK        0x000000ffffffe000ULL  #define    ENTRYHI_VPN2_MASK        0x000000ffffffe000ULL
# Line 124  Line 126 
126  #define    STATUS_ERL               0x04  #define    STATUS_ERL               0x04
127  #define    STATUS_EXL               0x02  #define    STATUS_EXL               0x02
128  #define    STATUS_IE                0x01  #define    STATUS_IE                0x01
129  #define    R5900_STATUS_EIE         0x10000  #define    R5900_STATUS_EDI         0x20000             /*  EI/DI instruction enable  */
130    #define    R5900_STATUS_EIE         0x10000             /*  Enable Interrupt Enable  */
131  #define COP0_CAUSE              13  #define COP0_CAUSE              13
132  #define    CAUSE_BD                 0x80000000UL        /*  branch delay flag  */  #define    CAUSE_BD                 0x80000000UL        /*  branch delay flag  */
133  #define    CAUSE_CE_MASK            0x30000000          /*  which coprocessor  */  #define    CAUSE_CE_MASK            0x30000000          /*  which coprocessor  */
# Line 195  Line 198 
198  #define EXCEPTION_TR            13      /*  Trap exception  */  #define EXCEPTION_TR            13      /*  Trap exception  */
199  #define EXCEPTION_VCEI          14      /*  Virtual Coherency Exception, Instruction  */  #define EXCEPTION_VCEI          14      /*  Virtual Coherency Exception, Instruction  */
200  #define EXCEPTION_FPE           15      /*  Floating point exception  */  #define EXCEPTION_FPE           15      /*  Floating point exception  */
201  /*  16..17: Available for "implementation dependant use"  */  /*  16..17: Available for "implementation dependent use"  */
202  #define EXCEPTION_C2E           18      /*  MIPS64 C2E (precise coprocessor 2 exception)  */  #define EXCEPTION_C2E           18      /*  MIPS64 C2E (precise coprocessor 2 exception)  */
203  /*  19..21: Reserved  */  /*  19..21: Reserved  */
204  #define EXCEPTION_MDMX          22      /*  MIPS64 MDMX unusable  */  #define EXCEPTION_MDMX          22      /*  MIPS64 MDMX unusable  */
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