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/* gxemul: $Id: comreg.h,v 1.3 2005/03/05 12:34:02 debug Exp $ */ |
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#ifndef COMREG_H |
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#define COMREG_H |
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|
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/* $NetBSD: comreg.h,v 1.11 1997/10/19 14:26:21 fvdl Exp $ */ |
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|
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/*- |
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* Copyright (c) 1991 The Regents of the University of California. |
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* All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed by the University of |
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* California, Berkeley and its contributors. |
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* 4. Neither the name of the University nor the names of its contributors |
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* may be used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* @(#)comreg.h 7.2 (Berkeley) 5/9/91 |
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*/ |
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|
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#include "ns16550reg.h" |
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|
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#define COM_FREQ 1843200 /* 16-bit baud rate divisor */ |
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#define COM_TOLERANCE 30 /* baud rate tolerance, in 0.1% units */ |
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|
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/* interrupt enable register */ |
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#define IER_ERXRDY 0x1 /* Enable receiver interrupt */ |
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#define IER_ETXRDY 0x2 /* Enable transmitter empty interrupt */ |
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#define IER_ERLS 0x4 /* Enable line status interrupt */ |
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#define IER_EMSC 0x8 /* Enable modem status interrupt */ |
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#define IER_ERTS 0x40 /* Enable RTS interrupt */ |
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#define IER_ECTS 0x80 /* Enable CTS interrupt */ |
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|
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/* interrupt identification register */ |
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#define IIR_IMASK 0xf |
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#define IIR_RXTOUT 0xc |
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#define IIR_RLS 0x6 /* Line status change */ |
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#define IIR_RXRDY 0x4 /* Receiver ready */ |
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#define IIR_TXRDY 0x2 /* Transmitter ready */ |
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#define IIR_MLSC 0x0 /* Modem status */ |
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#define IIR_NOPEND 0x1 /* No pending interrupts */ |
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#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ |
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|
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/* fifo control register */ |
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#define FIFO_ENABLE 0x01 /* Turn the FIFO on */ |
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#define FIFO_RCV_RST 0x02 /* Reset RX FIFO */ |
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#define FIFO_XMT_RST 0x04 /* Reset TX FIFO */ |
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#define FIFO_DMA_MODE 0x08 |
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#define FIFO_TRIGGER_1 0x00 /* Trigger RXRDY intr on 1 character */ |
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#define FIFO_TRIGGER_4 0x40 /* ibid 4 */ |
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#define FIFO_TRIGGER_8 0x80 /* ibid 8 */ |
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#define FIFO_TRIGGER_14 0xc0 /* ibid 14 */ |
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|
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/* enhanced feature register */ |
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#define EFR_AUTOCTS 0x80 /* Automatic CTS flow control */ |
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#define EFR_AUTORTS 0x40 /* Automatic RTS flow control */ |
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#define EFR_SPECIAL 0x20 /* Special char detect */ |
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#define EFR_EFCR 0x10 /* Enhanced function control bit */ |
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#define EFR_TXFLOWBOTH 0x0c /* Automatic transmit XON/XOFF 1 and 2 */ |
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#define EFR_TXFLOW1 0x08 /* Automatic transmit XON/XOFF 1 */ |
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#define EFR_TXFLOW2 0x04 /* Automatic transmit XON/XOFF 2 */ |
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#define EFR_TXFLOWNONE 0x00 /* No automatic XON/XOFF transmit */ |
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#define EFR_RXFLOWBOTH 0x03 /* Automatic receive XON/XOFF 1 and 2 */ |
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#define EFR_RXFLOW1 0x02 /* Automatic receive XON/XOFF 1 */ |
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#define EFR_RXFLOW2 0x01 /* Automatic receive XON/XOFF 2 */ |
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#define EFR_RXFLOWNONE 0x00 /* No automatic XON/XOFF receive */ |
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|
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/* line control register */ |
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#define LCR_EERS 0xBF /* Enable access to Enhanced Register Set */ |
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#define LCR_DLAB 0x80 /* Divisor latch access enable */ |
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#define LCR_SBREAK 0x40 /* Break Control */ |
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#define LCR_PZERO 0x38 /* Space parity */ |
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#define LCR_PONE 0x28 /* Mark parity */ |
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#define LCR_PEVEN 0x18 /* Even parity */ |
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#define LCR_PODD 0x08 /* Odd parity */ |
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#define LCR_PNONE 0x00 /* No parity */ |
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#define LCR_PENAB 0x08 /* XXX - low order bit of all parity */ |
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#define LCR_STOPB 0x04 /* 2 stop bits per serial word */ |
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#define LCR_8BITS 0x03 /* 8 bits per serial word */ |
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#define LCR_7BITS 0x02 /* 7 bits */ |
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#define LCR_6BITS 0x01 /* 6 bits */ |
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#define LCR_5BITS 0x00 /* 5 bits */ |
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|
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/* modem control register */ |
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#define MCR_LOOPBACK 0x10 /* Loop test: echos from TX to RX */ |
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#define MCR_IENABLE 0x08 /* Out2: enables UART interrupts */ |
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#define MCR_DRS 0x04 /* Out1: resets some internal modems */ |
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#define MCR_RTS 0x02 /* Request To Send */ |
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#define MCR_DTR 0x01 /* Data Terminal Ready */ |
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|
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/* line status register */ |
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#define LSR_RCV_FIFO 0x80 |
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#define LSR_TSRE 0x40 /* Transmitter empty: byte sent */ |
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#define LSR_TXRDY 0x20 /* Transmitter buffer empty */ |
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#define LSR_BI 0x10 /* Break detected */ |
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#define LSR_FE 0x08 /* Framing error: bad stop bit */ |
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#define LSR_PE 0x04 /* Parity error */ |
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#define LSR_OE 0x02 /* Overrun, lost incoming byte */ |
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#define LSR_RXRDY 0x01 /* Byte ready in Receive Buffer */ |
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#define LSR_RCV_MASK 0x1f /* Mask for incoming data or error */ |
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|
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/* modem status register */ |
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/* All deltas are from the last read of the MSR. */ |
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#define MSR_DCD 0x80 /* Current Data Carrier Detect */ |
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#define MSR_RI 0x40 /* Current Ring Indicator */ |
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#define MSR_DSR 0x20 /* Current Data Set Ready */ |
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#define MSR_CTS 0x10 /* Current Clear to Send */ |
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#define MSR_DDCD 0x08 /* DCD has changed state */ |
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#define MSR_TERI 0x04 /* RI has toggled low to high */ |
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#define MSR_DDSR 0x02 /* DSR has changed state */ |
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#define MSR_DCTS 0x01 /* CTS has changed state */ |
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|
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/* XXX ISA-specific. */ |
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#define COM_NPORTS 8 |
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|
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#endif /* COMREG_H */ |
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