src/include/bus_pci.h

#ifndef BUS_PCI_H
#define BUS_PCI_H

/*
 *  Copyright (C) 2004-2007  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: bus_pci.h,v 1.33 2006/12/30 13:31:00 debug Exp $
 */

#include "misc.h"
#include "pcireg.h"

struct machine;
struct memory;

struct pci_device;


#ifndef BUS_PCI_C

struct pci_data;

#else

struct pci_data {
        /*
         *  IRQ paths:
         *
         *  irq_path            Path of the controller itself.
         *  irq_path_isa        Path base of ISA interrupts.
         *  irq_path_pci        Path base of PCI interrupts.
         */
        char            *irq_path;
        char            *irq_path_isa;
        char            *irq_path_pci;

        /*
         *  Default I/O port, memory, and irq bases for PCI and legacy ISA
         *  devices, and the base address for actual (emulated) devices:
         *
         *  pci_portbase etc are what is stored in the device configuration
         *  registers. This address + pci_actual_{io,mem}_offset is where the
         *  emulated device should be registered.
         */
        uint64_t        pci_actual_io_offset;
        uint64_t        pci_actual_mem_offset;

        uint64_t        pci_portbase;
        uint64_t        pci_membase;

        uint64_t        isa_portbase;
        uint64_t        isa_membase;

        /*  Current base when allocating space for PCI devices:  */
        uint64_t        cur_pci_portbase;
        uint64_t        cur_pci_membase;

        /*  Current register access:  */
        int             cur_bus, cur_device, cur_func, cur_reg;
        int             last_was_write_ffffffff;

        struct pci_device *first_device;
};

#define PCI_CFG_MEM_SIZE        0x100

struct pci_device {
        /*  Pointer to the next PCI device on this bus:  */
        struct pci_device       *next;

        /*  Pointer back to the bus this device is connected to:  */
        struct pci_data         *pcibus;

        /*  Short device name, and bus/device/function value:  */
        char                    *name;
        int                     bus, device, function;

        /*  Configuration memory:  */
        unsigned char           cfg_mem[PCI_CFG_MEM_SIZE];
        unsigned char           cfg_mem_size[PCI_CFG_MEM_SIZE];

        /*  Used when setting up the configuration registers:  */
        int                     cur_mapreg_offset;

        /*  Function to handle device-specific cfg register writes:  */
        int                     (*cfg_reg_write)(struct pci_device *pd,
                                    int reg, uint32_t value);
        void                    *extra;
};

#define PCIINIT(name)   void pciinit_ ## name(struct machine *machine,  \
        struct memory *mem, struct pci_device *pd)

/*
 *  Store little-endian config data in the pci_data struct's cfg_mem[]
 *  or cfg_mem_size[], respectively.
 */
#define PCI_SET_DATA(ofs,value) {                                       \
        pd->cfg_mem[(ofs)]     = (value) & 255;                         \
        pd->cfg_mem[(ofs) + 1] = ((value) >> 8) & 255;                  \
        pd->cfg_mem[(ofs) + 2] = ((value) >> 16) & 255;                 \
        pd->cfg_mem[(ofs) + 3] = ((value) >> 24) & 255;                 \
        }
#define PCI_SET_DATA_SIZE(ofs,value)    {                               \
        pd->cfg_mem_size[(ofs)]     = (value) & 255;                    \
        pd->cfg_mem_size[(ofs) + 1] = ((value) >> 8) & 255;             \
        pd->cfg_mem_size[(ofs) + 2] = ((value) >> 16) & 255;            \
        pd->cfg_mem_size[(ofs) + 3] = ((value) >> 24) & 255;            \
        }

#endif

#define BUS_PCI_ADDR    0xcf8
#define BUS_PCI_DATA    0xcfc


/*
 *  bus_pci.c:
 */

/*  Run-time access:  */
void bus_pci_decompose_1(uint32_t t, int *bus, int *dev, int *func, int *reg);
void bus_pci_setaddr(struct cpu *cpu, struct pci_data *pci_data,
        int bus, int device, int function, int reg);
void bus_pci_data_access(struct cpu *cpu, struct pci_data *pci_data,
        uint64_t *data, int len, int writeflag);

/*  Initialization:  */
struct pci_data *bus_pci_init(struct machine *machine, char *irq_path,
        uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset,
        uint64_t pci_portbase, uint64_t pci_membase, char *pci_irqbase,
        uint64_t isa_portbase, uint64_t isa_membase, char *isa_irqbase);

/*  Add a PCI device to a PCI bus:  */
void bus_pci_add(struct machine *machine, struct pci_data *pci_data,
        struct memory *mem, int bus, int device, int function,
        const char *name);


#endif  /*  BUS_PCI_H  */
1	#ifndef BUS_PCI_H
2	#define BUS_PCI_H
3
4	/*
5	* Copyright (C) 2004-2007 Anders Gavare. All rights reserved.
6	*
7	* Redistribution and use in source and binary forms, with or without
8	* modification, are permitted provided that the following conditions are met:
9	*
10	* 1. Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.
12	* 2. Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	* 3. The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.
17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28	* SUCH DAMAGE.
29	*
30	*
31	* $Id: bus_pci.h,v 1.33 2006/12/30 13:31:00 debug Exp $
32	*/
33
34	#include "misc.h"
35	#include "pcireg.h"
36
37	struct machine;
38	struct memory;
39
40	struct pci_device;
41
42
43	#ifndef BUS_PCI_C
44
45	struct pci_data;
46
47	#else
48
49	struct pci_data {
50	/*
51	* IRQ paths:
52	*
53	* irq_path Path of the controller itself.
54	* irq_path_isa Path base of ISA interrupts.
55	* irq_path_pci Path base of PCI interrupts.
56	*/
57	char *irq_path;
58	char *irq_path_isa;
59	char *irq_path_pci;
60
61	/*
62	* Default I/O port, memory, and irq bases for PCI and legacy ISA
63	* devices, and the base address for actual (emulated) devices:
64	*
65	* pci_portbase etc are what is stored in the device configuration
66	* registers. This address + pci_actual_{io,mem}_offset is where the
67	* emulated device should be registered.
68	*/
69	uint64_t pci_actual_io_offset;
70	uint64_t pci_actual_mem_offset;
71
72	uint64_t pci_portbase;
73	uint64_t pci_membase;
74
75	uint64_t isa_portbase;
76	uint64_t isa_membase;
77
78	/* Current base when allocating space for PCI devices: */
79	uint64_t cur_pci_portbase;
80	uint64_t cur_pci_membase;
81
82	/* Current register access: */
83	int cur_bus, cur_device, cur_func, cur_reg;
84	int last_was_write_ffffffff;
85
86	struct pci_device *first_device;
87	};
88
89	#define PCI_CFG_MEM_SIZE 0x100
90
91	struct pci_device {
92	/* Pointer to the next PCI device on this bus: */
93	struct pci_device *next;
94
95	/* Pointer back to the bus this device is connected to: */
96	struct pci_data *pcibus;
97
98	/* Short device name, and bus/device/function value: */
99	char *name;
100	int bus, device, function;
101
102	/* Configuration memory: */
103	unsigned char cfg_mem[PCI_CFG_MEM_SIZE];
104	unsigned char cfg_mem_size[PCI_CFG_MEM_SIZE];
105
106	/* Used when setting up the configuration registers: */
107	int cur_mapreg_offset;
108
109	/* Function to handle device-specific cfg register writes: */
110	int (cfg_reg_write)(struct pci_device pd,
111	int reg, uint32_t value);
112	void *extra;
113	};
114
115	#define PCIINIT(name) void pciinit_ ## name(struct machine *machine, \
116	struct memory mem, struct pci_device pd)
117
118	/*
119	* Store little-endian config data in the pci_data struct's cfg_mem[]
120	* or cfg_mem_size[], respectively.
121	*/
122	#define PCI_SET_DATA(ofs,value) { \
123	pd->cfg_mem[(ofs)] = (value) & 255; \
124	pd->cfg_mem[(ofs) + 1] = ((value) >> 8) & 255; \
125	pd->cfg_mem[(ofs) + 2] = ((value) >> 16) & 255; \
126	pd->cfg_mem[(ofs) + 3] = ((value) >> 24) & 255; \
127	}
128	#define PCI_SET_DATA_SIZE(ofs,value) { \
129	pd->cfg_mem_size[(ofs)] = (value) & 255; \
130	pd->cfg_mem_size[(ofs) + 1] = ((value) >> 8) & 255; \
131	pd->cfg_mem_size[(ofs) + 2] = ((value) >> 16) & 255; \
132	pd->cfg_mem_size[(ofs) + 3] = ((value) >> 24) & 255; \
133	}
134
135	#endif
136
137	#define BUS_PCI_ADDR 0xcf8
138	#define BUS_PCI_DATA 0xcfc
139
140
141	/*
142	* bus_pci.c:
143	*/
144
145	/* Run-time access: */
146	void bus_pci_decompose_1(uint32_t t, int bus, int dev, int func, int reg);
147	void bus_pci_setaddr(struct cpu cpu, struct pci_data pci_data,
148	int bus, int device, int function, int reg);
149	void bus_pci_data_access(struct cpu cpu, struct pci_data pci_data,
150	uint64_t *data, int len, int writeflag);
151
152	/* Initialization: */
153	struct pci_data bus_pci_init(struct machine machine, char *irq_path,
154	uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset,
155	uint64_t pci_portbase, uint64_t pci_membase, char *pci_irqbase,
156	uint64_t isa_portbase, uint64_t isa_membase, char *isa_irqbase);
157
158	/* Add a PCI device to a PCI bus: */
159	void bus_pci_add(struct machine machine, struct pci_data pci_data,
160	struct memory *mem, int bus, int device, int function,
161	const char *name);
162
163
164	#endif /* BUS_PCI_H */