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/* gxemul: $Id: bcureg.h,v 1.2 2005/03/05 12:34:02 debug Exp $ */ |
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|
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#ifndef BCUREG_H |
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#define BCUREG_H |
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|
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/* $NetBSD: bcureg.h,v 1.8 2001/09/05 16:08:46 sato Exp $ */ |
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|
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/*- |
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* Copyright (c) 1999-2001 SATO Kazumi. All rights reserved. |
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* Copyright (c) 1999 PocketBSD Project. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed by the PocketBSD project |
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* and its contributors. |
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* 4. Neither the name of the project nor the names of its contributors |
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* may be used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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*/ |
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|
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/* |
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* BCU (Bus Control Unit) Registers definitions. |
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* start 0xB000000 (vr4101,4102,4111,4121) |
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* start 0xA000000 (vr4181) |
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* start 0xF000000 (vr4122, vr4131) |
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*/ |
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|
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#define BCUCNT1_REG_W 0x000 /* BCU Control Register 1 */ |
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|
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#define BCUCNT1_ROMMASK (1<<15) /* ROM SIZE (<= 4121,>= 4102) */ |
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#define BCUCNT1_ROM64M (1<<15) /* ROM SIZE 64Mbit*/ |
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#define BCUCNT1_ROM32M (0<<15) /* ROM SIZE 32Mbit*/ |
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|
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#define BCUCNT1_DRAMMASK (1<<14) /* DRAM SIZE (<= 4121,>= 4102) */ |
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#define BCUCNT1_DRAM64M (1<<14) /* DRAM SIZE 64Mbit*/ |
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#define BCUCNT1_DRAM32M (0<<14) /* DRAM SIZE 32Mbit*/ |
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|
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#define BCUCNT1_ROMSMASK (0x3<<14) /* ROM SIZE (=4181) */ |
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#define BCUCNT1_ROMS64M (0x2<<14) /* ROM SIZE 64Mbit */ |
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#define BCUCNT1_ROMS32M (0x1<<14) /* ROM SIZE 32Mbit */ |
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|
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#define BCUCNT1_ISAMLCD (1<<13) /* ISAM/LCD 0x0a000000 to 0xaffffff(>= 4102) */ |
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#define BCUCNT1_ISA (1<<13) /* ISA memory space */ |
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#define BCUCNT1_LCD (0<<13) /* LCD space*/ |
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|
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#define BCUCNT1_PAGEMASK (1<<12) /* Maximum burst access size for Page Rom (<= 4121,>= 4102) */ |
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#define BCUCNT1_PAGE128 (1<<12) /* 128bit */ |
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#define BCUCNT1_PAGE64 (0<<12) /* 64bit */ |
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|
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#define BCUCNT1_PAGESIZEMASK (3<<12) /* PageROM PAGESIZE (= 4122, 4131) */ |
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#define BCUCNT1_PASESIZE32 (2<<12) /* 32 byte */ |
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#define BCUCNT1_PASESIZE16 (1<<12) /* 16 byte */ |
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#define BCUCNT1_PASESIZE8 (0<<12) /* 8 byte */ |
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|
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#define BCUCNT1_PAGE2MASK (1<<10) /* (<= 4131,>= 4102) */ |
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#define BCUCNT1_PAGE2PAGE (1<<10) /* Page ROM */ |
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#define BCUCNT1_PAGE2ORD (0<<10) /* Prginary ROM */ |
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|
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#define BCUCNT1_PAGE0MASK (1<<8) /* (<= 4131,>= 4102) */ |
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#define BCUCNT1_PAGE0PAGE (1<<8) /* Page ROM */ |
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#define BCUCNT1_PAGE0ORD (0<<8) /* Prginary ROM */ |
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|
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#define BCUCNT1_REFMASK (1<<7) /* DRAM refresh interval (= 4101) */ |
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#define BCUCNT1_REF1024 (1<<7) /* 1024 cycles/128ms */ |
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#define BCUCNT1_REF4096 (0<<7) /* 4096 cycles/128ms */ |
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|
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#define BCUCNT1_ROMWEN2 (1<<6) /* Enable Flash memory write ROM 2 (<= 4131,>= 4102) */ |
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#define BCUCNT1_ROMWEN2EN (1<<6) /* Enable */ |
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#define BCUCNT1_ROMWEN2DS (0<<6) /* Prohibit */ |
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|
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#define BCUCNT1_PAGEROM (1<<6) /* Enable page ROM access (= 4101) */ |
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#define BCUCNT1_PAGEROMEN (1<<6) /* Page ROM */ |
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#define BCUCNT1_PAGEROMDIS (0<<6) /* not Page ROM */ |
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|
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#define BCUCNT1_ROMWEN (1<<5) /* Enable Flash memory write ROM 0 (= 4101) */ |
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#define BCUCNT1_ROMWENEN (1<<5) /* Enable */ |
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#define BCUCNT1_ROMWENDS (0<<5) /* Prohibit */ |
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|
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#define BCUCNT1_ROMWEN0 (1<<4) /* Enable Flash memory write ROM 0 (<= 4131,>= 4102, =4181) */ |
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#define BCUCNT1_ROMWEN0EN (1<<4) /* Enable */ |
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#define BCUCNT1_ROMWEN0DS (0<<4) /* Prohibit */ |
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|
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#define BCUCNT1_SRFSTAT (1<<4) /* DRAM refresh mode (= 4101) */ |
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#define BCUCNT1_SRFSTATSRF (1<<4) /* self refresh */ |
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#define BCUCNT1_SRFSTATCBR (0<<4) /* CBR refresh */ |
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|
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#define BCUCNT1_BCPUR (1<<3) /* CPU bus cycle control (= 4101) */ |
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#define BCUCNT1_BCPUREN (1<<3) /* CPU bus cycle control enable */ |
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#define BCUCNT1_BCPURDIS (0<<3) /* CPU bus cycle control disable */ |
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|
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#define BCUCNT1_HLD (1<<2) /* Bus hold enable (= 4122, 4131) */ |
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#define BCUCNT1_HLDEN (1<<2) /* enable */ |
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#define BCUCNT1_HLDDIS (1<<2) /* disable */ |
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|
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#define BCUCNT1_BUSHERR (1<<1) /* Bus Timeout detection enable (<= 4121,>= 4102) */ |
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|
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#define BCUCNT1_BUSHERREN (1<<1) /* Enable */ |
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#define BCUCNT1_BUSHERRDS (0<<1) /* Prohibit */ |
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|
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#define BCUCNT1_RTYPE (0x3<<1) /* ROM type (=4181) */ |
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#define BCUCNT1_RTOROM (0<<1) /* Odinary ROM */ |
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#define BCUCNT1_RTFLASH (1<<1) /* flash ROM */ |
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#define BCUCNT1_RTPAGEROM (2<<1) /* Page ROM */ |
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|
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#define BCUCNT1_RSTOUT (1) /* RSTOUT control bit */ |
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#define BCUCNT1_RSTOUTH (1) /* RSTOUT high level*/ |
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#define BCUCNT1_RSTOUTL (0) /* RSTOUT low level*/ |
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|
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|
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#define BCUCNT2_REG_W 0x002 /* BCU Control Register 2 (<= 4121,>= 4102, =4181) */ |
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|
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#define BCUCNT2_GMODE (1) /* LCD access control */ |
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#define BCUCNT2_GMODENOM (1) /* not invert LCD */ |
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#define BCUCNT2_GMODEINV (0) /* invert LCD */ |
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|
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#define BCUBR_REG_W 0x002 /* BCU Bus Restrain Register (= 4101) */ |
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|
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#define BCUROMSIZE_REG_W 0x004 /* ROM size setting register (= 4122, 4131) */ |
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#define BCUROMSIZE_SIZE3 (7<<12) /* Bank3 size */ |
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#define BCUROMSIZE_SIZE3_64 (5<<12) /* 64MB */ |
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#define BCUROMSIZE_SIZE3_32 (4<<12) /* 32MB */ |
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#define BCUROMSIZE_SIZE3_16 (3<<12) /* 16MB */ |
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#define BCUROMSIZE_SIZE3_8 (2<<12) /* 8MB */ |
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#define BCUROMSIZE_SIZE3_4 (1<<12) /* 4MB */ |
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|
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#define BCUROMSIZE_SIZE2 (7<<8) /* Bank2 size */ |
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#define BCUROMSIZE_SIZE2_64 (5<<8) /* 64MB */ |
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#define BCUROMSIZE_SIZE2_32 (4<<8) /* 32MB */ |
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#define BCUROMSIZE_SIZE2_16 (3<<8) /* 16MB */ |
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#define BCUROMSIZE_SIZE2_8 (2<<8) /* 8MB */ |
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#define BCUROMSIZE_SIZE2_4 (1<<8) /* 4MB */ |
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|
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#define BCUROMSIZE_SIZE1 (7<<4) /* Bank1 size */ |
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#define BCUROMSIZE_SIZE1_64 (5<<4) /* 64MB */ |
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#define BCUROMSIZE_SIZE1_32 (4<<4) /* 32MB */ |
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#define BCUROMSIZE_SIZE1_16 (3<<4) /* 16MB */ |
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#define BCUROMSIZE_SIZE1_8 (2<<4) /* 8MB */ |
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#define BCUROMSIZE_SIZE1_4 (1<<4) /* 4MB */ |
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|
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#define BCUROMSIZE_SIZE0 (7) /* Bank0 size */ |
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#define BCUROMSIZE_SIZE0_64 (5) /* 64MB */ |
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#define BCUROMSIZE_SIZE0_32 (4) /* 32MB */ |
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#define BCUROMSIZE_SIZE0_16 (3) /* 16MB */ |
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#define BCUROMSIZE_SIZE0_8 (2) /* 8MB */ |
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#define BCUROMSIZE_SIZE0_4 (1) /* 4MB */ |
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|
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#define BCUBRCNT_REG_W 0x004 /* BCU Bus Restrain Count Register (= 4101) */ |
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|
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#define BCUROMSPEED_REG_W 0x006 /* BCU ROM Speed Register (=4122, 4131) */ |
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#define BCUROMSPEED_PATIME (0x3<<12) /* Page Access time */ |
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#define BCUROMSPEED_PATIME_5VT (0x3<<12) /* 5VTClock */ |
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#define BCUROMSPEED_PATIME_4VT (0x2<<12) /* 4VTClock */ |
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#define BCUROMSPEED_PATIME_3VT (0x1<<12) /* 3VTClock */ |
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#define BCUROMSPEED_PATIME_2VT (0x0<<12) /* 2VTClock */ |
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|
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#define BCUROMSPEED_ATIME (0xf) /* Access time */ |
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#define BCUROMSPEED_ATIME_18VT (0xf) /* 18VTClock */ |
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#define BCUROMSPEED_ATIME_17VT (0xe) /* 17VTClock */ |
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#define BCUROMSPEED_ATIME_16VT (0xd) /* 16VTClock */ |
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#define BCUROMSPEED_ATIME_15VT (0xc) /* 15VTClock */ |
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#define BCUROMSPEED_ATIME_14VT (0xb) /* 14VTClock */ |
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#define BCUROMSPEED_ATIME_13VT (0xa) /* 13VTClock */ |
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#define BCUROMSPEED_ATIME_12VT (0x9) /* 12VTClock */ |
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#define BCUROMSPEED_ATIME_11VT (0x8) /* 11VTClock */ |
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#define BCUROMSPEED_ATIME_10VT (0x7) /* 10VTClock */ |
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#define BCUROMSPEED_ATIME_9VT (0x6) /* 9VTClock */ |
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#define BCUROMSPEED_ATIME_8VT (0x5) /* 8VTClock */ |
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#define BCUROMSPEED_ATIME_7VT (0x4) /* 7VTClock */ |
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#define BCUROMSPEED_ATIME_6VT (0x3) /* 6VTClock */ |
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#define BCUROMSPEED_ATIME_5VT (0x2) /* 5VTClock */ |
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#define BCUROMSPEED_ATIME_4VT (0x1) /* 4VTClock */ |
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#define BCUROMSPEED_ATIME_3VT (0x0) /* 3VTClock */ |
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|
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#define BCUBCL_REG_W 0x006 /* BCU CPU Restrain Disable Register (= 4101) */ |
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|
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#define BCUIO0SPEED_REG_W 0x008 /* BCU IO0 Speed Register (=4122, 4131) */ |
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#define BCUIO0SPEED_RWCS (0x3<<12) /* R/W - CS time */ |
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#define BCUIO0SPEED_RWCS_5VT (0x3<<12) /* 5VTClock */ |
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#define BCUIO0SPEED_RWCS_4VT (0x2<<12) /* 4VTClock */ |
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#define BCUIO0SPEED_RWCS_3VT (0x1<<12) /* 3VTClock */ |
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#define BCUIO0SPEED_RWCS_2VT (0x0<<12) /* 2VTClock */ |
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|
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#define BCUIO0SPEED_RDYRW (0xf<<8) /* IORDY-R/W time */ |
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#define BCUIO0SPEED_RDYRW_18VT (0xf) /* 18VTClock */ |
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#define BCUIO0SPEED_RDYRW_17VT (0xe) /* 17VTClock */ |
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#define BCUIO0SPEED_RDYRW_16VT (0xd) /* 16VTClock */ |
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#define BCUIO0SPEED_RDYRW_15VT (0xc) /* 15VTClock */ |
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#define BCUIO0SPEED_RDYRW_14VT (0xb) /* 14VTClock */ |
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#define BCUIO0SPEED_RDYRW_13VT (0xa) /* 13VTClock */ |
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#define BCUIO0SPEED_RDYRW_12VT (0x9) /* 12VTClock */ |
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#define BCUIO0SPEED_RDYRW_11VT (0x8) /* 11VTClock */ |
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#define BCUIO0SPEED_RDYRW_10VT (0x7) /* 10VTClock */ |
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#define BCUIO0SPEED_RDYRW_9VT (0x6) /* 9VTClock */ |
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#define BCUIO0SPEED_RDYRW_8VT (0x5) /* 8VTClock */ |
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#define BCUIO0SPEED_RDYRW_7VT (0x4) /* 7VTClock */ |
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#define BCUIO0SPEED_RDYRW_6VT (0x3) /* 6VTClock */ |
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#define BCUIO0SPEED_RDYRW_5VT (0x2) /* 5VTClock */ |
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#define BCUIO0SPEED_RDYRW_4VT (0x1) /* 4VTClock */ |
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#define BCUIO0SPEED_RDYRW_3VT (0x0) /* 3VTClock */ |
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|
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#define BCUIO0SPEED_RWRDY (0xf<<4) /* R/W-IORDY time */ |
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#define BCUIO0SPEED_RWRDY_14VT (0xf) /* 14VTClock */ |
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#define BCUIO0SPEED_RWRDY_13VT (0xe) /* 13VTClock */ |
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#define BCUIO0SPEED_RWRDY_12VT (0xd) /* 12VTClock */ |
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#define BCUIO0SPEED_RWRDY_11VT (0xc) /* 11VTClock */ |
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#define BCUIO0SPEED_RWRDY_10VT (0xb) /* 10VTClock */ |
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#define BCUIO0SPEED_RWRDY_9VT (0xa) /* 9VTClock */ |
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#define BCUIO0SPEED_RWRDY_8VT (0x9) /* 8VTClock */ |
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#define BCUIO0SPEED_RWRDY_7VT (0x8) /* 7VTClock */ |
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#define BCUIO0SPEED_RWRDY_6VT (0x7) /* 6VTClock */ |
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#define BCUIO0SPEED_RWRDY_5VT (0x6) /* 5VTClock */ |
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#define BCUIO0SPEED_RWRDY_4VT (0x5) /* 4VTClock */ |
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#define BCUIO0SPEED_RWRDY_3VT (0x4) /* 3VTClock */ |
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#define BCUIO0SPEED_RWRDY_2VT (0x3) /* 2VTClock */ |
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#define BCUIO0SPEED_RWRDY_1VT (0x2) /* 1VTClock */ |
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#define BCUIO0SPEED_RWRDY_0VT (0x1) /* 0VTClock */ |
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#define BCUIO0SPEED_RWRDY_M1VT (0x0) /* -1VTClock */ |
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|
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#define BCUIO0SPEED_CSRW (0xf<<0) /* IORDY-R/W time */ |
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#define BCUIO0SPEED_CSRW_16VT (0xf) /* 16VTClock */ |
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#define BCUIO0SPEED_CSRW_15VT (0xe) /* 15VTClock */ |
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#define BCUIO0SPEED_CSRW_14VT (0xd) /* 14VTClock */ |
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#define BCUIO0SPEED_CSRW_13VT (0xc) /* 13VTClock */ |
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#define BCUIO0SPEED_CSRW_12VT (0xb) /* 12VTClock */ |
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#define BCUIO0SPEED_CSRW_11VT (0xa) /* 11VTClock */ |
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#define BCUIO0SPEED_CSRW_10VT (0x9) /* 10VTClock */ |
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#define BCUIO0SPEED_CSRW_9VT (0x8) /* 9VTClock */ |
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#define BCUIO0SPEED_CSRW_8VT (0x7) /* 8VTClock */ |
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#define BCUIO0SPEED_CSRW_7VT (0x6) /* 7VTClock */ |
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#define BCUIO0SPEED_CSRW_6VT (0x5) /* 6VTClock */ |
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#define BCUIO0SPEED_CSRW_5VT (0x4) /* 5VTClock */ |
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#define BCUIO0SPEED_CSRW_4VT (0x3) /* 4VTClock */ |
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#define BCUIO0SPEED_CSRW_3VT (0x2) /* 3VTClock */ |
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#define BCUIO0SPEED_CSRW_2VT (0x1) /* 2VTClock */ |
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#define BCUIO0SPEED_CSRW_1VT (0x0) /* 1VTClock */ |
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|
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#define BCUBCLCNT_REG_W 0x008 /* BCU CPU Restrain Disable Count Register (= 4101) */ |
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|
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#define BCUIO1SPEED_REG_W 0x00A /* BCU IO1 Speed Register (=4122, 4131) */ |
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#define BCUIO1SPEED_RWCS (0x3<<12) /* R/W - CS time */ |
| 262 |
#define BCUIO1SPEED_RWCS_5VT (0x3<<12) /* 5VTClock */ |
| 263 |
#define BCUIO1SPEED_RWCS_4VT (0x2<<12) /* 4VTClock */ |
| 264 |
#define BCUIO1SPEED_RWCS_3VT (0x1<<12) /* 3VTClock */ |
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#define BCUIO1SPEED_RWCS_2VT (0x0<<12) /* 2VTClock */ |
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|
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#define BCUIO1SPEED_RDYRW (0xf<<8) /* IORDY-R/W time */ |
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#define BCUIO1SPEED_RDYRW_18VT (0xf) /* 18VTClock */ |
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#define BCUIO1SPEED_RDYRW_17VT (0xe) /* 17VTClock */ |
| 270 |
#define BCUIO1SPEED_RDYRW_16VT (0xd) /* 16VTClock */ |
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#define BCUIO1SPEED_RDYRW_15VT (0xc) /* 15VTClock */ |
| 272 |
#define BCUIO1SPEED_RDYRW_14VT (0xb) /* 14VTClock */ |
| 273 |
#define BCUIO1SPEED_RDYRW_13VT (0xa) /* 13VTClock */ |
| 274 |
#define BCUIO1SPEED_RDYRW_12VT (0x9) /* 12VTClock */ |
| 275 |
#define BCUIO1SPEED_RDYRW_11VT (0x8) /* 11VTClock */ |
| 276 |
#define BCUIO1SPEED_RDYRW_10VT (0x7) /* 10VTClock */ |
| 277 |
#define BCUIO1SPEED_RDYRW_9VT (0x6) /* 9VTClock */ |
| 278 |
#define BCUIO1SPEED_RDYRW_8VT (0x5) /* 8VTClock */ |
| 279 |
#define BCUIO1SPEED_RDYRW_7VT (0x4) /* 7VTClock */ |
| 280 |
#define BCUIO1SPEED_RDYRW_6VT (0x3) /* 6VTClock */ |
| 281 |
#define BCUIO1SPEED_RDYRW_5VT (0x2) /* 5VTClock */ |
| 282 |
#define BCUIO1SPEED_RDYRW_4VT (0x1) /* 4VTClock */ |
| 283 |
#define BCUIO1SPEED_RDYRW_3VT (0x0) /* 3VTClock */ |
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|
| 285 |
#define BCUIO1SPEED_RWRDY (0xf<<4) /* R/W-IORDY time */ |
| 286 |
#define BCUIO1SPEED_RWRDY_14VT (0xf) /* 14VTClock */ |
| 287 |
#define BCUIO1SPEED_RWRDY_13VT (0xe) /* 13VTClock */ |
| 288 |
#define BCUIO1SPEED_RWRDY_12VT (0xd) /* 12VTClock */ |
| 289 |
#define BCUIO1SPEED_RWRDY_11VT (0xc) /* 11VTClock */ |
| 290 |
#define BCUIO1SPEED_RWRDY_10VT (0xb) /* 10VTClock */ |
| 291 |
#define BCUIO1SPEED_RWRDY_9VT (0xa) /* 9VTClock */ |
| 292 |
#define BCUIO1SPEED_RWRDY_8VT (0x9) /* 8VTClock */ |
| 293 |
#define BCUIO1SPEED_RWRDY_7VT (0x8) /* 7VTClock */ |
| 294 |
#define BCUIO1SPEED_RWRDY_6VT (0x7) /* 6VTClock */ |
| 295 |
#define BCUIO1SPEED_RWRDY_5VT (0x6) /* 5VTClock */ |
| 296 |
#define BCUIO1SPEED_RWRDY_4VT (0x5) /* 4VTClock */ |
| 297 |
#define BCUIO1SPEED_RWRDY_3VT (0x4) /* 3VTClock */ |
| 298 |
#define BCUIO1SPEED_RWRDY_2VT (0x3) /* 2VTClock */ |
| 299 |
#define BCUIO1SPEED_RWRDY_1VT (0x2) /* 1VTClock */ |
| 300 |
#define BCUIO1SPEED_RWRDY_0VT (0x1) /* 0VTClock */ |
| 301 |
#define BCUIO1SPEED_RWRDY_M1VT (0x0) /* -1VTClock */ |
| 302 |
|
| 303 |
#define BCUIO1SPEED_CSRW (0xf<<0) /* IORDY-R/W time */ |
| 304 |
#define BCUIO1SPEED_CSRW_16VT (0xf) /* 16VTClock */ |
| 305 |
#define BCUIO1SPEED_CSRW_15VT (0xe) /* 15VTClock */ |
| 306 |
#define BCUIO1SPEED_CSRW_14VT (0xd) /* 14VTClock */ |
| 307 |
#define BCUIO1SPEED_CSRW_13VT (0xc) /* 13VTClock */ |
| 308 |
#define BCUIO1SPEED_CSRW_12VT (0xb) /* 12VTClock */ |
| 309 |
#define BCUIO1SPEED_CSRW_11VT (0xa) /* 11VTClock */ |
| 310 |
#define BCUIO1SPEED_CSRW_10VT (0x9) /* 10VTClock */ |
| 311 |
#define BCUIO1SPEED_CSRW_9VT (0x8) /* 9VTClock */ |
| 312 |
#define BCUIO1SPEED_CSRW_8VT (0x7) /* 8VTClock */ |
| 313 |
#define BCUIO1SPEED_CSRW_7VT (0x6) /* 7VTClock */ |
| 314 |
#define BCUIO1SPEED_CSRW_6VT (0x5) /* 6VTClock */ |
| 315 |
#define BCUIO1SPEED_CSRW_5VT (0x4) /* 5VTClock */ |
| 316 |
#define BCUIO1SPEED_CSRW_4VT (0x3) /* 4VTClock */ |
| 317 |
#define BCUIO1SPEED_CSRW_3VT (0x2) /* 3VTClock */ |
| 318 |
#define BCUIO1SPEED_CSRW_2VT (0x1) /* 2VTClock */ |
| 319 |
#define BCUIO1SPEED_CSRW_1VT (0x0) /* 1VTClock */ |
| 320 |
|
| 321 |
#define BCUSPEED_REG_W 0x00A /* BCU Access Cycle Change Register (4121>=4102)*/ |
| 322 |
|
| 323 |
#define BCUSPD_WPROM (0x3<<12) /* Page ROM access speed */ |
| 324 |
#define BCUSPD_WPROMRFU (0x3<<12) /* RFU */ |
| 325 |
#define BCUSPD_WPROM1T (0x2<<12) /* 1TClock */ |
| 326 |
#define BCUSPD_WPROM2T (0x1<<12) /* 2TClock */ |
| 327 |
#define BCUSPD_WPROM3T (0x0<<12) /* 3TClock */ |
| 328 |
|
| 329 |
#define BCUSPD_WLCDM (0x7<<8) /* access speed 0x0a000000-0affffff */ |
| 330 |
|
| 331 |
/* BCUCNT1_ISAMLCD == BCUCNT1_LCD */ |
| 332 |
#define BCUSPD_WLCDRFU (0x7<<8) /* LCD RFU */ |
| 333 |
#define BCUSPD_WLCDRFU1 (0x6<<8) /* LCD RFU */ |
| 334 |
#define BCUSPD_WLCDRFU2 (0x5<<8) /* LCD RFU */ |
| 335 |
#define BCUSPD_WLCDRFU3 (0x4<<8) /* LCD RFU */ |
| 336 |
#define BCUSPD_WLCD2T (0x3<<8) /* LCD 2TClock */ |
| 337 |
#define BCUSPD_WLCD4T (0x2<<8) /* LCD 4TClock */ |
| 338 |
#define BCUSPD_WLCD6T (0x1<<8) /* LCD 6TClock */ |
| 339 |
#define BCUSPD_WLCD8T (0x0<<8) /* LCD 8TClock */ |
| 340 |
/* BCUCNT1_ISAMLCD == BCUCNT1_ISAM */ |
| 341 |
#define BCUSPD_ISAM1T (0x7<<8) /* ISAM 1TClock */ |
| 342 |
#define BCUSPD_ISAM2T (0x6<<8) /* ISAM 2TClock */ |
| 343 |
#define BCUSPD_ISAM3T (0x5<<8) /* ISAM 3TClock */ |
| 344 |
#define BCUSPD_ISAM4T (0x4<<8) /* ISAM 4TClock */ |
| 345 |
#define BCUSPD_ISAM5T (0x3<<8) /* ISAM 5TClock */ |
| 346 |
#define BCUSPD_ISAM6T (0x2<<8) /* ISAM 6TClock */ |
| 347 |
#define BCUSPD_ISAM7T (0x1<<8) /* ISAM 7TClock */ |
| 348 |
#define BCUSPD_ISAM8T (0x0<<8) /* ISAM 8TClock */ |
| 349 |
|
| 350 |
#define BCUSPD_WISAA (0x7<<4) /* System Bus Access Speed */ |
| 351 |
#define BCUSPD_WISAA3T (0x5<<4) /* 3TClock */ |
| 352 |
#define BCUSPD_WISAA4T (0x4<<4) /* 4TClock */ |
| 353 |
#define BCUSPD_WISAA5T (0x3<<4) /* 5TClock */ |
| 354 |
#define BCUSPD_WISAA6T (0x2<<4) /* 6TClock */ |
| 355 |
#define BCUSPD_WISAA7T (0x1<<4) /* 7TClock */ |
| 356 |
#define BCUSPD_WISAA8T (0x0<<4) /* 8TClock */ |
| 357 |
|
| 358 |
#define BCUSPD_WROMA (0x7<<0) /* System Bus Access Speed */ |
| 359 |
#define BCUSPD_WROMA2T (0x7<<0) /* 2TClock */ |
| 360 |
#define BCUSPD_WROMA3T (0x6<<0) /* 3TClock */ |
| 361 |
#define BCUSPD_WROMA4T (0x5<<0) /* 4TClock */ |
| 362 |
#define BCUSPD_WROMA5T (0x4<<0) /* 5TClock */ |
| 363 |
#define BCUSPD_WROMA6T (0x3<<0) /* 6TClock */ |
| 364 |
#define BCUSPD_WROMA7T (0x2<<0) /* 7TClock */ |
| 365 |
#define BCUSPD_WROMA8T (0x1<<0) /* 8TClock */ |
| 366 |
#define BCUSPD_WROMA9T (0x0<<0) /* 9TClock */ |
| 367 |
|
| 368 |
|
| 369 |
#define BCUERRST_REG_W 0x00C /* BCU BUS ERROR Status Register (4121>=4102)*/ |
| 370 |
|
| 371 |
#define BCUERRST_BUSERRMASK (1) /* Bus error, clear to 0 when 1 is written */ |
| 372 |
#define BCUERRST_BUSERR (1) /* Bus error */ |
| 373 |
#define BCUERRST_BUSNORM (0) /* Normal */ |
| 374 |
|
| 375 |
#define BCU81SPEED_REG_W 0x00C /* BCU Access Cycle Change Register (=4181)*/ |
| 376 |
|
| 377 |
#define BCU81SPD_WPROM (0x7<<12) /* Page ROM access speed */ |
| 378 |
#define BCU81SPD_WPROM8T (0x7<<12) /* 8TClock */ |
| 379 |
#define BCU81SPD_WPROM7T (0x6<<12) /* 7TClock */ |
| 380 |
#define BCU81SPD_WPROM6T (0x5<<12) /* 6TClock */ |
| 381 |
#define BCU81SPD_WPROM5T (0x4<<12) /* 5TClock */ |
| 382 |
#define BCU81SPD_WPROM4T (0x3<<12) /* 4TClock */ |
| 383 |
#define BCU81SPD_WPROM3T (0x2<<12) /* 3TClock */ |
| 384 |
#define BCU81SPD_WPROM2T (0x1<<12) /* 2TClock */ |
| 385 |
#define BCU81SPD_WPROM1T (0x0<<12) /* 1TClock */ |
| 386 |
|
| 387 |
#define BCU81SPD_WROMA (0xf<<0) /* System Bus Access Speed */ |
| 388 |
#define BCU81SPD_WROMA16T (0xf<<0) /* 16TClock */ |
| 389 |
#define BCU81SPD_WROMA15T (0xe<<0) /* 15TClock */ |
| 390 |
#define BCU81SPD_WROMA14T (0xd<<0) /* 14TClock */ |
| 391 |
#define BCU81SPD_WROMA13T (0xc<<0) /* 13TClock */ |
| 392 |
#define BCU81SPD_WROMA12T (0xb<<0) /* 12TClock */ |
| 393 |
#define BCU81SPD_WROMA11T (0xa<<0) /* 11TClock */ |
| 394 |
#define BCU81SPD_WROMA10T (0x9<<0) /* 10TClock */ |
| 395 |
#define BCU81SPD_WROMA9T (0x8<<0) /* 9TClock */ |
| 396 |
#define BCU81SPD_WROMA8T (0x7<<0) /* 8TClock */ |
| 397 |
#define BCU81SPD_WROMA7T (0x6<<0) /* 7TClock */ |
| 398 |
#define BCU81SPD_WROMA6T (0x5<<0) /* 6TClock */ |
| 399 |
#define BCU81SPD_WROMA5T (0x4<<0) /* 5TClock */ |
| 400 |
#define BCU81SPD_WROMA4T (0x3<<0) /* 4TClock */ |
| 401 |
#define BCU81SPD_WROMA3T (0x2<<0) /* 3TClock */ |
| 402 |
#define BCU81SPD_WROMA2T (0x1<<0) /* 2TClock */ |
| 403 |
#define BCU81SPD_WROMA1T (0x0<<0) /* 1TClock */ |
| 404 |
|
| 405 |
#define BCURFCNT_REG_W 0x00E /* BCU Refresh Control Register(4121>=4102) */ |
| 406 |
#define BCU81RFCNT_REG_W 0x010 /* BCU Refresh Control Register(=4181) */ |
| 407 |
|
| 408 |
#define BCURFCNT_MASK 0x3fff /* refresh interval MASK */ |
| 409 |
|
| 410 |
#define BCUREVID_REG_W 0x010 /* BCU Revision ID Register (4122>=4101)*/ |
| 411 |
#define BCU81REVID_REG_W 0x014 /* BCU Revision ID Register (=4181)*/ |
| 412 |
|
| 413 |
#define BCUREVID_RIDMASK (0xf<<12) /* Revision ID */ |
| 414 |
#define BCUREVID_RIDSHFT (12) /* Revision ID */ |
| 415 |
#define BCUREVID_RID_4131 (0x5) /* VR4131 */ |
| 416 |
#define BCUREVID_RID_4122 (0x4) /* VR4122 */ |
| 417 |
#define BCUREVID_RID_4121 (0x3) /* VR4121 */ |
| 418 |
#define BCUREVID_RID_4111 (0x2) /* VR4111 */ |
| 419 |
#define BCUREVID_RID_4102 (0x1) /* VR4102 */ |
| 420 |
#define BCUREVID_RID_4101 (0x0) /* VR4101 */ |
| 421 |
#define BCUREVID_RID_4181 (0x0) /* VR4181 conflict VR4101 */ |
| 422 |
#define BCUREVID_FIXRID_OFF (0x10) /* conflict offset */ |
| 423 |
#define BCUREVID_FIXRID_4181 (0x10) /* VR4181 for kernel */ |
| 424 |
|
| 425 |
#define BCUREVID_MJREVMASK (0xf<<8) /* Major Revision */ |
| 426 |
#define BCUREVID_MJREVSHFT (8) /* Major Revision */ |
| 427 |
|
| 428 |
#define BCUREVID_MNREVMASK (0xf) /* Minor Revision */ |
| 429 |
#define BCUREVID_MNREVSHFT (0) /* Minor Revision */ |
| 430 |
|
| 431 |
|
| 432 |
#define BCUREFCOUNT_REG_W 0x012 /* BCU Refresh Count Register (>= 4102) */ |
| 433 |
|
| 434 |
#define BCUREFCOUNT_MASK 0x3fff /* refresh count MASK */ |
| 435 |
|
| 436 |
|
| 437 |
#define BCUCLKSPEED_REG_W 0x014 /* Clock Speed Register (>= 4102) */ |
| 438 |
#define BCU81CLKSPEED_REG_W 0x018 /* Clock Speed Register (= 4181) */ |
| 439 |
|
| 440 |
#define BCUCLKSPEED_DIVT2B (1<<15) /* (= 4102, 4111) */ |
| 441 |
#define BCUCLKSPEED_DIVT3B (1<<14) /* (= 4111) */ |
| 442 |
#define BCUCLKSPEED_DIVT4B (1<<13) /* (= 4111) */ |
| 443 |
|
| 444 |
#define BCUCLKSPEED_DIVTMASK (0xf<<12) /* (= 4121) */ |
| 445 |
#define BCUCLKSPEED_DIVT3 0x3 |
| 446 |
#define BCUCLKSPEED_DIVT4 0x4 |
| 447 |
#define BCUCLKSPEED_DIVT5 0x5 |
| 448 |
#define BCUCLKSPEED_DIVT6 0x6 |
| 449 |
#define BCUCLKSPEED_DIVTSHFT (12) |
| 450 |
|
| 451 |
#define BCUCLKSPEED_TDIVMODE (0x1<<12) /* (= 4122, 4131) */ |
| 452 |
#define BCUCLKSPEED_TDIV4 0x1 |
| 453 |
#define BCUCLKSPEED_TDIV2 0x0 |
| 454 |
#define BCUCLKSPEED_TDIVSHFT (12) |
| 455 |
|
| 456 |
#define BCU81CLKSPEED_DIVTMASK (0x7<<12) /* (=4181) */ |
| 457 |
#define BCU81CLKSPEED_DIVT1 0x7 |
| 458 |
#define BCU81CLKSPEED_DIVT2 0x3 |
| 459 |
#define BCU81CLKSPEED_DIVT3 0x5 |
| 460 |
#define BCU81CLKSPEED_DIVT4 0x6 |
| 461 |
#define BCU81CLKSPEED_DIVTSHFT (12) |
| 462 |
|
| 463 |
#define BCUCLKSPEED_DIVVTMASK (0xf<<8) /* (= 4121) */ |
| 464 |
#define BCUCLKSPEED_DIVVT1 0x1 |
| 465 |
#define BCUCLKSPEED_DIVVT2 0x2 |
| 466 |
#define BCUCLKSPEED_DIVVT3 0x3 |
| 467 |
#define BCUCLKSPEED_DIVVT4 0x4 |
| 468 |
#define BCUCLKSPEED_DIVVT5 0x5 |
| 469 |
#define BCUCLKSPEED_DIVVT6 0x6 |
| 470 |
#define BCUCLKSPEED_DIVVT1_5 0x9 |
| 471 |
#define BCUCLKSPEED_DIVVT2_5 0xa |
| 472 |
#define BCUCLKSPEED_DIVVTSHFT (8) |
| 473 |
|
| 474 |
#define BCUCLKSPEED_VTDIVMODE (0x7<<8) /* (= 4122, 4131) */ |
| 475 |
#define BCUCLKSPEED_VTDIV6 0x6 |
| 476 |
#define BCUCLKSPEED_VTDIVT5 0x5 |
| 477 |
#define BCUCLKSPEED_VTDIVT4 0x4 |
| 478 |
#define BCUCLKSPEED_VTDIVT3 0x3 |
| 479 |
#define BCUCLKSPEED_VTDIVT2 0x2 |
| 480 |
#define BCUCLKSPEED_VTDIVT1 0x1 |
| 481 |
#define BCUCLKSPEED_VTDIVSHFT (8) |
| 482 |
|
| 483 |
#define BCUCLKSPEED_CLKSPMASK (0x1f) /* calculate for Clock */ |
| 484 |
#define BCUCLKSPEED_CLKSPSHFT (0) |
| 485 |
|
| 486 |
#define BCUCNT3_REG_W 0x016 /* BCU Control Register 3 (>= 4111) */ |
| 487 |
|
| 488 |
#define BCUCNT3_EXTROMMASK (1<<15) /* ROM SIZE (4111,4121)*/ |
| 489 |
#define BCUCNT3_EXTROM64M (1<<15) /* 64Mbit DRAM */ |
| 490 |
#define BCUCNT3_EXTROM32M (0<<15) /* 32Mbit DRAM */ |
| 491 |
|
| 492 |
#define BCUCNT3_EXTDRAMMASK (1<<14) /* DRAM SIZE (4111,4121)*/ |
| 493 |
#define BCUCNT3_EXTDRAM64M (1<<14) /* 64Mbit DRAM */ |
| 494 |
#define BCUCNT3_EXTDRAM16M (0<<14) /* 16Mbit DRAM */ |
| 495 |
|
| 496 |
#define BCUCNT3_EXTROMCS (0x3<<12) /* Bank3,2 */ |
| 497 |
#define BCUCNT3_ROMROM (0x3<<12) /* Bank3 ROM ,2 ROM */ |
| 498 |
#define BCUCNT3_ROMRAM (0x2<<12) /* Bank3 ROM ,2 RAM */ |
| 499 |
#define BCUCNT3_RAMRAM (0x0<<12) /* Bank3 RAM ,2 RAM */ |
| 500 |
|
| 501 |
#define BCUCNT3_EXTMEM (1<<11) /* EXT MEN enable (4111,4121)*/ |
| 502 |
#define BCUCNT3_EXTMEMEN (1<<11) /* EXT MEN enable */ |
| 503 |
#define BCUCNT3_EXTMEMDS (0<<11) /* EXT MEN disable */ |
| 504 |
|
| 505 |
#define BCUCNT3_LCDSIZE (1<<7) /* LCD bus size */ |
| 506 |
#define BCUCNT3_LCD32 (1<<7) /* LCD bus 32bit */ |
| 507 |
#define BCUCNT3_LCD16 (0<<7) /* LCD bus 16bit */ |
| 508 |
|
| 509 |
#define BCUCNT3_SYSDIREN (1<<3) /* SYSDIR or GPIO6(=4122, 4131)*/ |
| 510 |
#define BCUCNT3_SYSDIR (1<<3) /* SYSDIR */ |
| 511 |
#define BCUCNT3_GPIO6 (0<<3) /* GPIO6 */ |
| 512 |
|
| 513 |
#define BCUCNT3_LCDSEL1 (1<<1) /* 0xc00-0xdff area buffer (=4122)*/ |
| 514 |
#define BCUCNT3_LCDSEL1_NOBUF (1<<1) /* nobuffer */ |
| 515 |
#define BCUCNT3_LCDSEL1_BUF (0<<1) /* buffer */ |
| 516 |
|
| 517 |
#define BCUCNT3_LCDSEL0 (1<<1) /* 0xa00-0xbff area buffer (=4122)*/ |
| 518 |
#define BCUCNT3_LCDSEL0_NOBUF (1<<1) /* nobuffer */ |
| 519 |
#define BCUCNT3_LCDSEL0_BUF (0<<1) /* buffer */ |
| 520 |
|
| 521 |
#endif /* BCUREG_H */ |
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