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dpavlin |
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/* GXemul: $Id: adb_viareg.h,v 1.1 2005/11/29 05:25:29 debug Exp $ */ |
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/* $NetBSD: viareg.h,v 1.4 2001/06/19 12:02:56 simonb Exp $ */ |
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#ifndef ADB_VIAREG_H |
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#define ADB_VIAREG_H |
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/*- |
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* Copyright (C) 1993 Allen K. Briggs, Chris P. Caputo, |
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* Michael L. Finch, Bradley A. Grantham, and |
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* Lawrence A. Kesteloot |
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* All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed by the Alice Group. |
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* 4. The names of the Alice Group or any of its members may not be used |
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* to endorse or promote products derived from this software without |
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* specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE ALICE GROUP ``AS IS'' AND ANY EXPRESS OR |
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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* IN NO EVENT SHALL THE ALICE GROUP BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* |
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*/ |
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/* |
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Prototype VIA control definitions |
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06/04/92,22:33:57 BG Let's see what I can do. |
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*/ |
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/* VIA1 data register A */ |
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#define DA1I_vSCCWrReq 0x80 |
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#define DA1O_vPage2 0x40 |
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#define DA1I_CPU_ID1 0x40 |
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#define DA1O_vHeadSel 0x20 |
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#define DA1O_vOverlay 0x10 |
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#define DA1O_vSync 0x08 |
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#define DA1O_RESERVED2 0x04 |
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#define DA1O_RESERVED1 0x02 |
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#define DA1O_RESERVED0 0x01 |
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/* VIA1 data register B */ |
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#define DB1I_Par_Err 0x80 |
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#define DB1O_vSndEnb 0x80 |
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#define DB1O_Par_Enb 0x40 |
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#define DB1O_vFDesk2 0x20 |
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#define DB1O_vFDesk1 0x10 |
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#define DB1I_vFDBInt 0x08 |
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#define DB1O_rTCEnb 0x04 |
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#define DB1O_rTCCLK 0x02 |
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#define DB1O_rTCData 0x01 |
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#define DB1I_rTCData 0x01 |
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/* VIA2 data register A */ |
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#define DA2O_v2Ram1 0x80 |
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#define DA2O_v2Ram0 0x40 |
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#define DA2I_v2IRQ0 0x40 |
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#define DA2I_v2IRQE 0x20 |
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#define DA2I_v2IRQD 0x10 |
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#define DA2I_v2IRQC 0x08 |
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#define DA2I_v2IRQB 0x04 |
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#define DA2I_v2IRQA 0x02 |
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#define DA2I_v2IRQ9 0x01 |
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/* VIA2 data register B */ |
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#define DB2O_v2VBL 0x80 |
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#define DB2O_Par_Test 0x80 |
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#define DB2I_v2SNDEXT 0x40 |
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#define DB2I_v2TM0A 0x20 |
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#define DB2I_v2TM1A 0x10 |
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#define DB2I_vFC3 0x08 |
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#define DB2O_vFC3 0x08 |
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#define DB2O_v2PowerOff 0x04 |
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#define DB2O_v2BusLk 0x02 |
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#define DB2O_vCDis 0x01 |
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#define DB2O_CEnable 0x01 |
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/* |
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* VIA1 interrupts |
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*/ |
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#define VIA1_T1 6 |
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#define VIA1_T2 5 |
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#define VIA1_ADBCLK 4 |
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#define VIA1_ADBDATA 3 |
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#define VIA1_ADBRDY 2 |
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#define VIA1_VBLNK 1 |
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#define VIA1_ONESEC 0 |
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/* VIA1 interrupt bits */ |
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#define V1IF_IRQ 0x80 |
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#define V1IF_T1 (1 << VIA1_T1) |
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#define V1IF_T2 (1 << VIA1_T2) |
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#define V1IF_ADBCLK (1 << VIA1_ADBCLK) |
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#define V1IF_ADBDATA (1 << VIA1_ADBDATA) |
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#define V1IF_ADBRDY (1 << VIA1_ADBRDY) |
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#define V1IF_VBLNK (1 << VIA1_VBLNK) |
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#define V1IF_ONESEC (1 << VIA1_ONESEC) |
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/* |
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* VIA2 interrupts |
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*/ |
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#define VIA2_T1 6 |
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#define VIA2_T2 5 |
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#define VIA2_ASC 4 |
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#define VIA2_SCSIIRQ 3 |
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#define VIA2_EXPIRQ 2 |
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#define VIA2_SLOTINT 1 |
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#define VIA2_SCSIDRQ 0 |
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/* VIA2 interrupt bits */ |
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#define V2IF_IRQ 0x80 |
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#define V2IF_T1 (1 << VIA2_T1) |
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#define V2IF_T2 (1 << VIA2_T2) |
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#define V2IF_ASC (1 << VIA2_ASC) |
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#define V2IF_SCSIIRQ (1 << VIA2_SCSIIRQ) |
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#define V2IF_EXPIRQ (1 << VIA2_EXPIRQ) |
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#define V2IF_SLOTINT (1 << VIA2_SLOTINT) |
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#define V2IF_SCSIDRQ (1 << VIA2_SCSIDRQ) |
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#define VIA1_INTS (V1IF_T1 | V1IF_ADBRDY) |
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#define VIA2_INTS (V2IF_T1 | V2IF_ASC | V2IF_SCSIIRQ | V2IF_SLOTINT | \ |
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V2IF_SCSIDRQ) |
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#define RBV_INTS (V2IF_T1 | V2IF_ASC | V2IF_SCSIIRQ | V2IF_SLOTINT | \ |
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V2IF_SCSIDRQ | V1IF_ADBRDY) |
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#define ACR_T1LATCH 0x40 |
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#if 0 |
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extern volatile unsigned char *Via1Base; |
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#endif |
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#define VIA1_addr Via1Base /* at PA 0x50f00000 */ |
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#define VIA2OFF 1 /* VIA2 addr = VIA1_addr * 0x2000 */ |
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#define RBVOFF 0x13 /* RBV addr = VIA1_addr * 0x13000 */ |
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#define VIA1 0 |
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#define VIA2 0 |
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/* VIA interface registers */ |
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#define vBufB 0x0000 /* register B */ |
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#define vBufA 0x0200 /* register A */ |
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#define vDirB 0x0400 /* data direction register */ |
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#define vDirA 0x0600 /* data direction register */ |
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#define vT1C 0x0800 |
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#define vT1CH 0x0a00 |
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#define vT1L 0x0c00 |
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#define vT1LH 0x0e00 |
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#define vT2C 0x1000 |
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#define vT2CH 0x1200 |
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#define vSR 0x1400 /* shift register */ |
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#define vACR 0x1600 /* aux control register */ |
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#define vPCR 0x1800 /* peripheral control register */ |
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#define vIFR 0x1a00 /* interrupt flag register */ |
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#define vIER 0x1c00 /* interrupt enable register */ |
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/* RBV interface registers */ |
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#define rBufB 0 /* register B */ |
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#define rBufA 2 /* register A */ |
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#define rIFR 0x3 /* interrupt flag register (writes?) */ |
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#define rIER 0x13 /* interrupt enable register */ |
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#define rMonitor 0x10 /* Monitor type */ |
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#define rSlotInt 0x12 /* Slot interrupt */ |
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/* RBV monitor type flags and masks */ |
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#define RBVDepthMask 0x07 /* depth in bits */ |
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#define RBVMonitorMask 0x38 /* Type numbers */ |
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#define RBVOff 0x40 /* monitor turn off */ |
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#define RBVMonIDNone 0x38 /* What RBV actually has for no video */ |
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#define RBVMonIDOff 0x0 /* What rbv_vidstatus() returns for no video */ |
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#define RBVMonID15BWP 0x08 /* BW portrait */ |
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#define RBVMonIDRGB 0x10 /* color monitor */ |
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#define RBVMonIDRGB15 0x28 /* 15 inch RGB */ |
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#define RBVMonIDBW 0x30 /* No internal video */ |
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#define via_reg(v, r) (*(Via1Base + (r))) |
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#if 0 |
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#include <machine/pio.h> |
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static __inline void via_reg_and(int, int, int); |
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static __inline void via_reg_or(int, int, int); |
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static __inline void via_reg_xor(int, int, int); |
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static __inline void write_via_reg(int, int, int); |
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static __inline int read_via_reg(int, int); |
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static __inline void |
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via_reg_and(ign, reg, val) |
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int ign, reg, val; |
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{ |
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volatile unsigned char *addr = Via1Base + reg; |
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out8(addr, in8(addr) & val); |
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} |
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static __inline void |
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via_reg_or(ign, reg, val) |
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int ign, reg, val; |
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{ |
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volatile unsigned char *addr = Via1Base + reg; |
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out8(addr, in8(addr) | val); |
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} |
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static __inline void |
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via_reg_xor(ign, reg, val) |
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int ign, reg, val; |
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{ |
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volatile unsigned char *addr = Via1Base + reg; |
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out8(addr, in8(addr) ^ val); |
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} |
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static __inline int |
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read_via_reg(ign, reg) |
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int ign, reg; |
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{ |
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volatile unsigned char *addr = Via1Base + reg; |
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return in8(addr); |
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} |
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static __inline void |
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write_via_reg(ign, reg, val) |
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int ign, reg, val; |
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{ |
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volatile unsigned char *addr = Via1Base + reg; |
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out8(addr, val); |
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} |
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#define vDirA_ADBState 0x30 |
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void via_init __P((void)); |
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int rbv_vidstatus __P((void)); |
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void via_shutdown __P((void)); |
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void via_set_modem __P((int)); |
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int add_nubus_intr __P((int, void (*) __P((void *, int)), void *)); |
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void enable_nubus_intr __P((void)); |
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void via1_register_irq __P((int, void (*)(void *), void *)); |
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void via2_register_irq __P((int, void (*)(void *), void *)); |
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extern void (*via1itab[7]) __P((void *)); |
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extern void (*via2itab[7]) __P((void *)); |
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#endif |
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#endif /* ADB_VIAREG_H */ |
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