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/* |
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* Copyright (C) 2004-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_wdsc.c,v 1.34 2007/01/28 14:15:30 debug Exp $ |
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* |
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* WDSC SCSI (WD33C93) controller. |
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* (For SGI-IP22. See sys/arch/sgimips/hpc/sbic* in NetBSD for details.) |
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* |
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* TODO: This device doesn't do much yet. |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "cpu.h" |
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#include "devices.h" |
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#include "diskimage.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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|
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#include "wdsc_sbicreg.h" |
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|
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|
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struct wdsc_data { |
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int irq_nr; |
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int controller_nr; |
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|
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int register_select; |
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unsigned char reg[DEV_WDSC_NREGS]; |
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|
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int irq_pending; |
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|
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int buf_allocatedlen; |
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int buf_curptr; |
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unsigned char *buf; |
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|
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int current_phase; |
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|
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struct scsi_transfer *xfer; |
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}; |
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|
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|
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DEVICE_TICK(wdsc) |
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{ |
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/* struct wdsc_data *d = extra; */ |
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|
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fatal("TODO: legacy interrupt rewrite!\n"); |
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abort(); |
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|
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// if (d->irq_pending) |
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// cpu_interrupt(cpu, d->irq_nr); |
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// else |
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// cpu_interrupt_ack(cpu, d->irq_nr); |
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} |
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|
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|
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/* |
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* dev_wdsc_regwrite(): |
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* |
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* Handle writes to WDSC registers. |
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*/ |
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static void dev_wdsc_regwrite(struct cpu *cpu, struct wdsc_data *d, int idata) |
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{ |
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d->reg[d->register_select] = idata & 0xff; |
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|
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debug("[ wdsc: write to register %i", d->register_select); |
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|
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switch (d->register_select) { |
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|
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case SBIC_myid: |
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debug(" (myid): 0x%02x => ", (int)idata); |
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if (idata & SBIC_ID_FS_16_20) |
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debug("16-20MHz, "); |
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if (idata & SBIC_ID_FS_12_15) |
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debug("12-15MHz, "); |
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if (idata & SBIC_ID_RAF) |
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debug("RAF(?), "); |
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if (idata & SBIC_ID_EHP) |
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debug("Parity, "); |
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if (idata & SBIC_ID_EAF) |
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debug("EnableAdvancedFeatures, "); |
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debug("ID=%i", idata & SBIC_ID_MASK); |
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break; |
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|
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case SBIC_control: |
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debug(" (control): 0x%02x =>", (int)idata); |
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if (idata & SBIC_CTL_DMA) |
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debug(" SingleByteDMA"); |
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if (idata & SBIC_CTL_DBA_DMA) |
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debug(" DirectBufferAccess"); |
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if (idata & SBIC_CTL_BURST_DMA) |
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debug(" BurstDMA"); |
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if (idata & SBIC_CTL_HHP) |
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debug(" HaltOnParity"); |
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if (idata & SBIC_CTL_EDI) |
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debug(" EndDisconIntr"); |
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if (idata & SBIC_CTL_IDI) |
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debug(" IntermediateDisconIntr"); |
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if (idata & SBIC_CTL_HA) |
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debug(" HaltOnATN"); |
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if (idata & SBIC_CTL_HSP) |
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debug(" HaltOnParityError"); |
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|
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if (idata == SBIC_CTL_NO_DMA) |
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debug(" PIO"); |
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|
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/* TODO: When/how are interrupts acknowledged? */ |
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if (idata & SBIC_CTL_EDI) |
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d->irq_pending = 0; |
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|
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break; |
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|
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case SBIC_count_hi: |
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debug(" (count_hi): 0x%02x", (int)idata); |
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break; |
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|
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case SBIC_count_med: |
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debug(" (count_med): 0x%02x", (int)idata); |
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break; |
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|
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case SBIC_count_lo: |
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debug(" (count_lo): 0x%02x", (int)idata); |
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break; |
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|
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case SBIC_selid: |
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debug(" (selid): 0x%02x => ", (int)idata); |
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|
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if (idata & SBIC_SID_SCC) |
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debug("SelectCommandChaining, "); |
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if (idata & SBIC_SID_FROM_SCSI) |
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debug("FromSCSI, "); |
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else |
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debug("ToSCSI, "); |
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|
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debug("id %i", idata & SBIC_SID_IDMASK); |
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break; |
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|
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case SBIC_rselid: |
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debug(" (rselid): 0x%02x => ", (int)idata); |
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|
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if (idata & SBIC_RID_ER) |
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debug("EnableReselection, "); |
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if (idata & SBIC_RID_ES) |
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debug("EnableSelection, "); |
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if (idata & SBIC_RID_DSP) |
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debug("DisableSelectParity, "); |
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if (idata & SBIC_RID_SIV) |
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debug("SourceIDValid, "); |
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|
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debug("id %i", idata & SBIC_RID_MASK); |
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break; |
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|
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case SBIC_cmd: |
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debug(" (cmd): 0x%02x => ", (int)idata); |
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|
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/* SBT = Single Byte Transfer */ |
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if (idata & SBIC_CMD_SBT) |
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debug("SBT, "); |
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|
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/* Handle commands: */ |
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switch (idata & SBIC_CMD_MASK) { |
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case SBIC_CMD_RESET: |
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debug("RESET"); |
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d->irq_pending = 1; |
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d->reg[SBIC_csr] = SBIC_CSR_RESET; |
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break; |
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case SBIC_CMD_ABORT: |
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debug("ABORT"); |
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break; |
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case SBIC_CMD_SEL_ATN: |
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debug("SEL_ATN"); |
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d->irq_pending = 1; |
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d->reg[SBIC_csr] = SBIC_CSR_SEL_TIMEO; |
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if (d->controller_nr == 0 && diskimage_exist( |
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cpu->machine, d->reg[SBIC_selid] & |
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SBIC_SID_IDMASK, DISKIMAGE_SCSI)) { |
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if (d->xfer != NULL) |
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scsi_transfer_free(d->xfer); |
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d->xfer = scsi_transfer_alloc(); |
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|
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/* According to NetBSD, we can go either to |
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SBIC_CSR_MIS_2 | CMD_PHASE, or |
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SBIC_CSR_MIS_2 | MESG_OUT_PHASE. */ |
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|
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d->reg[SBIC_csr] = SBIC_CSR_MIS_2 | CMD_PHASE; |
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|
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d->current_phase = CMD_PHASE; |
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} |
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break; |
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case SBIC_CMD_XFER_INFO: |
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debug("XFER_INFO"); |
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|
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if (d->buf != NULL) |
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free(d->buf); |
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|
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d->buf_allocatedlen = (d->reg[SBIC_count_hi] << 16) |
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+ (d->reg[SBIC_count_med] << 8) + |
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d->reg[SBIC_count_lo]; |
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|
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d->buf = malloc(d->buf_allocatedlen); |
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if (d->buf == NULL) { |
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fprintf(stderr, "out of memory in wdsc\n"); |
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exit(1); |
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} |
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|
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d->buf_curptr = 0; |
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d->irq_pending = 0; |
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break; |
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default: |
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debug("unimplemented command"); |
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} |
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break; |
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|
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case SBIC_data: |
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debug(" (data): 0x%02x", (int)idata); |
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|
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switch (d->reg[SBIC_cmd] & ~SBIC_CMD_SBT) { |
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case SBIC_CMD_XFER_INFO: |
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if (d->buf == NULL || d->buf_curptr >= |
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d->buf_allocatedlen) { |
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fprintf(stderr, "fatal error in wdsc\n"); |
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exit(1); |
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} |
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|
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d->buf[d->buf_curptr++] = idata; |
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|
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if (d->buf_curptr >= d->buf_allocatedlen) { |
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int res; |
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|
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/* |
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* Transfer buf to/from the SCSI unit: |
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*/ |
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|
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switch (d->current_phase) { |
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case CMD_PHASE: |
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scsi_transfer_allocbuf( |
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&d->xfer->cmd_len, &d->xfer->cmd, |
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d->buf_allocatedlen, 1); |
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memcpy(d->xfer->cmd, d->buf, |
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d->buf_allocatedlen); |
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break; |
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default: |
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fatal("wdsc: unimplemented phase %i!\n", |
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d->current_phase); |
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} |
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|
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res = diskimage_scsicommand(cpu, |
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d->reg[SBIC_selid] & SBIC_SID_IDMASK, |
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DISKIMAGE_SCSI, d->xfer); |
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debug("{ res = %i }", res); |
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|
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d->irq_pending = 1; |
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|
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if (res == 2) |
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d->reg[SBIC_csr] = SBIC_CSR_XFERRED | |
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DATA_OUT_PHASE; |
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else |
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d->reg[SBIC_csr] = SBIC_CSR_XFERRED | |
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DATA_IN_PHASE; |
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|
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/* status phase? msg in and msg out? */ |
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} |
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break; |
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default: |
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fatal("[ wdsc: don't know how to handle data for " |
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"cmd = 0x%02x ]\n", d->reg[SBIC_cmd]); |
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} |
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|
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break; |
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|
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default: |
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debug(" (TODO): 0x%02x", (int)idata); |
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} |
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|
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debug(" ]\n"); |
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|
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/* After writing to a register, advance to the next: */ |
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d->register_select ++; |
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} |
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|
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|
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/* |
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* dev_wdsc_access(): |
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*/ |
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DEVICE_ACCESS(wdsc) |
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{ |
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size_t i; |
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struct wdsc_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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|
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/* |
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* All registers on the WDSC seem to be accessed by writing the |
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* register number to one address (SBIC_ADDR), and then reading/ |
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* writing another address (SBIC_VAL). |
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* |
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* On SGI-IP22, these are at offset 3 and 7, respectively. |
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* |
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* TODO: If this device is to be used by other machine types, then |
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* this needs to be conditionalized. |
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*/ |
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relative_addr = (relative_addr - 3) / 4; |
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|
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switch (relative_addr) { |
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|
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case SBIC_ADDR: |
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/* |
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* Reading the combined ADDR/ASR returns the Status |
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* Register, writing selects which register to access |
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* via SBIC_VAL. |
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*/ |
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if (writeflag == MEM_READ) { |
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odata = SBIC_ASR_DBR; |
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if (d->irq_pending) |
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odata |= SBIC_ASR_INT; |
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|
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debug("[ wdsc: read from Status Register: %02x ]\n", |
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(int)odata); |
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} else { |
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d->register_select = idata & (DEV_WDSC_NREGS - 1); |
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} |
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break; |
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|
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case SBIC_VAL: |
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if (writeflag == MEM_READ) { |
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odata = d->reg[d->register_select]; |
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|
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if (d->register_select == SBIC_csr) { |
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/* TODO: when should interrupts actually be |
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ack:ed? */ |
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d->irq_pending = 0; |
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} |
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|
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debug("[ wdsc: read from register %i: 0x%02x ]\n", |
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d->register_select, (int)odata); |
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} else { |
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dev_wdsc_regwrite(cpu, d, idata & 0xff); |
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} |
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break; |
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|
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default: |
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/* These should never occur: */ |
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if (writeflag==MEM_READ) { |
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fatal("[ wdsc: read from 0x%x:", (int)relative_addr); |
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for (i=0; i<len; i++) |
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fatal(" %02x", data[i]); |
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fatal(" (len=%i) ]\n", len); |
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} else { |
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fatal("[ wdsc: write to 0x%x:", (int)relative_addr); |
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for (i=0; i<len; i++) |
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fatal(" %02x", data[i]); |
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fatal(" (len=%i) ]\n", len); |
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} |
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} |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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dev_wdsc_tick(cpu, extra); |
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|
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return 1; |
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} |
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|
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|
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/* |
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* dev_wdsc_init(): |
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*/ |
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void dev_wdsc_init(struct machine *machine, struct memory *mem, |
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uint64_t baseaddr, int controller_nr, int irq_nr) |
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{ |
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struct wdsc_data *d; |
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|
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d = malloc(sizeof(struct wdsc_data)); |
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if (d == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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memset(d, 0, sizeof(struct wdsc_data)); |
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d->irq_nr = irq_nr; |
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d->controller_nr = controller_nr; |
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|
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memory_device_register(mem, "wdsc", baseaddr, DEV_WDSC_LENGTH, |
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dev_wdsc_access, d, DM_DEFAULT, NULL); |
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|
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machine_add_tickfunction(machine, dev_wdsc_tick, d, 14, 0.0); |
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} |
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