src/devices/dev_rd94.c

/*
 *  Copyright (C) 2003-2007  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *   
 *
 *  $Id: dev_rd94.c,v 1.39 2007/01/28 14:15:30 debug Exp $
 *  
 *  Used by NEC-RD94, -R94, and -R96.
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "bus_pci.h"
#include "cop0.h"
#include "cpu.h"
#include "cpu_mips.h"
#include "device.h"
#include "machine.h"
#include "memory.h"
#include "misc.h"

#include "rd94.h"


#define RD94_TICK_SHIFT         14

#define DEV_RD94_LENGTH         0x1000

struct rd94_data {
        struct pci_data *pci_data;
        uint32_t        reg[DEV_RD94_LENGTH / 4];
        int             pciirq;

        int             intmask;
        int             interval;
        int             interval_start;
};


DEVICE_TICK(rd94)
{
        struct rd94_data *d = extra;

        /*  TODO: hm... intmask !=0 ?  */
        if (d->interval_start > 0 && d->interval > 0 && d->intmask != 0) {
                d->interval --;
                if (d->interval <= 0) {
                        debug("[ rd94: interval timer interrupt ]\n");

fatal("TODO: rd94 legacy interrupt rewrite\n");
abort();
//                      cpu_interrupt(cpu, 5);
                }
        }
}


DEVICE_ACCESS(rd94)
{
        struct rd94_data *d = (struct rd94_data *) extra;
        uint64_t idata = 0, odata = 0;
        int regnr, bus, dev, func, pcireg;

        if (writeflag == MEM_WRITE)
                idata = memory_readmax64(cpu, data, len);

        regnr = relative_addr / sizeof(uint32_t);

        switch (relative_addr) {

        case RD94_SYS_CONFIG:
                if (writeflag == MEM_WRITE) {
                        fatal("[ rd94: write to CONFIG: 0x%llx ]\n",
                            (long long)idata);
                } else {
                        odata = 0;
                        fatal("[ rd94: read from CONFIG: 0x%llx ]\n",
                            (long long)odata);
                }
                break;

        case RD94_SYS_INTSTAT1:         /*  LB (Local Bus ???)  */
                if (writeflag == MEM_WRITE) {
                } else {
                        /*  Return value is (irq level + 1) << 2  */
                        odata = (8+1) << 2;

                        /*  Ugly hack:  */
                        if ((cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] & 0x800)
                            == 0)
                                odata = 0;
                }
                debug("[ rd94: intstat1 ]\n");

fatal("TODO: rd94 legacy interrupt rewrite\n");
abort();
/*              cpu_interrupt_ack(cpu, 3); */
                break;

        case RD94_SYS_INTSTAT2:         /*  PCI/EISA  */
                if (writeflag == MEM_WRITE) {
                } else {
                        odata = 0;      /*  TODO  */
                }
                debug("[ rd94: intstat2 ]\n");

fatal("TODO: rd94 legacy interrupt rewrite\n");
abort();
/*              cpu_interrupt_ack(cpu, 4); */
                break;

        case RD94_SYS_INTSTAT3:         /*  IT (Interval Timer)  */
                if (writeflag == MEM_WRITE) {
                } else {
                        odata = 0;      /*  return value does not matter?  */
                }
                debug("[ rd94: intstat3 ]\n");

fatal("TODO: rd94 legacy interrupt rewrite\n");
abort();
//              cpu_interrupt_ack(cpu, 5);
                d->interval = d->interval_start;
                break;

        case RD94_SYS_INTSTAT4:         /*  IPI  */
                if (writeflag == MEM_WRITE) {
                } else {
                        odata = 0;      /*  return value does not matter?  */
                }
                fatal("[ rd94: intstat4 ]\n");
fatal("TODO: rd94 legacy interrupt rewrite\n");
abort();
//              cpu_interrupt_ack(cpu, 6);
                break;

        case RD94_SYS_CPUID:
                if (writeflag == MEM_WRITE) {
                        fatal("[ rd94: write to CPUID: 0x%llx ]\n",
                            (long long)idata);
                } else {
                        odata = cpu->cpu_id;
                        fatal("[ rd94: read from CPUID: 0x%llx ]\n",
                            (long long)odata);
                }
                break;

        case RD94_SYS_EXT_IMASK:
                if (writeflag == MEM_WRITE) {
                        d->intmask = idata;
                } else {
                        odata = d->intmask;
                }
                break;

        case RD94_SYS_IT_VALUE:
                if (writeflag == MEM_WRITE) {
                        d->interval = d->interval_start = idata;
                        debug("[ rd94: setting Interval Timer value to %i ]\n",
                            (int)idata);
                } else {
                        odata = d->interval_start;
                        /*  TODO: or d->interval ?  */;
                }
                break;

        case RD94_SYS_PCI_CONFADDR:
                bus_pci_decompose_1(idata, &bus, &dev, &func, &pcireg);
                bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, pcireg);
                break;

        case RD94_SYS_PCI_CONFDATA:
                bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
                    &odata : &idata, len, writeflag);
                break;

        default:if (writeflag == MEM_WRITE) {
                        fatal("[ rd94: unimplemented write to address 0x%x, "
                            "data=0x%02x ]\n", (int)relative_addr, (int)idata);
                } else {
                        fatal("[ rd94: unimplemented read from address 0x%x"
                            " ]\n", (int)relative_addr);
                }
        }

        if (writeflag == MEM_READ)
                memory_writemax64(cpu, data, len, odata);

        return 1;
}


DEVINIT(rd94)
{
        struct rd94_data *d = malloc(sizeof(struct rd94_data));
        if (d == NULL) {
                fprintf(stderr, "out of memory\n");
                exit(1);
        }
        memset(d, 0, sizeof(struct rd94_data));
        d->pciirq   = devinit->irq_nr;
        d->pci_data = bus_pci_init(devinit->machine, "TODO irq",
            0,0, 0,0,0, 0,0,0);

        memory_device_register(devinit->machine->memory, devinit->name,
            devinit->addr, DEV_RD94_LENGTH,
            dev_rd94_access, (void *)d, DM_DEFAULT, NULL);

        machine_add_tickfunction(devinit->machine, dev_rd94_tick,
            d, RD94_TICK_SHIFT, 0.0);

        devinit->return_ptr = d->pci_data;

        return 1;
}

1	dpavlin	4	/*
2	dpavlin	34	* Copyright (C) 2003-2007 Anders Gavare. All rights reserved.
3	dpavlin	4	*
4			* Redistribution and use in source and binary forms, with or without
5			* modification, are permitted provided that the following conditions are met:
6			*
7			* 1. Redistributions of source code must retain the above copyright
8			* notice, this list of conditions and the following disclaimer.
9			* 2. Redistributions in binary form must reproduce the above copyright
10			* notice, this list of conditions and the following disclaimer in the
11			* documentation and/or other materials provided with the distribution.
12			* 3. The name of the author may not be used to endorse or promote products
13			* derived from this software without specific prior written permission.
14			*
15			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25			* SUCH DAMAGE.
26			*
27			*
28	dpavlin	34	* $Id: dev_rd94.c,v 1.39 2007/01/28 14:15:30 debug Exp $
29	dpavlin	4	*
30			* Used by NEC-RD94, -R94, and -R96.
31			*/
32
33			#include <stdio.h>
34			#include <stdlib.h>
35			#include <string.h>
36
37			#include "bus_pci.h"
38			#include "cop0.h"
39			#include "cpu.h"
40			#include "cpu_mips.h"
41			#include "device.h"
42			#include "machine.h"
43			#include "memory.h"
44			#include "misc.h"
45
46			#include "rd94.h"
47
48
49			#define RD94_TICK_SHIFT 14
50
51			#define DEV_RD94_LENGTH 0x1000
52
53			struct rd94_data {
54			struct pci_data *pci_data;
55			uint32_t reg[DEV_RD94_LENGTH / 4];
56			int pciirq;
57
58			int intmask;
59			int interval;
60			int interval_start;
61			};
62
63
64	dpavlin	30	DEVICE_TICK(rd94)
65	dpavlin	4	{
66			struct rd94_data *d = extra;
67
68			/* TODO: hm... intmask !=0 ? */
69			if (d->interval_start > 0 && d->interval > 0 && d->intmask != 0) {
70			d->interval --;
71			if (d->interval <= 0) {
72			debug("[ rd94: interval timer interrupt ]\n");
73	dpavlin	34
74			fatal("TODO: rd94 legacy interrupt rewrite\n");
75			abort();
76			// cpu_interrupt(cpu, 5);
77	dpavlin	4	}
78			}
79			}
80
81
82	dpavlin	22	DEVICE_ACCESS(rd94)
83	dpavlin	4	{
84			struct rd94_data d = (struct rd94_data ) extra;
85			uint64_t idata = 0, odata = 0;
86	dpavlin	22	int regnr, bus, dev, func, pcireg;
87	dpavlin	4
88	dpavlin	18	if (writeflag == MEM_WRITE)
89			idata = memory_readmax64(cpu, data, len);
90
91	dpavlin	4	regnr = relative_addr / sizeof(uint32_t);
92
93			switch (relative_addr) {
94	dpavlin	22
95	dpavlin	4	case RD94_SYS_CONFIG:
96			if (writeflag == MEM_WRITE) {
97			fatal("[ rd94: write to CONFIG: 0x%llx ]\n",
98			(long long)idata);
99			} else {
100			odata = 0;
101			fatal("[ rd94: read from CONFIG: 0x%llx ]\n",
102			(long long)odata);
103			}
104			break;
105	dpavlin	22
106	dpavlin	4	case RD94_SYS_INTSTAT1: /* LB (Local Bus ???) */
107			if (writeflag == MEM_WRITE) {
108			} else {
109			/* Return value is (irq level + 1) << 2 */
110			odata = (8+1) << 2;
111
112			/* Ugly hack: */
113			if ((cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] & 0x800)
114			== 0)
115			odata = 0;
116			}
117			debug("[ rd94: intstat1 ]\n");
118	dpavlin	34
119			fatal("TODO: rd94 legacy interrupt rewrite\n");
120			abort();
121	dpavlin	4	/* cpu_interrupt_ack(cpu, 3); */
122			break;
123	dpavlin	22
124	dpavlin	4	case RD94_SYS_INTSTAT2: /* PCI/EISA */
125			if (writeflag == MEM_WRITE) {
126			} else {
127			odata = 0; /* TODO */
128			}
129			debug("[ rd94: intstat2 ]\n");
130	dpavlin	34
131			fatal("TODO: rd94 legacy interrupt rewrite\n");
132			abort();
133	dpavlin	4	/* cpu_interrupt_ack(cpu, 4); */
134			break;
135	dpavlin	22
136	dpavlin	4	case RD94_SYS_INTSTAT3: /* IT (Interval Timer) */
137			if (writeflag == MEM_WRITE) {
138			} else {
139			odata = 0; /* return value does not matter? */
140			}
141			debug("[ rd94: intstat3 ]\n");
142	dpavlin	34
143			fatal("TODO: rd94 legacy interrupt rewrite\n");
144			abort();
145			// cpu_interrupt_ack(cpu, 5);
146	dpavlin	4	d->interval = d->interval_start;
147			break;
148	dpavlin	22
149	dpavlin	4	case RD94_SYS_INTSTAT4: /* IPI */
150			if (writeflag == MEM_WRITE) {
151			} else {
152			odata = 0; /* return value does not matter? */
153			}
154			fatal("[ rd94: intstat4 ]\n");
155	dpavlin	34	fatal("TODO: rd94 legacy interrupt rewrite\n");
156			abort();
157			// cpu_interrupt_ack(cpu, 6);
158	dpavlin	4	break;
159	dpavlin	22
160	dpavlin	4	case RD94_SYS_CPUID:
161			if (writeflag == MEM_WRITE) {
162			fatal("[ rd94: write to CPUID: 0x%llx ]\n",
163			(long long)idata);
164			} else {
165			odata = cpu->cpu_id;
166			fatal("[ rd94: read from CPUID: 0x%llx ]\n",
167			(long long)odata);
168			}
169			break;
170	dpavlin	22
171	dpavlin	4	case RD94_SYS_EXT_IMASK:
172			if (writeflag == MEM_WRITE) {
173			d->intmask = idata;
174			} else {
175			odata = d->intmask;
176			}
177			break;
178	dpavlin	22
179	dpavlin	4	case RD94_SYS_IT_VALUE:
180			if (writeflag == MEM_WRITE) {
181			d->interval = d->interval_start = idata;
182			debug("[ rd94: setting Interval Timer value to %i ]\n",
183			(int)idata);
184			} else {
185			odata = d->interval_start;
186			/* TODO: or d->interval ? */;
187			}
188			break;
189	dpavlin	22
190	dpavlin	4	case RD94_SYS_PCI_CONFADDR:
191	dpavlin	22	bus_pci_decompose_1(idata, &bus, &dev, &func, &pcireg);
192			bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, pcireg);
193			break;
194
195	dpavlin	4	case RD94_SYS_PCI_CONFDATA:
196	dpavlin	22	bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
197			&odata : &idata, len, writeflag);
198	dpavlin	4	break;
199	dpavlin	22
200			default:if (writeflag == MEM_WRITE) {
201	dpavlin	4	fatal("[ rd94: unimplemented write to address 0x%x, "
202			"data=0x%02x ]\n", (int)relative_addr, (int)idata);
203			} else {
204			fatal("[ rd94: unimplemented read from address 0x%x"
205			" ]\n", (int)relative_addr);
206			}
207			}
208
209			if (writeflag == MEM_READ)
210			memory_writemax64(cpu, data, len, odata);
211
212			return 1;
213			}
214
215
216	dpavlin	22	DEVINIT(rd94)
217	dpavlin	4	{
218			struct rd94_data *d = malloc(sizeof(struct rd94_data));
219			if (d == NULL) {
220			fprintf(stderr, "out of memory\n");
221			exit(1);
222			}
223			memset(d, 0, sizeof(struct rd94_data));
224			d->pciirq = devinit->irq_nr;
225	dpavlin	34	d->pci_data = bus_pci_init(devinit->machine, "TODO irq",
226	dpavlin	22	0,0, 0,0,0, 0,0,0);
227	dpavlin	4
228			memory_device_register(devinit->machine->memory, devinit->name,
229			devinit->addr, DEV_RD94_LENGTH,
230	dpavlin	20	dev_rd94_access, (void *)d, DM_DEFAULT, NULL);
231	dpavlin	4
232			machine_add_tickfunction(devinit->machine, dev_rd94_tick,
233	dpavlin	24	d, RD94_TICK_SHIFT, 0.0);
234	dpavlin	4
235			devinit->return_ptr = d->pci_data;
236
237			return 1;
238			}
239