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/* |
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* Copyright (C) 2004-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_jazz.c,v 1.27 2007/01/28 13:28:27 debug Exp $ |
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* |
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* Microsoft Jazz-related stuff (Acer PICA-61, etc). |
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* |
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* TODO/NOTE: This is mostly a quick hack, it doesn't really implement |
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* much of the Jazz architecture. Also, the a0/20 isa-like stuff is |
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* not supposed to be here. |
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* |
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* TODO: Figure out how the int enable mask works; it seems to be shifted |
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* 10 bits (?) according to NetBSD/arc sources. |
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* |
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* TODO: Don't hardcode the timer to 100 Hz. |
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* |
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* JAZZ interrupts 0..14 are connected to MIPS irq 3, |
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* JAZZ interrupt 15 (the timer) is connected to MIPS irq 6, |
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* and ISA interrupts 0..15 are connected to MIPS irq 4. |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "cpu.h" |
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#include "device.h" |
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#include "devices.h" |
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#include "interrupt.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "timer.h" |
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|
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#include "jazz_r4030_dma.h" |
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#include "pica.h" |
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|
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|
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#define DEV_JAZZ_LENGTH 0x280 |
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#define DEV_JAZZ_TICKSHIFT 14 |
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#define PICA_TIMER_IRQ 15 |
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|
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struct jazz_data { |
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struct interrupt mips_irq_3; |
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struct interrupt mips_irq_4; |
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struct interrupt mips_irq_6; |
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|
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struct cpu *cpu; |
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|
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/* Jazz stuff: */ |
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uint32_t int_enable_mask; /* TODO! */ |
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uint32_t int_asserted; |
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|
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/* ISA stuff: */ |
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uint32_t isa_int_enable_mask; |
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uint32_t isa_int_asserted; |
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|
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int interval; |
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int interval_start; |
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|
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struct timer *timer; |
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int pending_timer_interrupts; |
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int jazz_timer_value; |
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int jazz_timer_current; |
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struct interrupt jazz_timer_irq; |
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|
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uint64_t dma_translation_table_base; |
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uint64_t dma_translation_table_limit; |
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|
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uint32_t dma0_mode; |
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uint32_t dma0_enable; |
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uint32_t dma0_count; |
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uint32_t dma0_addr; |
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|
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uint32_t dma1_mode; |
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/* same for dma1,2,3 actually (TODO) */ |
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|
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int led; |
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}; |
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|
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|
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void reassert_isa_interrupts(struct jazz_data *d) |
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{ |
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if (d->isa_int_asserted & d->isa_int_enable_mask) |
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INTERRUPT_ASSERT(d->mips_irq_4); |
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else |
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INTERRUPT_DEASSERT(d->mips_irq_4); |
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} |
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|
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|
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void jazz_interrupt_assert(struct interrupt *interrupt) |
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{ |
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struct jazz_data *d = interrupt->extra; |
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d->int_asserted |= (1 << interrupt->line); |
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|
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if (d->int_asserted & 0x7fff) |
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INTERRUPT_ASSERT(d->mips_irq_3); |
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if (d->int_asserted & 0x8000) |
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INTERRUPT_ASSERT(d->mips_irq_6); |
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} |
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void jazz_interrupt_deassert(struct interrupt *interrupt) |
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{ |
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struct jazz_data *d = interrupt->extra; |
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d->int_asserted &= ~(1 << interrupt->line); |
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|
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if (!(d->int_asserted & 0x7fff)) |
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INTERRUPT_DEASSERT(d->mips_irq_3); |
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if (!(d->int_asserted & 0x8000)) |
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INTERRUPT_DEASSERT(d->mips_irq_6); |
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} |
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void jazz_isa_interrupt_assert(struct interrupt *interrupt) |
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{ |
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struct jazz_data *d = interrupt->extra; |
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d->isa_int_asserted |= (1 << interrupt->line); |
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reassert_isa_interrupts(d); |
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} |
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void jazz_isa_interrupt_deassert(struct interrupt *interrupt) |
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{ |
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struct jazz_data *d = interrupt->extra; |
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d->isa_int_asserted &= ~(1 << interrupt->line); |
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reassert_isa_interrupts(d); |
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} |
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|
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|
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/* |
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* dev_jazz_dma_controller(): |
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*/ |
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size_t dev_jazz_dma_controller(void *dma_controller_data, |
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unsigned char *data, size_t len, int writeflag) |
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{ |
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struct jazz_data *d = (struct jazz_data *) dma_controller_data; |
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struct cpu *cpu = d->cpu; |
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int i, enab_writeflag; |
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int res, ncpy; |
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uint32_t dma_addr; |
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unsigned char tr[sizeof(uint32_t)]; |
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uint32_t phys_addr; |
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|
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#if 0 |
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fatal("[ dev_jazz_dma_controller(): writeflag=%i, len=%i, data =", |
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writeflag, (int)len); |
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for (i=0; i<len; i++) |
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fatal(" %02x", data[i]); |
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fatal(" mode=%08x enable=%08x count=%08x addr=%08x", |
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d->dma0_mode, d->dma0_enable, d->dma0_count, d->dma0_addr); |
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fatal(" table=%08x", |
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d->dma_translation_table_base); |
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fatal(" ]\n"); |
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#endif |
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|
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if (!(d->dma0_enable & R4030_DMA_ENAB_RUN)) { |
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fatal("[ dev_jazz_dma_controller(): dma not enabled? ]\n"); |
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/* return 0; */ |
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} |
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|
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/* R4030 "write" means write to the device, writeflag as the |
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argument to this function means write to memory. */ |
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enab_writeflag = (d->dma0_enable & R4030_DMA_ENAB_WRITE)? 0 : 1; |
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if (enab_writeflag != writeflag) { |
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fatal("[ dev_jazz_dma_controller(): wrong direction? ]\n"); |
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return 0; |
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} |
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|
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dma_addr = d->dma0_addr; |
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i = 0; |
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while (dma_addr < d->dma0_addr + d->dma0_count && i < (int32_t)len) { |
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|
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res = cpu->memory_rw(cpu, cpu->mem, |
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d->dma_translation_table_base + (dma_addr >> 12) * 8, |
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tr, sizeof(tr), 0, PHYSICAL | NO_EXCEPTIONS); |
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|
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if (cpu->byte_order==EMUL_BIG_ENDIAN) |
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phys_addr = (tr[0] << 24) + (tr[1] << 16) + |
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(tr[2] << 8) + tr[3]; |
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else |
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phys_addr = (tr[3] << 24) + (tr[2] << 16) + |
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(tr[1] << 8) + tr[0]; |
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phys_addr &= ~0xfff; /* just in case */ |
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phys_addr += (dma_addr & 0xfff); |
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|
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/* fatal(" !!! dma_addr = %08x, phys_addr = %08x\n", |
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(int)dma_addr, (int)phys_addr); */ |
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|
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/* Speed up the copying by copying 16 or 256 bytes: */ |
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ncpy = 1; |
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if ((phys_addr & 15) == 0 && i + 15 <= (int32_t)len) |
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ncpy = 15; |
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if ((phys_addr & 255) == 0 && i + 255 <= (int32_t)len) |
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ncpy = 255; |
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|
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res = cpu->memory_rw(cpu, cpu->mem, phys_addr, |
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&data[i], ncpy, writeflag, PHYSICAL | NO_EXCEPTIONS); |
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|
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dma_addr += ncpy; |
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i += ncpy; |
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} |
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|
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/* TODO: Is this correct? */ |
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d->dma0_count = 0; |
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|
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return len; |
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} |
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|
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|
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static void timer_tick(struct timer *t, void *extra) |
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{ |
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struct jazz_data *d = extra; |
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d->pending_timer_interrupts ++; |
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} |
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|
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|
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DEVICE_TICK(jazz) |
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{ |
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struct jazz_data *d = extra; |
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|
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/* Used by NetBSD/arc and OpenBSD/arc: */ |
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if (d->interval_start > 0 && d->interval > 0 |
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&& (d->int_enable_mask & 2) /* Hm? */ ) { |
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d->interval -= 2; |
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if (d->interval <= 0) { |
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/* debug("[ jazz: interval timer interrupt ]\n"); |
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INTERRUPT_ASSERT(d->jazz_timer_irq); */ |
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} |
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|
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/* New timer system: */ |
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if (d->pending_timer_interrupts > 0) |
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INTERRUPT_ASSERT(d->jazz_timer_irq); |
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} |
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|
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/* Linux? */ |
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if (d->jazz_timer_value != 0) { |
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d->jazz_timer_current -= 5; |
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if (d->jazz_timer_current < 1) { |
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d->jazz_timer_current = d->jazz_timer_value; |
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/* INTERRUPT_ASSERT(d->mips_irq_6); */ |
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} |
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|
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/* New timer system: */ |
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if (d->pending_timer_interrupts > 0) |
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INTERRUPT_ASSERT(d->mips_irq_6); |
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} |
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} |
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|
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|
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DEVICE_ACCESS(jazz) |
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{ |
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struct jazz_data *d = (struct jazz_data *) extra; |
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uint64_t idata = 0, odata = 0; |
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int regnr; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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|
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regnr = relative_addr / sizeof(uint32_t); |
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|
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switch (relative_addr) { |
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case R4030_SYS_CONFIG: |
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if (writeflag == MEM_WRITE) { |
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fatal("[ jazz: unimplemented write to R4030_SYS_CONFIG" |
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", data=0x%08x ]\n", (int)idata); |
| 285 |
} else { |
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/* Reading the config register should give |
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0x0104 or 0x0410. Why? TODO */ |
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odata = 0x104; |
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} |
| 290 |
break; |
| 291 |
case R4030_SYS_TL_BASE: |
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if (writeflag == MEM_WRITE) { |
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d->dma_translation_table_base = idata; |
| 294 |
} else { |
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odata = d->dma_translation_table_base; |
| 296 |
} |
| 297 |
break; |
| 298 |
case R4030_SYS_TL_LIMIT: |
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if (writeflag == MEM_WRITE) { |
| 300 |
d->dma_translation_table_limit = idata; |
| 301 |
} else { |
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odata = d->dma_translation_table_limit; |
| 303 |
} |
| 304 |
break; |
| 305 |
case R4030_SYS_TL_IVALID: |
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/* TODO: Does invalidation actually need to be implemented? */ |
| 307 |
break; |
| 308 |
case R4030_SYS_DMA0_REGS: |
| 309 |
if (writeflag == MEM_WRITE) { |
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d->dma0_mode = idata; |
| 311 |
} else { |
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odata = d->dma0_mode; |
| 313 |
} |
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break; |
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case R4030_SYS_DMA0_REGS + 0x8: |
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if (writeflag == MEM_WRITE) { |
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d->dma0_enable = idata; |
| 318 |
} else { |
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odata = d->dma0_enable; |
| 320 |
} |
| 321 |
break; |
| 322 |
case R4030_SYS_DMA0_REGS + 0x10: |
| 323 |
if (writeflag == MEM_WRITE) { |
| 324 |
d->dma0_count = idata; |
| 325 |
} else { |
| 326 |
odata = d->dma0_count; |
| 327 |
} |
| 328 |
break; |
| 329 |
case R4030_SYS_DMA0_REGS + 0x18: |
| 330 |
if (writeflag == MEM_WRITE) { |
| 331 |
d->dma0_addr = idata; |
| 332 |
} else { |
| 333 |
odata = d->dma0_addr; |
| 334 |
} |
| 335 |
break; |
| 336 |
case R4030_SYS_DMA1_REGS: |
| 337 |
if (writeflag == MEM_WRITE) { |
| 338 |
d->dma1_mode = idata; |
| 339 |
} else { |
| 340 |
odata = d->dma1_mode; |
| 341 |
} |
| 342 |
break; |
| 343 |
case R4030_SYS_ISA_VECTOR: |
| 344 |
/* ? */ |
| 345 |
printf("R4030_SYS_ISA_VECTOR: w=%i\n", writeflag); |
| 346 |
{ |
| 347 |
uint32_t x = d->isa_int_asserted |
| 348 |
& d->isa_int_enable_mask; |
| 349 |
odata = 0; |
| 350 |
while (odata < 16) { |
| 351 |
if (x & (1 << odata)) |
| 352 |
break; |
| 353 |
odata ++; |
| 354 |
} |
| 355 |
if (odata >= 16) |
| 356 |
odata = 0; |
| 357 |
} |
| 358 |
break; |
| 359 |
case R4030_SYS_IT_VALUE: /* Interval timer reload value */ |
| 360 |
if (writeflag == MEM_WRITE) { |
| 361 |
d->interval_start = idata; |
| 362 |
d->interval = d->interval_start; |
| 363 |
} else |
| 364 |
odata = d->interval_start; |
| 365 |
break; |
| 366 |
case R4030_SYS_IT_STAT: |
| 367 |
/* Accessing this word seems to acknowledge interrupts? */ |
| 368 |
INTERRUPT_DEASSERT(d->jazz_timer_irq); |
| 369 |
if (d->pending_timer_interrupts > 0) |
| 370 |
d->pending_timer_interrupts --; |
| 371 |
|
| 372 |
if (writeflag == MEM_WRITE) |
| 373 |
d->interval = idata; |
| 374 |
else |
| 375 |
odata = d->interval; |
| 376 |
d->interval = d->interval_start; |
| 377 |
break; |
| 378 |
case R4030_SYS_EXT_IMASK: |
| 379 |
if (writeflag == MEM_WRITE) { |
| 380 |
int old_assert_3 = (0x7fff & |
| 381 |
d->int_asserted & d->int_enable_mask); |
| 382 |
int old_assert_6 = (0x8000 & |
| 383 |
d->int_asserted & d->int_enable_mask); |
| 384 |
int new_assert_3, new_assert_6; |
| 385 |
|
| 386 |
d->int_enable_mask = idata; |
| 387 |
|
| 388 |
new_assert_3 = |
| 389 |
d->int_asserted & d->int_enable_mask & 0x7fff; |
| 390 |
new_assert_6 = |
| 391 |
d->int_asserted & d->int_enable_mask & 0x8000; |
| 392 |
|
| 393 |
if (old_assert_3 && !new_assert_3) |
| 394 |
INTERRUPT_DEASSERT(d->mips_irq_3); |
| 395 |
else if (!old_assert_3 && new_assert_3) |
| 396 |
INTERRUPT_ASSERT(d->mips_irq_3); |
| 397 |
|
| 398 |
if (old_assert_6 && !new_assert_6) |
| 399 |
INTERRUPT_DEASSERT(d->mips_irq_6); |
| 400 |
else if (!old_assert_6 && new_assert_6) |
| 401 |
INTERRUPT_ASSERT(d->mips_irq_6); |
| 402 |
} else |
| 403 |
odata = d->int_enable_mask; |
| 404 |
break; |
| 405 |
default: |
| 406 |
if (writeflag == MEM_WRITE) { |
| 407 |
fatal("[ jazz: unimplemented write to address 0x%x" |
| 408 |
", data=0x%02x ]\n", (int)relative_addr, |
| 409 |
(int)idata); |
| 410 |
} else { |
| 411 |
fatal("[ jazz: unimplemented read from address 0x%x" |
| 412 |
" ]\n", (int)relative_addr); |
| 413 |
} |
| 414 |
} |
| 415 |
|
| 416 |
if (writeflag == MEM_READ) |
| 417 |
memory_writemax64(cpu, data, len, odata); |
| 418 |
|
| 419 |
return 1; |
| 420 |
} |
| 421 |
|
| 422 |
|
| 423 |
DEVICE_ACCESS(jazz_led) |
| 424 |
{ |
| 425 |
struct jazz_data *d = (struct jazz_data *) extra; |
| 426 |
uint64_t idata = 0, odata = 0; |
| 427 |
int regnr; |
| 428 |
|
| 429 |
if (writeflag == MEM_WRITE) |
| 430 |
idata = memory_readmax64(cpu, data, len); |
| 431 |
|
| 432 |
regnr = relative_addr / sizeof(uint32_t); |
| 433 |
|
| 434 |
switch (relative_addr) { |
| 435 |
case 0: |
| 436 |
if (writeflag == MEM_WRITE) { |
| 437 |
d->led = idata; |
| 438 |
debug("[ jazz_led: write to LED: 0x%02x ]\n", |
| 439 |
(int)idata); |
| 440 |
} else { |
| 441 |
odata = d->led; |
| 442 |
} |
| 443 |
break; |
| 444 |
default: |
| 445 |
if (writeflag == MEM_WRITE) { |
| 446 |
fatal("[ jazz_led: unimplemented write to address 0x%x" |
| 447 |
", data=0x%02x ]\n", (int)relative_addr, |
| 448 |
(int)idata); |
| 449 |
} else { |
| 450 |
fatal("[ jazz_led: unimplemented read from address 0x%x" |
| 451 |
" ]\n", (int)relative_addr); |
| 452 |
} |
| 453 |
} |
| 454 |
|
| 455 |
if (writeflag == MEM_READ) |
| 456 |
memory_writemax64(cpu, data, len, odata); |
| 457 |
|
| 458 |
return 1; |
| 459 |
} |
| 460 |
|
| 461 |
|
| 462 |
/* |
| 463 |
* dev_jazz_a0_access(): |
| 464 |
* |
| 465 |
* ISA interrupt stuff, high 8 interrupts. |
| 466 |
* |
| 467 |
* TODO: use isa8 stuff instead! |
| 468 |
*/ |
| 469 |
DEVICE_ACCESS(jazz_a0) |
| 470 |
{ |
| 471 |
struct jazz_data *d = (struct jazz_data *) extra; |
| 472 |
uint64_t idata = 0, odata = 0; |
| 473 |
|
| 474 |
if (writeflag == MEM_WRITE) |
| 475 |
idata = memory_readmax64(cpu, data, len); |
| 476 |
|
| 477 |
switch (relative_addr) { |
| 478 |
case 0: |
| 479 |
if (writeflag == MEM_WRITE) { |
| 480 |
/* TODO: only if idata == 0x20? */ |
| 481 |
d->isa_int_asserted &= 0xff; |
| 482 |
|
| 483 |
reassert_isa_interrupts(d); |
| 484 |
} |
| 485 |
break; |
| 486 |
case 1: |
| 487 |
if (writeflag == MEM_WRITE) { |
| 488 |
idata = ((idata ^ 0xff) & 0xff) << 8; |
| 489 |
d->isa_int_enable_mask = |
| 490 |
(d->isa_int_enable_mask & 0xff) | idata; |
| 491 |
debug("[ jazz_isa_a0: setting isa_int_enable_mask " |
| 492 |
"to 0x%04x ]\n", (int)d->isa_int_enable_mask); |
| 493 |
|
| 494 |
reassert_isa_interrupts(d); |
| 495 |
} else |
| 496 |
odata = d->isa_int_enable_mask; |
| 497 |
break; |
| 498 |
default: |
| 499 |
if (writeflag == MEM_WRITE) { |
| 500 |
fatal("[ jazz_isa_a0: unimplemented write to " |
| 501 |
"address 0x%x, data=0x%02x ]\n", |
| 502 |
(int)relative_addr, (int)idata); |
| 503 |
} else { |
| 504 |
fatal("[ jazz_isa_a0: unimplemented read from " |
| 505 |
"address 0x%x ]\n", (int)relative_addr); |
| 506 |
} |
| 507 |
} |
| 508 |
|
| 509 |
if (writeflag == MEM_READ) |
| 510 |
memory_writemax64(cpu, data, len, odata); |
| 511 |
|
| 512 |
return 1; |
| 513 |
} |
| 514 |
|
| 515 |
|
| 516 |
/* |
| 517 |
* dev_jazz_20_access(): |
| 518 |
* |
| 519 |
* ISA interrupt stuff, low 8 interrupts. |
| 520 |
*/ |
| 521 |
DEVICE_ACCESS(jazz_20) |
| 522 |
{ |
| 523 |
struct jazz_data *d = (struct jazz_data *) extra; |
| 524 |
uint64_t idata = 0, odata = 0; |
| 525 |
|
| 526 |
if (writeflag == MEM_WRITE) |
| 527 |
idata = memory_readmax64(cpu, data, len); |
| 528 |
|
| 529 |
switch (relative_addr) { |
| 530 |
case 0: |
| 531 |
if (writeflag == MEM_WRITE) { |
| 532 |
/* TODO: only if idata == 0x20? */ |
| 533 |
d->isa_int_asserted &= 0xff00; |
| 534 |
reassert_isa_interrupts(d); |
| 535 |
} |
| 536 |
break; |
| 537 |
case 1: |
| 538 |
if (writeflag == MEM_WRITE) { |
| 539 |
idata = (idata ^ 0xff) & 0xff; |
| 540 |
d->isa_int_enable_mask = |
| 541 |
(d->isa_int_enable_mask & 0xff00) | idata; |
| 542 |
debug("[ jazz_isa_20: setting isa_int_enable_mask " |
| 543 |
"to 0x%04x ]\n", (int)d->isa_int_enable_mask); |
| 544 |
|
| 545 |
reassert_isa_interrupts(d); |
| 546 |
} else |
| 547 |
odata = d->isa_int_enable_mask; |
| 548 |
break; |
| 549 |
default: |
| 550 |
if (writeflag == MEM_WRITE) { |
| 551 |
fatal("[ jazz_isa_20: unimplemented write to " |
| 552 |
"address 0x%x, data=0x%02x ]\n", |
| 553 |
(int)relative_addr, (int)idata); |
| 554 |
} else { |
| 555 |
fatal("[ jazz_isa_20: unimplemented read from " |
| 556 |
"address 0x%x ]\n", (int)relative_addr); |
| 557 |
} |
| 558 |
} |
| 559 |
|
| 560 |
if (writeflag == MEM_READ) |
| 561 |
memory_writemax64(cpu, data, len, odata); |
| 562 |
|
| 563 |
return 1; |
| 564 |
} |
| 565 |
|
| 566 |
|
| 567 |
/* |
| 568 |
* dev_jazz_jazzio_access(): |
| 569 |
* |
| 570 |
* See jazzio_intr() in NetBSD's |
| 571 |
* /usr/src/sys/arch/arc/jazz/jazzio.c for more info. |
| 572 |
*/ |
| 573 |
DEVICE_ACCESS(jazz_jazzio) |
| 574 |
{ |
| 575 |
struct jazz_data *d = (struct jazz_data *) extra; |
| 576 |
uint64_t idata = 0, odata = 0; |
| 577 |
int i, v; |
| 578 |
|
| 579 |
if (writeflag == MEM_WRITE) |
| 580 |
idata = memory_readmax64(cpu, data, len); |
| 581 |
|
| 582 |
switch (relative_addr) { |
| 583 |
case 0: |
| 584 |
v = 0; |
| 585 |
for (i=0; i<15; i++) { |
| 586 |
if (d->int_asserted & (1<<i)) { |
| 587 |
v = i+1; |
| 588 |
break; |
| 589 |
} |
| 590 |
} |
| 591 |
odata = v << 2; |
| 592 |
break; |
| 593 |
case 2: |
| 594 |
/* TODO: Should this be here?! */ |
| 595 |
|
| 596 |
if (writeflag == MEM_WRITE) |
| 597 |
d->jazz_timer_value = idata; |
| 598 |
else |
| 599 |
odata = d->jazz_timer_value; |
| 600 |
break; |
| 601 |
default: |
| 602 |
if (writeflag == MEM_WRITE) { |
| 603 |
fatal("[ jazzio: unimplemented write to address 0x%x" |
| 604 |
", data=0x%02x ]\n", (int)relative_addr, |
| 605 |
(int)idata); |
| 606 |
} else { |
| 607 |
fatal("[ jazzio: unimplemented read from address 0x%x" |
| 608 |
" ]\n", (int)relative_addr); |
| 609 |
} |
| 610 |
} |
| 611 |
|
| 612 |
/* This is needed by Windows NT during startup: */ |
| 613 |
INTERRUPT_DEASSERT(d->mips_irq_3); |
| 614 |
|
| 615 |
if (writeflag == MEM_READ) |
| 616 |
memory_writemax64(cpu, data, len, odata); |
| 617 |
|
| 618 |
return 1; |
| 619 |
} |
| 620 |
|
| 621 |
|
| 622 |
DEVINIT(jazz) |
| 623 |
{ |
| 624 |
char tmpstr[300]; |
| 625 |
int i; |
| 626 |
struct jazz_data *d = malloc(sizeof(struct jazz_data)); |
| 627 |
if (d == NULL) { |
| 628 |
fprintf(stderr, "out of memory\n"); |
| 629 |
exit(1); |
| 630 |
} |
| 631 |
memset(d, 0, sizeof(struct jazz_data)); |
| 632 |
|
| 633 |
d->cpu = devinit->machine->cpus[0]; /* TODO */ |
| 634 |
|
| 635 |
d->isa_int_enable_mask = 0xffff; |
| 636 |
|
| 637 |
/* |
| 638 |
* Register 16 native JAZZ irqs, and 16 ISA irqs: |
| 639 |
* |
| 640 |
* emul[x].machine[y].cpu[z].jazz.%i (native) |
| 641 |
* emul[x].machine[y].cpu[z].jazz.isa.%i (ISA) |
| 642 |
*/ |
| 643 |
for (i=0; i<16; i++) { |
| 644 |
struct interrupt template; |
| 645 |
char n[300]; |
| 646 |
snprintf(n, sizeof(n), "%s.jazz.%i", |
| 647 |
devinit->interrupt_path, i); |
| 648 |
memset(&template, 0, sizeof(template)); |
| 649 |
template.line = i; |
| 650 |
template.name = n; |
| 651 |
template.extra = d; |
| 652 |
template.interrupt_assert = jazz_interrupt_assert; |
| 653 |
template.interrupt_deassert = jazz_interrupt_deassert; |
| 654 |
interrupt_handler_register(&template); |
| 655 |
} |
| 656 |
for (i=0; i<16; i++) { |
| 657 |
struct interrupt template; |
| 658 |
char n[300]; |
| 659 |
snprintf(n, sizeof(n), "%s.jazz.isa.%i", |
| 660 |
devinit->interrupt_path, i); |
| 661 |
memset(&template, 0, sizeof(template)); |
| 662 |
template.line = i; |
| 663 |
template.name = n; |
| 664 |
template.extra = d; |
| 665 |
template.interrupt_assert = jazz_isa_interrupt_assert; |
| 666 |
template.interrupt_deassert = jazz_isa_interrupt_deassert; |
| 667 |
interrupt_handler_register(&template); |
| 668 |
} |
| 669 |
|
| 670 |
/* Connect to MIPS CPU interrupt lines: */ |
| 671 |
snprintf(tmpstr, sizeof(tmpstr), "%s.3", devinit->interrupt_path); |
| 672 |
INTERRUPT_CONNECT(tmpstr, d->mips_irq_3); |
| 673 |
snprintf(tmpstr, sizeof(tmpstr), "%s.4", devinit->interrupt_path); |
| 674 |
INTERRUPT_CONNECT(tmpstr, d->mips_irq_4); |
| 675 |
snprintf(tmpstr, sizeof(tmpstr), "%s.6", devinit->interrupt_path); |
| 676 |
INTERRUPT_CONNECT(tmpstr, d->mips_irq_6); |
| 677 |
|
| 678 |
/* Connect to JAZZ timer interrupt: */ |
| 679 |
snprintf(tmpstr, sizeof(tmpstr), "%s.jazz.%i", |
| 680 |
devinit->interrupt_path, PICA_TIMER_IRQ); |
| 681 |
INTERRUPT_CONNECT(tmpstr, d->jazz_timer_irq); |
| 682 |
|
| 683 |
memory_device_register(devinit->machine->memory, "jazz", |
| 684 |
devinit->addr, DEV_JAZZ_LENGTH, |
| 685 |
dev_jazz_access, (void *)d, DM_DEFAULT, NULL); |
| 686 |
|
| 687 |
/* At least for Magnum and Pica-61: */ |
| 688 |
memory_device_register(devinit->machine->memory, "jazz_led", |
| 689 |
0x08000f000ULL, 4, dev_jazz_led_access, (void *)d, |
| 690 |
DM_DEFAULT, NULL); |
| 691 |
|
| 692 |
memory_device_register(devinit->machine->memory, "jazz_isa_20", |
| 693 |
0x90000020ULL, 2, dev_jazz_20_access, (void *)d, DM_DEFAULT, NULL); |
| 694 |
|
| 695 |
memory_device_register(devinit->machine->memory, "jazz_isa_a0", |
| 696 |
0x900000a0ULL, 2, dev_jazz_a0_access, (void *)d, DM_DEFAULT, NULL); |
| 697 |
|
| 698 |
memory_device_register(devinit->machine->memory, "pica_jazzio", |
| 699 |
0xf0000000ULL, 4, dev_jazz_jazzio_access, (void *)d, |
| 700 |
DM_DEFAULT, NULL); |
| 701 |
|
| 702 |
/* Add a timer, hardcoded to 100 Hz. TODO: Don't hardcode! */ |
| 703 |
d->timer = timer_add(100.0, timer_tick, d); |
| 704 |
machine_add_tickfunction(devinit->machine, dev_jazz_tick, |
| 705 |
d, DEV_JAZZ_TICKSHIFT, 0.0); |
| 706 |
|
| 707 |
devinit->return_ptr = d; |
| 708 |
|
| 709 |
return 1; |
| 710 |
} |
| 711 |
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