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/* |
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* Copyright (C) 2006-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_mb8696x.c,v 1.3 2007/02/03 20:14:23 debug Exp $ |
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* |
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* Fujitsu MB8696x Ethernet interface. |
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* |
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* Used as the LAN adapter (MB86967) in the Dreamcast machine mode. |
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* |
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* |
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* Note: This is just a bogus module so far. |
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* |
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* (TODO: "Reverse engineer" more of NetBSD's mb86960.c to implement this.) |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <sys/time.h> |
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|
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#include "cpu.h" |
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#include "device.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "net.h" |
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|
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#include "mb86960reg.h" |
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|
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|
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#ifdef UNSTABLE_DEVEL |
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#define MB8696X_DEBUG |
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#endif |
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|
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#ifdef MB8696X_DEBUG |
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#define debug fatal |
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#endif |
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|
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struct mb8696x_data { |
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int addr_mult; |
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|
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/* |
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* Registers: |
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* |
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* reg contains 32 registers. However, registers 8..15 are bank- |
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* switched, based on a setting in FE_DLCR7. mar_8_15 are "multicast |
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* address registers", and bmpr_8_15 are "buffer memory port |
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* registers". |
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*/ |
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uint8_t reg[MB8696X_NREGS]; |
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uint8_t mar_8_15[8]; |
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uint8_t bmpr_8_15[8]; |
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|
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/* EEPROM contents and internal state during a read operation: */ |
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uint8_t eeprom[FE_EEPROM_SIZE]; |
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int eeprom_state; |
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uint8_t eeprom_bit_count; |
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uint8_t eeprom_command; |
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uint16_t eeprom_data; |
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}; |
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|
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#define EEPROM_STATE_NOTHING 0 |
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#define EEPROM_STATE_READY 1 /* Waiting for start bit */ |
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#define EEPROM_STATE_COMMAND 2 /* Waiting for 8 command bits */ |
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#define EEPROM_STATE_READ 3 |
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|
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|
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DEVICE_ACCESS(mb8696x) |
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{ |
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struct mb8696x_data *d = (struct mb8696x_data *) extra; |
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uint64_t idata = 0, odata = 0; |
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uint8_t *reg_ptr; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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|
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relative_addr /= d->addr_mult; |
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|
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/* |
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* Default result on reads: (Note special treatment of banked regs.) |
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*/ |
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reg_ptr = &d->reg[relative_addr]; |
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if (relative_addr >= 8 && relative_addr <= 15 && |
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(d->reg[FE_DLCR7] & FE_D7_RBS) == FE_D7_RBS_MAR) |
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reg_ptr = &d->mar_8_15[relative_addr - 8]; |
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if (relative_addr >= 8 && relative_addr <= 15 && |
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(d->reg[FE_DLCR7] & FE_D7_RBS) == FE_D7_RBS_BMPR) |
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reg_ptr = &d->bmpr_8_15[relative_addr - 8]; |
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|
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odata = *reg_ptr; |
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|
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|
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switch (relative_addr) { |
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|
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case FE_DLCR0: /* TX interrupt status */ |
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case FE_DLCR1: /* RX interrupt status */ |
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/* Write-1-to-clear: */ |
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if (writeflag == MEM_WRITE) |
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(*reg_ptr) &= ~idata; |
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|
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/* TODO: reassert interrupts */ |
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|
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break; |
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|
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case FE_DLCR2: /* TX interrupt control */ |
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case FE_DLCR3: /* RX interrupt control */ |
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if (writeflag == MEM_WRITE) |
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(*reg_ptr) = idata; |
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|
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/* TODO: reassert interrupts */ |
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|
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break; |
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|
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case FE_DLCR6: |
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case FE_DLCR8: /* Ethernet addr byte 0 */ |
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case FE_DLCR9: /* Ethernet addr byte 1 */ |
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case FE_DLCR10: /* Ethernet addr byte 2 */ |
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case FE_DLCR11: /* Ethernet addr byte 3 */ |
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case FE_DLCR12: /* Ethernet addr byte 4 */ |
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case FE_DLCR13: /* Ethernet addr byte 5 */ |
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if (writeflag == MEM_WRITE) |
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(*reg_ptr) = idata; |
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break; |
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|
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case FE_DLCR7: |
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if (writeflag == MEM_WRITE) { |
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/* Identification cannot be overwritten: */ |
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(*reg_ptr) &= FE_D7_IDENT; |
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(*reg_ptr) |= (idata & ~FE_D7_IDENT); |
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} |
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break; |
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|
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case FE_BMPR16: |
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/* EEPROM control */ |
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if (writeflag == MEM_WRITE) { |
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if (idata & ~(FE_B16_DOUT | FE_B16_DIN | |
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FE_B16_SELECT | FE_B16_CLOCK)) { |
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fatal("mb8696x: UNIMPLEMENTED bits when " |
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"writing to FE_BMPR16: 0x%02x\n", |
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(int)idata); |
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exit(1); |
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} |
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|
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/* Dropped out of select state? */ |
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if (!(idata & FE_B16_SELECT)) |
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d->eeprom_state = EEPROM_STATE_NOTHING; |
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|
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/* Switching to select state? */ |
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if (!((*reg_ptr) & FE_B16_SELECT) && |
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idata & FE_B16_SELECT) |
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d->eeprom_state = EEPROM_STATE_READY; |
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|
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/* Bit clock? */ |
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if (!((*reg_ptr) & FE_B16_CLOCK) && |
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idata & FE_B16_CLOCK) { |
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int bit = d->reg[FE_BMPR17] & FE_B17_DATA? 1:0; |
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switch (d->eeprom_state) { |
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case EEPROM_STATE_READY: |
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d->eeprom_state = EEPROM_STATE_COMMAND; |
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d->eeprom_bit_count = 0; |
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break; |
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case EEPROM_STATE_COMMAND: |
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d->eeprom_bit_count ++; |
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d->eeprom_command <<= 1; |
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d->eeprom_command |= bit; |
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if (d->eeprom_bit_count == 8) { |
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int addr = (d->eeprom_command |
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& 0x7f) << 1; |
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/* printf("COMMAND=%08x\n", |
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d->eeprom_command); */ |
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if (!(d->eeprom_command&0x80)) { |
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fatal("WRITES to the " |
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"EEPROM are not yet" |
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" implemented.\n"); |
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exit(1); |
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} |
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/* This is a read command. */ |
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d->eeprom_bit_count = 0; |
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d->eeprom_state = |
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EEPROM_STATE_READ; |
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d->eeprom_data = d->eeprom[addr] |
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* 256 + d->eeprom[addr+1]; |
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} |
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break; |
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case EEPROM_STATE_READ: |
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d->reg[FE_BMPR17] = 0; |
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if (d->eeprom_data & 0x8000) |
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d->reg[FE_BMPR17] = FE_B17_DATA; |
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d->eeprom_data <<= 1; |
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d->eeprom_bit_count ++; |
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if (d->eeprom_bit_count > 16) |
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fatal("[ WARNING: more than 16" |
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" bits of EEPROM data " |
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"read? ]\n"); |
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break; |
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} |
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} |
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|
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(*reg_ptr) = idata; |
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} |
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break; |
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|
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case FE_BMPR17: |
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/* EEPROM data */ |
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if (writeflag == MEM_WRITE) { |
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if (idata & ~FE_B17_DATA) { |
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fatal("mb8696x: UNIMPLEMENTED bits when " |
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"writing to FE_BMPR17: 0x%02x\n", |
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(int)idata); |
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exit(1); |
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} |
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(*reg_ptr) = idata; |
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} |
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break; |
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|
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default: |
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{ |
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char *bank = ""; |
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if ((d->reg[FE_DLCR7] & FE_D7_RBS) == FE_D7_RBS_MAR) |
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bank = " (bank MAR)"; |
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if ((d->reg[FE_DLCR7] & FE_D7_RBS) == FE_D7_RBS_BMPR) |
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bank = " (bank BMPR)"; |
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if (writeflag == MEM_READ) { |
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fatal("[ mb8696x: read from UNIMPLEMENTED reg " |
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"%i%s ]\n", (int)relative_addr, bank); |
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} else { |
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fatal("[ mb8696x: write to UNIMPLEMENTED reg " |
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"%i%s: 0x%02x ]\n", (int)relative_addr, |
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bank, (int)idata); |
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} |
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|
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#ifdef MB8696X_DEBUG |
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exit(1); |
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#endif |
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} |
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} |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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DEVINIT(mb8696x) |
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{ |
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struct machine *machine = devinit->machine; |
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struct mb8696x_data *d = malloc(sizeof(struct mb8696x_data)); |
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if (d == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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memset(d, 0, sizeof(struct mb8696x_data)); |
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d->addr_mult = devinit->addr_mult; |
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|
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memory_device_register(machine->memory, devinit->name, devinit->addr, |
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MB8696X_NREGS * d->addr_mult, dev_mb8696x_access, d, |
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DM_DEFAULT, NULL); |
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|
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/* NetBSD/dreamcast expects ident = 86967. */ |
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d->reg[FE_DLCR7] = FE_D7_IDENT_86967; |
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|
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/* |
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* Generate the MAC address, both in the first 6 bytes of the |
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* EEPROM, and in DLCR8..13: |
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*/ |
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net_generate_unique_mac(machine, &d->eeprom[0]); |
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memcpy(&d->reg[FE_DLCR8], &d->eeprom[0], 6); |
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|
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return 1; |
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} |
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