| 1 |
dpavlin |
4 |
/* gxemul: $Id: impactsr-bsd.h,v 1.2 2005/03/05 12:34:02 debug Exp $ */ |
| 2 |
|
|
|
| 3 |
|
|
#ifndef IMPACTSR_H |
| 4 |
|
|
#define IMPACTSR_H |
| 5 |
|
|
|
| 6 |
|
|
/* |
| 7 |
|
|
* Copyright (C) 2004 by Stanislaw Skowronek. All rights reserved. |
| 8 |
|
|
* |
| 9 |
|
|
* Redistribution and use in source and binary forms, with or without |
| 10 |
|
|
* modification, are permitted provided that the following conditions are met: |
| 11 |
|
|
* |
| 12 |
|
|
* 1. Redistributions of source code must retain the above copyright |
| 13 |
|
|
* notice, this list of conditions and the following disclaimer. |
| 14 |
|
|
* 2. Redistributions in binary form must reproduce the above copyright |
| 15 |
|
|
* notice, this list of conditions and the following disclaimer in the |
| 16 |
|
|
* documentation and/or other materials provided with the distribution. |
| 17 |
|
|
* |
| 18 |
|
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 19 |
|
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 |
|
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 |
|
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 22 |
|
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 23 |
|
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 24 |
|
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 25 |
|
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 26 |
|
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 27 |
|
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 28 |
|
|
* SUCH DAMAGE. |
| 29 |
|
|
*/ |
| 30 |
|
|
|
| 31 |
|
|
/* Convenient access macros */ |
| 32 |
|
|
#define IMPACTSR_REG64(vma,off) (*(volatile unsigned long *)((vma)+(off))) |
| 33 |
|
|
#define IMPACTSR_REG32(vma,off) (*(volatile unsigned int *)((vma)+(off))) |
| 34 |
|
|
#define IMPACTSR_REG16(vma,off) (*(volatile unsigned short *)((vma)+(off))) |
| 35 |
|
|
#define IMPACTSR_REG8(vma,off) (*(volatile unsigned char *)((vma)+(off))) |
| 36 |
|
|
|
| 37 |
|
|
/* ImpactSR (HQ4) register offsets */ |
| 38 |
|
|
#define IMPACTSR_CFIFO(vma) IMPACTSR_REG64(vma,0x20400) |
| 39 |
|
|
#define IMPACTSR_CFIFOW(vma) IMPACTSR_REG32(vma,0x20400) |
| 40 |
|
|
#define IMPACTSR_CFIFOP(vma) IMPACTSR_REG64(vma,0x130400) |
| 41 |
|
|
#define IMPACTSR_CFIFOPW(vma) IMPACTSR_REG32(vma,0x130400) |
| 42 |
|
|
|
| 43 |
|
|
#define IMPACTSR_STATUS(vma) IMPACTSR_REG32(vma,0x20000) |
| 44 |
|
|
#define IMPACTSR_FIFOSTATUS(vma) IMPACTSR_REG32(vma,0x20008) |
| 45 |
|
|
#define IMPACTSR_GIOSTATUS(vma) IMPACTSR_REG32(vma,0x20100) |
| 46 |
|
|
#define IMPACTSR_DMABUSY(vma) IMPACTSR_REG32(vma,0x20200) |
| 47 |
|
|
|
| 48 |
|
|
#define IMPACTSR_RESTATUS(vma) IMPACTSR_REG32(vma,0x2c578) |
| 49 |
|
|
|
| 50 |
|
|
#define IMPACTSR_CFIFO_HW(vma) IMPACTSR_REG32(vma,0x40000) |
| 51 |
|
|
#define IMPACTSR_CFIFO_LW(vma) IMPACTSR_REG32(vma,0x40008) |
| 52 |
|
|
#define IMPACTSR_CFIFO_DELAY(vma) IMPACTSR_REG32(vma,0x40010) |
| 53 |
|
|
#define IMPACTSR_DFIFO_HW(vma) IMPACTSR_REG32(vma,0x40020) |
| 54 |
|
|
#define IMPACTSR_DFIFO_LW(vma) IMPACTSR_REG32(vma,0x40028) |
| 55 |
|
|
#define IMPACTSR_DFIFO_DELAY(vma) IMPACTSR_REG32(vma,0x40030) |
| 56 |
|
|
|
| 57 |
|
|
#define IMPACTSR_XMAP_PP1SELECT(vma) IMPACTSR_REG8(vma,0x71c08) |
| 58 |
|
|
#define IMPACTSR_XMAP_INDEX(vma) IMPACTSR_REG8(vma,0x71c88) |
| 59 |
|
|
#define IMPACTSR_XMAP_CONFIG(vma) IMPACTSR_REG32(vma,0x71d00) |
| 60 |
|
|
#define IMPACTSR_XMAP_CONFIGB(vma) IMPACTSR_REG8(vma,0x71d08) |
| 61 |
|
|
#define IMPACTSR_XMAP_BUF_SELECT(vma) IMPACTSR_REG32(vma,0x71d80) |
| 62 |
|
|
#define IMPACTSR_XMAP_MAIN_MODE(vma) IMPACTSR_REG32(vma,0x71e00) |
| 63 |
|
|
#define IMPACTSR_XMAP_OVERLAY_MODE(vma) IMPACTSR_REG32(vma,0x71e80) |
| 64 |
|
|
#define IMPACTSR_XMAP_DIB(vma) IMPACTSR_REG32(vma,0x71f00) |
| 65 |
|
|
#define IMPACTSR_XMAP_DIB_DW(vma) IMPACTSR_REG32(vma,0x71f40) |
| 66 |
|
|
#define IMPACTSR_XMAP_RE_RAC(vma) IMPACTSR_REG32(vma,0x71f80) |
| 67 |
|
|
|
| 68 |
|
|
#define IMPACTSR_VC3_INDEX(vma) IMPACTSR_REG8(vma,0x72008) |
| 69 |
|
|
#define IMPACTSR_VC3_INDEXDATA(vma) IMPACTSR_REG32(vma,0x72038) |
| 70 |
|
|
#define IMPACTSR_VC3_DATA(vma) IMPACTSR_REG16(vma,0x720b0) |
| 71 |
|
|
#define IMPACTSR_VC3_RAM(vma) IMPACTSR_REG16(vma,0x72190) |
| 72 |
|
|
|
| 73 |
|
|
/* FIFO status */ |
| 74 |
|
|
#define IMPACTSR_CFIFO_MAX 128 |
| 75 |
|
|
#define IMPACTSR_BFIFO_MAX 16 |
| 76 |
|
|
|
| 77 |
|
|
/* Commands for CFIFO */ |
| 78 |
|
|
#define IMPACTSR_CMD_WRITERSS(reg,val) (((0x00180004L|((reg)<<8))<<32)|((unsigned)(val)&0xffffffff)) |
| 79 |
|
|
#define IMPACTSR_CMD_EXECRSS(reg,val) (((0x001c0004L|((reg)<<8))<<32)|((unsigned)(val)&0xffffffff)) |
| 80 |
|
|
|
| 81 |
|
|
#define IMPACTSR_CMD_GLINE_XSTARTF(v) IMPACTSR_CMD_WRITERSS(0x00c,v) |
| 82 |
|
|
#define IMPACTSR_CMD_IR_ALIAS(v) IMPACTSR_CMD_EXECRSS(0x045,v) |
| 83 |
|
|
#define IMPACTSR_CMD_BLOCKXYSTARTI(x,y) IMPACTSR_CMD_WRITERSS(0x046,((x)<<16)|(y)) |
| 84 |
|
|
#define IMPACTSR_CMD_BLOCKXYENDI(x,y) IMPACTSR_CMD_WRITERSS(0x047,((x)<<16)|(y)) |
| 85 |
|
|
#define IMPACTSR_CMD_PACKEDCOLOR(v) IMPACTSR_CMD_WRITERSS(0x05b,v) |
| 86 |
|
|
#define IMPACTSR_CMD_RED(v) IMPACTSR_CMD_WRITERSS(0x05c,v) |
| 87 |
|
|
#define IMPACTSR_CMD_ALPHA(v) IMPACTSR_CMD_WRITERSS(0x05f,v) |
| 88 |
|
|
#define IMPACTSR_CMD_CHAR(v) IMPACTSR_CMD_EXECRSS(0x070,v) |
| 89 |
|
|
#define IMPACTSR_CMD_CHAR_H(v) IMPACTSR_CMD_WRITERSS(0x070,v) |
| 90 |
|
|
#define IMPACTSR_CMD_CHAR_L(v) IMPACTSR_CMD_EXECRSS(0x071,v) |
| 91 |
|
|
#define IMPACTSR_CMD_XFRCONTROL(v) IMPACTSR_CMD_WRITERSS(0x102,v) |
| 92 |
|
|
#define IMPACTSR_CMD_FILLMODE(v) IMPACTSR_CMD_WRITERSS(0x110,v) |
| 93 |
|
|
#define IMPACTSR_CMD_CONFIG(v) IMPACTSR_CMD_WRITERSS(0x112,v) |
| 94 |
|
|
#define IMPACTSR_CMD_XYWIN(x,y) IMPACTSR_CMD_WRITERSS(0x115,((y)<<16)|(x)) |
| 95 |
|
|
#define IMPACTSR_CMD_BKGRD_RG(v) IMPACTSR_CMD_WRITERSS(0x140,((v)<<8)) |
| 96 |
|
|
#define IMPACTSR_CMD_BKGRD_BA(v) IMPACTSR_CMD_WRITERSS(0x141,((v)<<8)) |
| 97 |
|
|
#define IMPACTSR_CMD_WINMODE(v) IMPACTSR_CMD_WRITERSS(0x14f,v) |
| 98 |
|
|
#define IMPACTSR_CMD_XFRSIZE(x,y) IMPACTSR_CMD_WRITERSS(0x153,((y)<<16)|(x)) |
| 99 |
|
|
#define IMPACTSR_CMD_XFRMASKLO(v) IMPACTSR_CMD_WRITERSS(0x156,v) |
| 100 |
|
|
#define IMPACTSR_CMD_XFRMASKHI(v) IMPACTSR_CMD_WRITERSS(0x157,v) |
| 101 |
|
|
#define IMPACTSR_CMD_XFRCOUNTERS(x,y) IMPACTSR_CMD_WRITERSS(0x158,((y)<<16)|(x)) |
| 102 |
|
|
#define IMPACTSR_CMD_XFRMODE(v) IMPACTSR_CMD_WRITERSS(0x159,v) |
| 103 |
|
|
#define IMPACTSR_CMD_RE_TOGGLECNTX(v) IMPACTSR_CMD_WRITERSS(0x15f,v) |
| 104 |
|
|
#define IMPACTSR_CMD_PIXCMD(v) IMPACTSR_CMD_WRITERSS(0x160,v) |
| 105 |
|
|
#define IMPACTSR_CMD_PP1FILLMODE(m,o) IMPACTSR_CMD_WRITERSS(0x161,(m)|(o<<26)) |
| 106 |
|
|
#define IMPACTSR_CMD_COLORMASKMSBS(v) IMPACTSR_CMD_WRITERSS(0x162,v) |
| 107 |
|
|
#define IMPACTSR_CMD_COLORMASKLSBSA(v) IMPACTSR_CMD_WRITERSS(0x163,v) |
| 108 |
|
|
#define IMPACTSR_CMD_COLORMASKLSBSB(v) IMPACTSR_CMD_WRITERSS(0x164,v) |
| 109 |
|
|
#define IMPACTSR_CMD_DRBPOINTERS(v) IMPACTSR_CMD_WRITERSS(0x16d,v) |
| 110 |
|
|
|
| 111 |
|
|
#define IMPACTSR_CMD_HQ_PIXELFORMAT(v) (0x000c000400000000L|((unsigned)(v)&0xffffffff)) |
| 112 |
|
|
#define IMPACTSR_CMD_HQ_SCANWIDTH(v) (0x000a020400000000L|((unsigned)(v)&0xffffffff)) |
| 113 |
|
|
#define IMPACTSR_CMD_HQ_DMATYPE(v) (0x000a060400000000L|((unsigned)(v)&0xffffffff)) |
| 114 |
|
|
#define IMPACTSR_CMD_HQ_PG_LIST_0(v) (0x0008000400000000L|((unsigned)(v)&0xffffffff)) |
| 115 |
|
|
#define IMPACTSR_CMD_HQ_PG_WIDTH(v) (0x0008040400000000L|((unsigned)(v)&0xffffffff)) |
| 116 |
|
|
#define IMPACTSR_CMD_HQ_PG_OFFSET(v) (0x0008050400000000L|((unsigned)(v)&0xffffffff)) |
| 117 |
|
|
#define IMPACTSR_CMD_HQ_PG_STARTADDR(v) (0x0008060400000000L|((unsigned)(v)&0xffffffff)) |
| 118 |
|
|
#define IMPACTSR_CMD_HQ_PG_LINECNT(v) (0x0008070400000000L|((unsigned)(v)&0xffffffff)) |
| 119 |
|
|
#define IMPACTSR_CMD_HQ_PG_WIDTHA(v) (0x0008080400000000L|((unsigned)(v)&0xffffffff)) |
| 120 |
|
|
#define IMPACTSR_CMD_HQ_TXBASE(p) (0x00482008|((p)<<9)) |
| 121 |
|
|
#define IMPACTSR_CMD_HQ_TXMAX(p,v) (0x0048300400000000L|((unsigned)(v)&0xffffffff)|((unsigned long)(p)<<40)) |
| 122 |
|
|
#define IMPACTSR_CMD_HQ_PGBITS(p,v) (0x00482b0400000000L|((unsigned)(v)&0xffffffff)|((unsigned long)(p)<<40)) |
| 123 |
|
|
#define IMPACTSR_CMD_HQ_PGSIZE(v) (0x00482a0400000000L|((unsigned)(v)&0xffffffff)) |
| 124 |
|
|
#define IMPACTSR_CMD_HQ_STACKPTR(v) (0x00483a0400000000L|((unsigned)(v)&0xffffffff)) |
| 125 |
|
|
|
| 126 |
|
|
/* Logic operations for the PP1 (SI=source invert, DI=dest invert, RI=result invert) */ |
| 127 |
|
|
#define IMPACTSR_LO_COPY 0 |
| 128 |
|
|
#define IMPACTSR_LO_DIAND 1 |
| 129 |
|
|
#define IMPACTSR_LO_AND 2 |
| 130 |
|
|
#define IMPACTSR_LO_CLEAR 3 |
| 131 |
|
|
#define IMPACTSR_LO_OR 4 |
| 132 |
|
|
#define IMPACTSR_LO_XOR 5 |
| 133 |
|
|
#define IMPACTSR_LO_NOP 6 |
| 134 |
|
|
#define IMPACTSR_LO_SIAND 7 |
| 135 |
|
|
#define IMPACTSR_LO_DIOR 8 |
| 136 |
|
|
#define IMPACTSR_LO_RINOP 9 |
| 137 |
|
|
#define IMPACTSR_LO_RIXOR 10 |
| 138 |
|
|
#define IMPACTSR_LO_RIOR 11 |
| 139 |
|
|
#define IMPACTSR_LO_SET 12 |
| 140 |
|
|
#define IMPACTSR_LO_RIAND 13 |
| 141 |
|
|
#define IMPACTSR_LO_SIOR 14 |
| 142 |
|
|
#define IMPACTSR_LO_RICOPY 15 |
| 143 |
|
|
|
| 144 |
|
|
#endif /* IMPACTSR_H */ |
Parent Directory
| 
Revision Log