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#ifndef CPU_IA64_H |
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#define CPU_IA64_H |
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|
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/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_ia64.h,v 1.14 2006/07/16 13:32:27 debug Exp $ |
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*/ |
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|
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#include "misc.h" |
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|
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|
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struct cpu_family; |
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|
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#define IA64_N_IC_ARGS 3 |
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#define IA64_INSTR_ALIGNMENT_SHIFT 4 |
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#define IA64_IC_ENTRIES_SHIFT 8 |
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#define IA64_IC_ENTRIES_PER_PAGE (1 << IA64_IC_ENTRIES_SHIFT) |
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#define IA64_PC_TO_IC_ENTRY(a) (((a)>>IA64_INSTR_ALIGNMENT_SHIFT) \ |
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& (IA64_IC_ENTRIES_PER_PAGE-1)) |
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#define IA64_ADDR_TO_PAGENR(a) ((a) >> (IA64_IC_ENTRIES_SHIFT \ |
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+ IA64_INSTR_ALIGNMENT_SHIFT)) |
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|
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#define IA64_L2N 17 |
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#define IA64_L3N 18 |
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|
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DYNTRANS_MISC_DECLARATIONS(ia64,IA64,uint64_t) |
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DYNTRANS_MISC64_DECLARATIONS(ia64,IA64,uint8_t) |
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|
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#define IA64_MAX_VPH_TLB_ENTRIES 128 |
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|
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#define N_IA64_REG 128 |
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|
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struct ia64_cpu { |
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/* TODO */ |
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uint64_t r[N_IA64_REG]; |
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|
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|
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/* |
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* Instruction translation cache and Virtual->Physical->Host |
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* address translation: |
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*/ |
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DYNTRANS_ITC(ia64) |
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VPH_TLBS(ia64,IA64) |
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VPH64(ia64,IA64,uint8_t) |
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}; |
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|
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|
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/* cpu_ia64.c: */ |
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int ia64_run_instr(struct cpu *cpu); |
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void ia64_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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void ia64_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
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void ia64_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
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void ia64_init_64bit_dummy_tables(struct cpu *cpu); |
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int ia64_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
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unsigned char *data, size_t len, int writeflag, int cache_flags); |
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int ia64_userland_memory_rw(struct cpu *cpu, struct memory *mem, |
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uint64_t vaddr, unsigned char *data, size_t len, int writeflag, |
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int cache_flags); |
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int ia64_cpu_family_init(struct cpu_family *); |
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|
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|
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#endif /* CPU_IA64_H */ |
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