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dpavlin |
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/* gxemul: $Id: bireg.h,v 1.2 2005/03/05 12:34:02 debug Exp $ */ |
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/* $NetBSD: bireg.h,v 1.7 2000/07/06 17:47:02 ragge Exp $ */ |
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#ifndef BIREG_H |
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#define BIREG_H |
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/* |
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* Copyright (c) 1988 Regents of the University of California. |
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* All rights reserved. |
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* |
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* This code is derived from software contributed to Berkeley by |
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* Chris Torek. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed by the University of |
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* California, Berkeley and its contributors. |
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* 4. Neither the name of the University nor the names of its contributors |
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* may be used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* @(#)bireg.h 7.3 (Berkeley) 6/28/90 |
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*/ |
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/* |
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* VAXBI node definitions. |
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*/ |
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/* |
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* BI node addresses |
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*/ |
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#define BI_NODESIZE 0x2000 /* Size of one BI node */ |
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#define BI_NODE(node) (BI_NODESIZE * (node)) |
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#define BI_BASE(bi,nod) ((0x20000000 + (bi) * 0x2000000) + BI_NODE(nod)) |
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#define MAXNBI 16 /* Spec says there can be 16 anyway */ |
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#define NNODEBI 16 /* 16 nodes per BI */ |
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#define BI_PROBE 0x80000 /* CPU on 8200, NBIA on 8800 */ |
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/* |
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* BI nodes all start with BI interface registers (those on the BIIC chip). |
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* These are followed with interface-specific registers. |
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* |
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* NB: This structure does NOT include the four GPRs (not anymore!) |
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* |
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* 990712: The structs not used anymore due to conversion to bus.h. |
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*/ |
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#ifdef notdef |
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struct biiregs { |
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u_short bi_dtype; /* device type */ |
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u_short bi_revs; /* revisions */ |
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u_long bi_csr; /* control and status register */ |
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u_long bi_ber; /* bus error register */ |
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u_long bi_eintrcsr; /* error interrupt control register */ |
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u_long bi_intrdes; /* interrupt destination register */ |
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/* the rest are not required for all nodes */ |
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u_long bi_ipintrmsk; /* IP interrupt mask register */ |
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u_long bi_fipsdes; /* Force-Bit IPINTR/STOP destination reg */ |
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u_long bi_ipintrsrc; /* IPINTR source register */ |
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u_long bi_sadr; /* starting address register */ |
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u_long bi_eadr; /* ending address register */ |
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u_long bi_bcicsr; /* BCI control and status register */ |
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u_long bi_wstat; /* write status register */ |
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u_long bi_fipscmd; /* Force-Bit IPINTR/STOP command reg */ |
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u_long bi_xxx1[3]; /* unused */ |
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u_long bi_uintrcsr; /* user interface interrupt control reg */ |
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u_long bi_xxx2[43]; /* unused */ |
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/* although these are on the BIIC, their interpretation varies */ |
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/* u_long bi_gpr[4]; */ /* general purpose registers */ |
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}; |
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/* |
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* A generic BI node. |
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*/ |
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struct bi_node { |
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struct biiregs biic; /* interface */ |
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u_long bi_xxx[1988]; /* pad to 8K */ |
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}; |
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/* |
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* A cpu node. |
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*/ |
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struct bi_cpu { |
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struct biiregs biic; /* interface chip */ |
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u_long bi_gpr[4]; /* gprs (unused) */ |
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u_long bi_sosr; /* slave only status register */ |
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u_long bi_xxx[63]; /* pad */ |
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u_long bi_rxcd; /* receive console data register */ |
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}; |
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#endif |
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#define BIREG_DTYPE 0x00 |
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#define BIREG_VAXBICSR 0x04 |
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#define BIREG_BER 0x08 |
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#define BIREG_EINTRCSR 0x0c |
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#define BIREG_INTRDES 0x10 |
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#define BIREG_IPINTRMSK 0x14 |
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#define BIREG_FIPSDES 0x18 |
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#define BIREG_IPINTRSRC 0x1c |
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#define BIREG_SADR 0x20 |
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#define BIREG_EADR 0x24 |
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#define BIREG_BCICSR 0x28 |
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#define BIREG_WSTAT 0x2c |
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#define BIREG_FIPSCMD 0x30 |
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#define BIREG_UINTRCSR 0x40 |
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/* device types */ |
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#define BIDT_MS820 0x0001 /* MS820 memory board */ |
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#define BIDT_DRB32 0x0101 /* DRB32 (MFA) Supercomputer gateway */ |
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#define BIDT_DWBUA 0x0102 /* DWBUA Unibus adapter */ |
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#define BIDT_KLESI 0x0103 /* KLESI-B (DWBLA) adapter */ |
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#define BIDT_HSB70 0x4104 /* HSB70 */ |
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#define BIDT_KA820 0x0105 /* KA820 cpu */ |
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#define BIDT_DB88 0x0106 /* DB88 (NBI) adapter */ |
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#define BIDT_DWMBA 0x2107 /* XMI-BI (XBI) adapter */ |
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#define BIDT_DWMBB 0x0107 /* XMI-BI (XBI) adapter */ |
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#define BIDT_CIBCA 0x0108 /* Computer Interconnect adapter */ |
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#define BIDT_DMB32 0x0109 /* DMB32 (COMB) adapter */ |
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#define BIDT_BAA 0x010a /* BAA */ |
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#define BIDT_CIBCI 0x010b /* Computer Interconnect adapter (old) */ |
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#define BIDT_DEBNT 0x410b /* (AIE_TK70) Ethernet+TK50/TBK70 */ |
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#define BIDT_KA800 0x010c /* KA800 (ACP) slave processor */ |
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#define BIDT_KFBTA 0x410d /* RD/RX disk controller */ |
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#define BIDT_KDB50 0x010e /* KDB50 (BDA) disk controller */ |
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#define BIDT_DEBNK 0x410e /* (AIE_TK) BI Ethernet (Lance) + TK50 */ |
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#define BIDT_DEBNA 0x410f /* (AIE) BI Ethernet (Lance) adapter */ |
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#define BIDT_DEBNI 0x0118 /* (XNA) BI Ethernet adapter */ |
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/* bits in bi_csr */ |
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#define BICSR_IREV(x) ((u_char)((x) >> 24)) /* VAXBI interface rev */ |
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#define BICSR_TYPE(x) ((u_char)((x) >> 16)) /* BIIC type */ |
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#define BICSR_HES 0x8000 /* hard error summary */ |
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#define BICSR_SES 0x4000 /* soft error summary */ |
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#define BICSR_INIT 0x2000 /* initialise node */ |
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#define BICSR_BROKE 0x1000 /* broke */ |
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#define BICSR_STS 0x0800 /* self test status */ |
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#define BICSR_NRST 0x0400 /* node reset */ |
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#define BICSR_UWP 0x0100 /* unlock write pending */ |
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#define BICSR_HEIE 0x0080 /* hard error interrupt enable */ |
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#define BICSR_SEIE 0x0040 /* soft error interrupt enable */ |
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#define BICSR_ARB_MASK 0x0030 /* mask to get arbitration codes */ |
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#define BICSR_ARB_NONE 0x0030 /* no arbitration */ |
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#define BICSR_ARB_LOG 0x0020 /* low priority */ |
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#define BICSR_ARB_HIGH 0x0010 /* high priority */ |
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#define BICSR_ARB_RR 0x0000 /* round robin */ |
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#define BICSR_NODEMASK 0x000f /* node ID */ |
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#define BICSR_BITS \ |
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"\20\20HES\17SES\16INIT\15BROKE\14STS\13NRST\11UWP\10HEIE\7SEIE" |
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/* bits in bi_ber */ |
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#define BIBER_MBZ 0x8000fff0 |
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#define BIBER_NMR 0x40000000 /* no ack to multi-responder command */ |
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#define BIBER_MTCE 0x20000000 /* master transmit check error */ |
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#define BIBER_CTE 0x10000000 /* control transmit error */ |
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#define BIBER_MPE 0x08000000 /* master parity error */ |
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#define BIBER_ISE 0x04000000 /* interlock sequence error */ |
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#define BIBER_TDF 0x02000000 /* transmitter during fault */ |
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#define BIBER_IVE 0x01000000 /* ident vector error */ |
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#define BIBER_CPE 0x00800000 /* command parity error */ |
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#define BIBER_SPE 0x00400000 /* slave parity error */ |
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#define BIBER_RDS 0x00200000 /* read data substitute */ |
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#define BIBER_RTO 0x00100000 /* retry timeout */ |
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#define BIBER_STO 0x00080000 /* stall timeout */ |
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#define BIBER_BTO 0x00040000 /* bus timeout */ |
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#define BIBER_NEX 0x00020000 /* nonexistent address */ |
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#define BIBER_ICE 0x00010000 /* illegal confirmation error */ |
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#define BIBER_UPEN 0x00000008 /* user parity enable */ |
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#define BIBER_IPE 0x00000004 /* ID parity error */ |
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#define BIBER_CRD 0x00000002 /* corrected read data */ |
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#define BIBER_NPE 0x00000001 /* null bus parity error */ |
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#define BIBER_HARD 0x4fff0000 |
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#define BIBER_BITS \ |
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"\20\37NMR\36MTCE\35CTE\34MPE\33ISE\32TDF\31IVE\30CPE\ |
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\27SPE\26RDS\25RTO\24STO\23BTO\22NEX\21ICE\4UPEN\3IPE\2CRD\1NPE" |
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/* bits in bi_eintrcsr */ |
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#define BIEIC_INTRAB 0x01000000 /* interrupt abort */ |
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#define BIEIC_INTRC 0x00800000 /* interrupt complete */ |
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#define BIEIC_INTRSENT 0x00200000 /* interrupt command sent */ |
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#define BIEIC_INTRFORCE 0x00100000 /* interrupt force */ |
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#define BIEIC_LEVELMASK 0x000f0000 /* mask for interrupt levels */ |
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#define BIEIC_IPL17 0x00080000 /* ipl 0x17 */ |
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#define BIEIC_IPL16 0x00040000 /* ipl 0x16 */ |
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#define BIEIC_IPL15 0x00020000 /* ipl 0x15 */ |
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#define BIEIC_IPL14 0x00010000 /* ipl 0x14 */ |
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#define BIEIC_VECMASK 0x00003ffc /* vector mask for error intr */ |
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/* bits in bi_intrdes */ |
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#define BIDEST_MASK 0x0000ffff /* one bit per node to be intr'ed */ |
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/* bits in bi_ipintrmsk */ |
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#define BIIPINTR_MASK 0xffff0000 /* one per node to allow to ipintr */ |
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/* bits in bi_fipsdes */ |
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#define BIFIPSD_MASK 0x0000ffff |
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/* bits in bi_ipintrsrc */ |
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#define BIIPSRC_MASK 0xffff0000 |
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/* sadr and eadr are simple addresses */ |
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/* bits in bi_bcicsr */ |
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#define BCI_BURSTEN 0x00020000 /* burst mode enable */ |
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#define BCI_IPSTOP_FRC 0x00010000 /* ipintr/stop force */ |
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#define BCI_MCASTEN 0x00008000 /* multicast space enable */ |
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#define BCI_BCASTEN 0x00004000 /* broadcast enable */ |
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#define BCI_STOPEN 0x00002000 /* stop enable */ |
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#define BCI_RSRVDEN 0x00001000 /* reserved enable */ |
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#define BCI_IDENTEN 0x00000800 /* ident enable */ |
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#define BCI_INVALEN 0x00000400 /* inval enable */ |
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#define BCI_WINVEN 0x00000200 /* write invalidate enable */ |
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#define BCI_UINTEN 0x00000100 /* user interface csr space enable */ |
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#define BCI_BIICEN 0x00000080 /* BIIC csr space enable */ |
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#define BCI_INTEN 0x00000040 /* interrupt enable */ |
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#define BCI_IPINTEN 0x00000020 /* ipintr enable */ |
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#define BCI_PIPEEN 0x00000010 /* pipeline NXT enable */ |
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#define BCI_RTOEVEN 0x00000008 /* read timeout EV enable */ |
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#define BCI_BITS \ |
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"\20\22BURSTEN\21IPSTOP_FRC\20MCASTEN\ |
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\17BCASTEN\16STOPEN\15RSRVDEN\14IDENTEN\13INVALEN\12WINVEN\11UINTEN\ |
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\10BIICEN\7INTEN\6IPINTEN\5PIPEEN\4RTOEVEN" |
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/* bits in bi_wstat */ |
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#define BIW_GPR3 0x80000000 /* gpr 3 was written */ |
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#define BIW_GPR2 0x40000000 /* gpr 2 was written */ |
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#define BIW_GPR1 0x20000000 /* gpr 1 was written */ |
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#define BIW_GPR0 0x10000000 /* gpr 0 was written */ |
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/* bits in force-bit ipintr/stop command register */ |
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#define BIFIPSC_CMDMASK 0x0000f000 /* command */ |
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#define BIFIPSC_MIDEN 0x00000800 /* master ID enable */ |
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/* bits in bi_uintcsr */ |
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#define BIUI_INTAB 0xf0000000 /* interrupt abort level */ |
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#define BIUI_INTC 0x0f000000 /* interrupt complete bits */ |
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#define BIUI_SENT 0x00f00000 /* interrupt sent bits */ |
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#define BIUI_FORCE 0x000f0000 /* force interrupt level */ |
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#define BIUI_EVECEN 0x00008000 /* external vector enable */ |
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#define BIUI_VEC 0x00003ffc /* interrupt vector */ |
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/* tell if a bi device is a slave (hence has SOSR) */ |
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#define BIDT_ISSLAVE(x) (((x) & 0x7f00) == 0) |
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/* bits in bi_sosr */ |
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#define BISOSR_MEMSIZE 0x1ffc0000 /* memory size */ |
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#define BISOSR_BROKE 0x00001000 /* broke */ |
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/* bits in bi_rxcd */ |
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#define BIRXCD_BUSY2 0x80000000 /* busy 2 */ |
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#define BIRXCD_NODE2 0x0f000000 /* node id 2 */ |
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#define BIRXCD_CHAR2 0x00ff0000 /* character 2 */ |
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#define BIRXCD_BUSY1 0x00008000 /* busy 1 */ |
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#define BIRXCD_NODE1 0x00000f00 /* node id 1 */ |
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#define BIRXCD_CHAR1 0x000000ff /* character 1 */ |
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#endif |
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