src/devices/dev_gt.c

/*
 *  Copyright (C) 2003-2006  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *   
 *
 *  $Id: dev_gt.c,v 1.42 2006/07/21 16:55:41 debug Exp $
 *  
 *  Galileo Technology GT-64xxx PCI controller.
 *
 *      GT-64011        Used in Cobalt machines.
 *      GT-64120        Used in evbmips machines (Malta).
 *      GT-64260        Used in mvmeppc machines.
 *
 *  TODO: This more or less just a dummy device, so far. It happens to work
 *        with some NetBSD ports in some cases, and perhaps with Linux too,
 *        but it is not really working for anything else.
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "bus_pci.h"
#include "cpu.h"
#include "devices.h"
#include "machine.h"
#include "memory.h"
#include "misc.h"

#include "gtreg.h"


#define TICK_SHIFT              14

/*  #define debug fatal  */

#define PCI_PRODUCT_GALILEO_GT64011  0x4146    /*  GT-64011  */
#define PCI_PRODUCT_GALILEO_GT64120  0x4620    /*  GT-64120  */
#define PCI_PRODUCT_GALILEO_GT64260  0x6430    /*  GT-64260  */


struct gt_data {
        int             timer0_irqnr;
        int             pci_irqbase;
        int             type;

        uint32_t        pci0_iold;      /*  I/O Low Decode address  */
        uint32_t        pci0_iohd;      /*  I/O High Decode address  */

        struct pci_data *pci_data;
};


DEVICE_TICK(gt)
{
        struct gt_data *gt_data = extra;

        /*  TODO: Implement real timer interrupts.  */

        cpu_interrupt(cpu, gt_data->timer0_irqnr);
}


DEVICE_ACCESS(gt)
{
        uint64_t idata = 0, odata = 0;
        int bus, dev, func, reg;
        size_t i;
        struct gt_data *d = extra;

        if (writeflag == MEM_WRITE)
                idata = memory_readmax64(cpu, data, len);

        switch (relative_addr) {

        case GT_PCI0IOLD_OFS:
                if (writeflag == MEM_READ) {
                        odata = d->pci0_iold;
                } else {
                        fatal("[ gt: write to GT_PCI0IOLD_OFS: 0x%x (TODO) ]\n",
                            (int)idata);
                }
                break;

        case GT_PCI0IOHD_OFS:
                if (writeflag == MEM_READ) {
                        odata = d->pci0_iohd;
                } else {
                        fatal("[ gt: write to GT_PCI0IOHD_OFS: 0x%x (TODO) ]\n",
                            (int)idata);
                }
                break;

        case GT_PCI0IOREMAP_OFS:
                /*  TODO: Same as GT_PCI0IOLD_OFS?  */
                if (writeflag == MEM_READ) {
                        odata = d->pci0_iold;
                } else {
                        debug("[ gt: write to GT_PCI0IOREMAP_OFS: 0x%x "
                            "(TODO) ]\n", (int)idata);
                }
                break;

        case GT_INTR_CAUSE:
                if (writeflag == MEM_WRITE) {
                        debug("[ gt: write to GT_INTR_CAUSE: 0x%08x ]\n",
                            (int)idata);
                        return 1;
                } else {
                        odata = GTIC_T0EXP;
                        cpu_interrupt_ack(cpu, d->timer0_irqnr);

                        debug("[ gt: read from GT_INTR_CAUSE (0x%08x) ]\n",
                            (int)odata);
                }
                break;

        case GT_PCI0_INTR_ACK:
                odata = cpu->machine->isa_pic_data.last_int;
                cpu_interrupt_ack(cpu, d->pci_irqbase + odata);
                break;

        case GT_PCI0_CFG_ADDR:
                if (cpu->byte_order != EMUL_LITTLE_ENDIAN) {
                        fatal("[ gt: TODO: big endian PCI access ]\n");
                        exit(1);
                }
                bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
                bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
                break;

        case GT_PCI0_CFG_DATA:
                if (cpu->byte_order != EMUL_LITTLE_ENDIAN) {
                        fatal("[ gt: TODO: big endian PCI access ]\n");
                        exit(1);
                }
                bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
                    &odata : &idata, len, writeflag);
                break;

        default:
                if (writeflag == MEM_READ) {
                        debug("[ gt: read from addr 0x%x ]\n",
                            (int)relative_addr);
                } else {
                        debug("[ gt: write to addr 0x%x:", (int)relative_addr);
                        for (i=0; i<len; i++)
                                debug(" %02x", data[i]);
                        debug(" ]\n");
                }
        }

        if (writeflag == MEM_READ)
                memory_writemax64(cpu, data, len, odata);

        return 1;
}


/*
 *  dev_gt_init():
 *
 *  Initialize a GT device.  Return a pointer to the pci_data used, so that
 *  the caller may add PCI devices.  First, however, we add the GT device
 *  itself.
 */
struct pci_data *dev_gt_init(struct machine *machine, struct memory *mem,
        uint64_t baseaddr, int irq_nr, int pciirq, int type)
{
        struct gt_data *d;
        uint64_t pci_portbase = 0, pci_membase = 0;
        uint64_t isa_portbase = 0, isa_membase = 0;
        int isa_irqbase = 0, pci_irqbase = 0;
        uint64_t pci_io_offset = 0, pci_mem_offset = 0;
        char *gt_name = "NO";

        d = malloc(sizeof(struct gt_data));
        if (d == NULL) {
                fprintf(stderr, "out of memory\n");
                exit(1);
        }
        memset(d, 0, sizeof(struct gt_data));
        d->timer0_irqnr = irq_nr;

        switch (type) {
        case 11:
                /*  Cobalt:  */
                d->type = PCI_PRODUCT_GALILEO_GT64011;
                gt_name = "gt64011";
                pci_io_offset = 0;
                pci_mem_offset = 0;
                pci_portbase = 0x10000000ULL;
                pci_membase = 0x10100000ULL;
                pci_irqbase = 8;
                isa_portbase = 0x10000000ULL;
                isa_membase = 0x10100000ULL;
                isa_irqbase = 8;
                break;
        case 120:
                /*  EVBMIPS (Malta):  */
                d->type = PCI_PRODUCT_GALILEO_GT64120;
                gt_name = "gt64120";
                pci_io_offset = 0;
                pci_mem_offset = 0;
                pci_portbase = 0x18000000ULL;
                pci_membase = 0x10000000ULL;
                pci_irqbase = 8;
                isa_portbase = 0x18000000ULL;
                isa_membase = 0x10000000ULL;
                isa_irqbase = 8;
                break;
        case 260:
                /*  MVMEPPC (mvme5500):  */
                d->type = PCI_PRODUCT_GALILEO_GT64260;
                gt_name = "gt64260";
                pci_io_offset = 0;
                pci_mem_offset = 0;
                pci_portbase = 0x18000000ULL;
                pci_membase = 0x10000000ULL;
                pci_irqbase = 8;
                isa_portbase = 0x18000000ULL;
                isa_membase = 0x10000000ULL;
                isa_irqbase = 8;
                break;
        default:fatal("dev_gt_init(): unimplemented GT type (%i).\n", type);
                exit(1);
        }

        d->pci_irqbase = pci_irqbase;
        d->pci0_iold = pci_portbase >> 21;
        d->pci0_iohd = 0x0000000f;      /*  TODO?  */

        d->pci_data = bus_pci_init(machine,
            pciirq, pci_io_offset, pci_mem_offset,
            pci_portbase, pci_membase, pci_irqbase,
            isa_portbase, isa_membase, isa_irqbase);

        /*
         *  According to NetBSD/cobalt:
         *  pchb0 at pci0 dev 0 function 0: Galileo GT-64011
         *  System Controller, rev 1
         */
        bus_pci_add(machine, d->pci_data, mem, 0, 0, 0, gt_name);

        memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH,
            dev_gt_access, d, DM_DEFAULT, NULL);
        machine_add_tickfunction(machine, dev_gt_tick, d, TICK_SHIFT, 0.0);

        return d->pci_data;
}

1	dpavlin	4	/*
2	dpavlin	22	* Copyright (C) 2003-2006 Anders Gavare. All rights reserved.
3	dpavlin	4	*
4			* Redistribution and use in source and binary forms, with or without
5			* modification, are permitted provided that the following conditions are met:
6			*
7			* 1. Redistributions of source code must retain the above copyright
8			* notice, this list of conditions and the following disclaimer.
9			* 2. Redistributions in binary form must reproduce the above copyright
10			* notice, this list of conditions and the following disclaimer in the
11			* documentation and/or other materials provided with the distribution.
12			* 3. The name of the author may not be used to endorse or promote products
13			* derived from this software without specific prior written permission.
14			*
15			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25			* SUCH DAMAGE.
26			*
27			*
28	dpavlin	28	* $Id: dev_gt.c,v 1.42 2006/07/21 16:55:41 debug Exp $
29	dpavlin	4	*
30	dpavlin	10	* Galileo Technology GT-64xxx PCI controller.
31	dpavlin	4	*
32	dpavlin	10	* GT-64011 Used in Cobalt machines.
33			* GT-64120 Used in evbmips machines (Malta).
34	dpavlin	22	* GT-64260 Used in mvmeppc machines.
35	dpavlin	10	*
36	dpavlin	12	* TODO: This more or less just a dummy device, so far. It happens to work
37	dpavlin	22	* with some NetBSD ports in some cases, and perhaps with Linux too,
38			* but it is not really working for anything else.
39	dpavlin	4	*/
40
41			#include <stdio.h>
42			#include <stdlib.h>
43			#include <string.h>
44
45			#include "bus_pci.h"
46			#include "cpu.h"
47			#include "devices.h"
48			#include "machine.h"
49			#include "memory.h"
50			#include "misc.h"
51
52	dpavlin	28	#include "gtreg.h"
53	dpavlin	4
54	dpavlin	28
55	dpavlin	12	#define TICK_SHIFT 14
56	dpavlin	4
57	dpavlin	12	/* #define debug fatal */
58
59	dpavlin	20	#define PCI_PRODUCT_GALILEO_GT64011 0x4146 /* GT-64011 */
60			#define PCI_PRODUCT_GALILEO_GT64120 0x4620 /* GT-64120 */
61	dpavlin	22	#define PCI_PRODUCT_GALILEO_GT64260 0x6430 /* GT-64260 */
62	dpavlin	4
63	dpavlin	28
64	dpavlin	4	struct gt_data {
65	dpavlin	28	int timer0_irqnr;
66			int pci_irqbase;
67			int type;
68	dpavlin	4
69	dpavlin	28	uint32_t pci0_iold; /* I/O Low Decode address */
70			uint32_t pci0_iohd; /* I/O High Decode address */
71
72			struct pci_data *pci_data;
73	dpavlin	4	};
74
75
76	dpavlin	28	DEVICE_TICK(gt)
77	dpavlin	4	{
78			struct gt_data *gt_data = extra;
79
80	dpavlin	28	/* TODO: Implement real timer interrupts. */
81
82			cpu_interrupt(cpu, gt_data->timer0_irqnr);
83	dpavlin	4	}
84
85
86	dpavlin	22	DEVICE_ACCESS(gt)
87	dpavlin	4	{
88			uint64_t idata = 0, odata = 0;
89	dpavlin	22	int bus, dev, func, reg;
90			size_t i;
91	dpavlin	4	struct gt_data *d = extra;
92
93	dpavlin	18	if (writeflag == MEM_WRITE)
94			idata = memory_readmax64(cpu, data, len);
95	dpavlin	4
96			switch (relative_addr) {
97	dpavlin	12
98	dpavlin	28	case GT_PCI0IOLD_OFS:
99			if (writeflag == MEM_READ) {
100			odata = d->pci0_iold;
101			} else {
102			fatal("[ gt: write to GT_PCI0IOLD_OFS: 0x%x (TODO) ]\n",
103			(int)idata);
104	dpavlin	12	}
105			break;
106
107	dpavlin	28	case GT_PCI0IOHD_OFS:
108			if (writeflag == MEM_READ) {
109			odata = d->pci0_iohd;
110			} else {
111			fatal("[ gt: write to GT_PCI0IOHD_OFS: 0x%x (TODO) ]\n",
112			(int)idata);
113			}
114			break;
115
116			case GT_PCI0IOREMAP_OFS:
117			/* TODO: Same as GT_PCI0IOLD_OFS? */
118			if (writeflag == MEM_READ) {
119			odata = d->pci0_iold;
120			} else {
121			debug("[ gt: write to GT_PCI0IOREMAP_OFS: 0x%x "
122			"(TODO) ]\n", (int)idata);
123			}
124			break;
125
126			case GT_INTR_CAUSE:
127	dpavlin	4	if (writeflag == MEM_WRITE) {
128	dpavlin	28	debug("[ gt: write to GT_INTR_CAUSE: 0x%08x ]\n",
129			(int)idata);
130	dpavlin	4	return 1;
131			} else {
132	dpavlin	28	odata = GTIC_T0EXP;
133			cpu_interrupt_ack(cpu, d->timer0_irqnr);
134	dpavlin	4
135	dpavlin	28	debug("[ gt: read from GT_INTR_CAUSE (0x%08x) ]\n",
136			(int)odata);
137	dpavlin	4	}
138			break;
139	dpavlin	12
140	dpavlin	28	case GT_PCI0_INTR_ACK:
141	dpavlin	20	odata = cpu->machine->isa_pic_data.last_int;
142	dpavlin	28	cpu_interrupt_ack(cpu, d->pci_irqbase + odata);
143	dpavlin	12	break;
144
145	dpavlin	28	case GT_PCI0_CFG_ADDR:
146	dpavlin	22	if (cpu->byte_order != EMUL_LITTLE_ENDIAN) {
147			fatal("[ gt: TODO: big endian PCI access ]\n");
148			exit(1);
149			}
150			bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
151			bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
152			break;
153
154	dpavlin	28	case GT_PCI0_CFG_DATA:
155	dpavlin	22	if (cpu->byte_order != EMUL_LITTLE_ENDIAN) {
156			fatal("[ gt: TODO: big endian PCI access ]\n");
157			exit(1);
158	dpavlin	4	}
159	dpavlin	22	bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
160			&odata : &idata, len, writeflag);
161	dpavlin	4	break;
162	dpavlin	22
163	dpavlin	4	default:
164	dpavlin	20	if (writeflag == MEM_READ) {
165	dpavlin	12	debug("[ gt: read from addr 0x%x ]\n",
166	dpavlin	4	(int)relative_addr);
167			} else {
168	dpavlin	12	debug("[ gt: write to addr 0x%x:", (int)relative_addr);
169	dpavlin	4	for (i=0; i<len; i++)
170			debug(" %02x", data[i]);
171			debug(" ]\n");
172			}
173			}
174
175			if (writeflag == MEM_READ)
176			memory_writemax64(cpu, data, len, odata);
177
178			return 1;
179			}
180
181
182			/*
183			* dev_gt_init():
184			*
185			* Initialize a GT device. Return a pointer to the pci_data used, so that
186			* the caller may add PCI devices. First, however, we add the GT device
187			* itself.
188			*/
189			struct pci_data dev_gt_init(struct machine machine, struct memory *mem,
190	dpavlin	10	uint64_t baseaddr, int irq_nr, int pciirq, int type)
191	dpavlin	4	{
192			struct gt_data *d;
193	dpavlin	20	uint64_t pci_portbase = 0, pci_membase = 0;
194			uint64_t isa_portbase = 0, isa_membase = 0;
195			int isa_irqbase = 0, pci_irqbase = 0;
196			uint64_t pci_io_offset = 0, pci_mem_offset = 0;
197	dpavlin	22	char *gt_name = "NO";
198	dpavlin	4
199			d = malloc(sizeof(struct gt_data));
200			if (d == NULL) {
201			fprintf(stderr, "out of memory\n");
202			exit(1);
203			}
204			memset(d, 0, sizeof(struct gt_data));
205	dpavlin	28	d->timer0_irqnr = irq_nr;
206	dpavlin	4
207	dpavlin	10	switch (type) {
208			case 11:
209	dpavlin	20	/* Cobalt: */
210	dpavlin	10	d->type = PCI_PRODUCT_GALILEO_GT64011;
211	dpavlin	22	gt_name = "gt64011";
212	dpavlin	20	pci_io_offset = 0;
213			pci_mem_offset = 0;
214			pci_portbase = 0x10000000ULL;
215			pci_membase = 0x10100000ULL;
216	dpavlin	28	pci_irqbase = 8;
217	dpavlin	20	isa_portbase = 0x10000000ULL;
218			isa_membase = 0x10100000ULL;
219			isa_irqbase = 8;
220	dpavlin	10	break;
221			case 120:
222	dpavlin	20	/* EVBMIPS (Malta): */
223	dpavlin	10	d->type = PCI_PRODUCT_GALILEO_GT64120;
224	dpavlin	22	gt_name = "gt64120";
225	dpavlin	20	pci_io_offset = 0;
226			pci_mem_offset = 0;
227			pci_portbase = 0x18000000ULL;
228			pci_membase = 0x10000000ULL;
229			pci_irqbase = 8;
230			isa_portbase = 0x18000000ULL;
231			isa_membase = 0x10000000ULL;
232			isa_irqbase = 8;
233	dpavlin	10	break;
234	dpavlin	22	case 260:
235			/* MVMEPPC (mvme5500): */
236			d->type = PCI_PRODUCT_GALILEO_GT64260;
237			gt_name = "gt64260";
238			pci_io_offset = 0;
239			pci_mem_offset = 0;
240			pci_portbase = 0x18000000ULL;
241			pci_membase = 0x10000000ULL;
242			pci_irqbase = 8;
243			isa_portbase = 0x18000000ULL;
244			isa_membase = 0x10000000ULL;
245			isa_irqbase = 8;
246			break;
247			default:fatal("dev_gt_init(): unimplemented GT type (%i).\n", type);
248	dpavlin	10	exit(1);
249			}
250
251	dpavlin	28	d->pci_irqbase = pci_irqbase;
252			d->pci0_iold = pci_portbase >> 21;
253			d->pci0_iohd = 0x0000000f; /* TODO? */
254
255	dpavlin	22	d->pci_data = bus_pci_init(machine,
256	dpavlin	20	pciirq, pci_io_offset, pci_mem_offset,
257			pci_portbase, pci_membase, pci_irqbase,
258			isa_portbase, isa_membase, isa_irqbase);
259
260	dpavlin	4	/*
261			* According to NetBSD/cobalt:
262			* pchb0 at pci0 dev 0 function 0: Galileo GT-64011
263			* System Controller, rev 1
264			*/
265	dpavlin	22	bus_pci_add(machine, d->pci_data, mem, 0, 0, 0, gt_name);
266	dpavlin	4
267			memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH,
268	dpavlin	20	dev_gt_access, d, DM_DEFAULT, NULL);
269	dpavlin	24	machine_add_tickfunction(machine, dev_gt_tick, d, TICK_SHIFT, 0.0);
270	dpavlin	4
271			return d->pci_data;
272			}
273