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/* |
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* Copyright (C) 2004-2006 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_ahc.c,v 1.5 2006/07/21 16:55:41 debug Exp $ |
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* |
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* Adaptec AHC SCSI controller. |
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* |
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* NetBSD should say something like this, on SGI-IP32: |
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* ahc0 at pci0 dev 1 function 0 |
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* ahc0: interrupting at crime irq 0 |
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* ahc0: aic7880 Wide Channel A, SCSI Id=7, 16/255 SCBs |
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* ahc0: Host Adapter Bios disabled. Using default SCSI device parameters |
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* |
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* TODO: This more or less just a dummy device, so far. |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "cpu.h" |
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#include "device.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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|
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#include "aic7xxx_reg.h" |
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|
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|
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/* #define AHC_DEBUG |
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#define debug fatal */ |
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|
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|
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#define DEV_AHC_LENGTH 0x100 |
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|
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struct ahc_data { |
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unsigned char reg[DEV_AHC_LENGTH]; |
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}; |
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|
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|
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DEVICE_ACCESS(ahc) |
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{ |
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struct ahc_data *d = extra; |
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uint64_t idata, odata = 0; |
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int ok = 0; |
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char *name = NULL; |
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|
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idata = memory_readmax64(cpu, data, len); |
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|
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/* YUCK! SGI uses reversed order inside 32-bit words: */ |
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if (cpu->byte_order == EMUL_BIG_ENDIAN) |
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relative_addr = (relative_addr & ~0x3) |
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| (3 - (relative_addr & 3)); |
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|
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relative_addr %= DEV_AHC_LENGTH; |
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|
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if (len != 1) |
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fatal("[ ahc: ERROR! Unimplemented len %i ]\n", len); |
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|
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if (writeflag == MEM_READ) |
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odata = d->reg[relative_addr]; |
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|
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switch (relative_addr) { |
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|
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case SCSIID: |
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if (writeflag == MEM_READ) { |
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ok = 1; name = "SCSIID"; |
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odata = 0; |
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} else { |
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fatal("[ ahc: write to SCSIOFFSET, data = 0x" |
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"%02x: TODO ]\n", (int)idata); |
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} |
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break; |
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|
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case KERNEL_QINPOS: |
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if (writeflag == MEM_WRITE) { |
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|
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/* TODO */ |
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|
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d->reg[INTSTAT] |= SEQINT; |
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} |
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break; |
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|
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case SEECTL: |
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ok = 1; name = "SEECTL"; |
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if (writeflag == MEM_WRITE) |
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d->reg[relative_addr] = idata; |
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odata |= SEERDY; |
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break; |
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|
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case SCSICONF: |
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ok = 1; name = "SCSICONF"; |
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if (writeflag == MEM_READ) { |
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odata = 0; |
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} else { |
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fatal("[ ahc: write to SCSICONF, data = 0x%02x:" |
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" TODO ]\n", (int)idata); |
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} |
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break; |
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|
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case SEQRAM: |
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case SEQADDR0: |
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case SEQADDR1: |
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/* TODO: This is just a dummy. */ |
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break; |
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|
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case HCNTRL: |
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ok = 1; name = "HCNTRL"; |
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if (writeflag == MEM_WRITE) |
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d->reg[relative_addr] = idata; |
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break; |
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|
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case INTSTAT: |
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ok = 1; name = "INTSTAT"; |
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if (writeflag == MEM_WRITE) |
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fatal("[ ahc: write to INTSTAT? data = 0x%02x ]\n", |
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(int)idata); |
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break; |
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|
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case CLRINT: |
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if (writeflag == MEM_READ) { |
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ok = 1; name = "ERROR"; |
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/* TODO */ |
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} else { |
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ok = 1; name = "CLRINT"; |
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if (idata & ~0xf) |
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fatal("[ ahc: write to CLRINT: 0x%02x " |
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"(TODO) ]\n", (int)idata); |
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/* Clear the lowest 4 bits of intstat: */ |
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d->reg[INTSTAT] &= ~(idata & 0xf); |
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} |
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break; |
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|
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default: |
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if (writeflag == MEM_WRITE) |
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fatal("[ ahc: UNIMPLEMENTED write to address 0x%x, " |
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"data=0x%02x ]\n", (int)relative_addr, (int)idata); |
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else |
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fatal("[ ahc: UNIMPLEMENTED read from address 0x%x ]\n", |
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(int)relative_addr); |
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} |
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|
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#if 0 |
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cpu_interrupt(cpu, 0x200); |
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#endif |
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|
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#ifdef AHC_DEBUG |
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if (ok) { |
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if (name == NULL) { |
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if (writeflag == MEM_WRITE) |
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debug("[ ahc: write to address 0x%x: 0x" |
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"%02x ]\n", (int)relative_addr, (int)idata); |
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else |
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debug("[ ahc: read from address 0x%x: 0x" |
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"%02x ]\n", (int)relative_addr, (int)odata); |
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} else { |
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if (writeflag == MEM_WRITE) |
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debug("[ ahc: write to %s: 0x%02x ]\n", |
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name, (int)idata); |
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else |
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debug("[ ahc: read from %s: 0x%02x ]\n", |
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name, (int)odata); |
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} |
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} |
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#endif |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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DEVINIT(ahc) |
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{ |
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struct ahc_data *d = malloc(sizeof(struct ahc_data)); |
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if (d == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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memset(d, 0, sizeof(struct ahc_data)); |
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|
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memory_device_register(devinit->machine->memory, devinit->name, |
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devinit->addr, DEV_AHC_LENGTH, dev_ahc_access, d, |
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DM_DEFAULT, NULL); |
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|
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return 1; |
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} |
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