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/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_x86_instr.c,v 1.13 2006/04/22 18:07:30 debug Exp $ |
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* |
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* x86/amd64 instructions. |
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* |
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* Individual functions should keep track of cpu->n_translated_instrs. |
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* (n_translated_instrs is automatically increased by 1 for each function |
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* call. If no instruction was executed, then it should be decreased. If, say, |
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* 4 instructions were combined into one function and executed, then it should |
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* be increased by 3.) |
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*/ |
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|
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|
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/* |
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* nop: Do nothing. |
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*/ |
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X(nop) |
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{ |
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} |
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|
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|
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/*****************************************************************************/ |
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|
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|
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/* |
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* sti, cli, std, cld, stc, clc: Set/clear flag bits. |
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*/ |
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X(stc) { cpu->cd.x86.rflags |= X86_FLAGS_CF; } |
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X(clc) { cpu->cd.x86.rflags &= ~X86_FLAGS_CF; } |
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X(std) { cpu->cd.x86.rflags |= X86_FLAGS_DF; } |
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X(cld) { cpu->cd.x86.rflags &= ~X86_FLAGS_DF; } |
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X(sti) { cpu->cd.x86.rflags |= X86_FLAGS_IF; } |
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X(cli) { cpu->cd.x86.rflags &= ~X86_FLAGS_IF; } |
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|
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|
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/* |
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* cpuid |
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*/ |
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X(cpuid) |
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{ |
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x86_cpuid(cpu); |
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} |
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|
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|
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/* |
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* inc, dec |
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*/ |
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X(inc_ax) |
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{ |
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MODE_uint_t r = cpu->cd.x86.r[X86_R_AX], r2 = r + 1; |
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cpu->cd.x86.r[X86_R_AX] = (r & ~0xffff) + (r2 & 0xffff); |
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} |
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X(inc_cx) |
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{ |
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MODE_uint_t r = cpu->cd.x86.r[X86_R_CX], r2 = r + 1; |
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cpu->cd.x86.r[X86_R_CX] = (r & ~0xffff) + (r2 & 0xffff); |
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} |
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X(inc_dx) |
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{ |
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MODE_uint_t r = cpu->cd.x86.r[X86_R_DX], r2 = r + 1; |
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cpu->cd.x86.r[X86_R_DX] = (r & ~0xffff) + (r2 & 0xffff); |
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} |
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X(inc_bx) |
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{ |
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MODE_uint_t r = cpu->cd.x86.r[X86_R_BX], r2 = r + 1; |
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cpu->cd.x86.r[X86_R_BX] = (r & ~0xffff) + (r2 & 0xffff); |
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} |
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X(inc_sp) |
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{ |
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MODE_uint_t r = cpu->cd.x86.r[X86_R_SP], r2 = r + 1; |
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cpu->cd.x86.r[X86_R_SP] = (r & ~0xffff) + (r2 & 0xffff); |
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} |
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X(inc_bp) |
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{ |
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MODE_uint_t r = cpu->cd.x86.r[X86_R_BP], r2 = r + 1; |
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cpu->cd.x86.r[X86_R_BP] = (r & ~0xffff) + (r2 & 0xffff); |
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} |
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X(inc_si) |
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{ |
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MODE_uint_t r = cpu->cd.x86.r[X86_R_SI], r2 = r + 1; |
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cpu->cd.x86.r[X86_R_SI] = (r & ~0xffff) + (r2 & 0xffff); |
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} |
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X(inc_di) |
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{ |
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MODE_uint_t r = cpu->cd.x86.r[X86_R_DI], r2 = r + 1; |
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cpu->cd.x86.r[X86_R_DI] = (r & ~0xffff) + (r2 & 0xffff); |
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} |
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X(inc_eax) { cpu->cd.x86.r[X86_R_AX] ++; } |
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X(inc_ecx) { cpu->cd.x86.r[X86_R_CX] ++; } |
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X(inc_edx) { cpu->cd.x86.r[X86_R_DX] ++; } |
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X(inc_ebx) { cpu->cd.x86.r[X86_R_BX] ++; } |
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X(inc_esp) { cpu->cd.x86.r[X86_R_SP] ++; } |
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X(inc_ebp) { cpu->cd.x86.r[X86_R_BP] ++; } |
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X(inc_esi) { cpu->cd.x86.r[X86_R_SI] ++; } |
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X(inc_edi) { cpu->cd.x86.r[X86_R_DI] ++; } |
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|
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|
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/* |
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* mov_reg_imm_8: |
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* |
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* arg[1] = imm8 |
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* arg[2] = pointer to a _byte_ inside an emulated register |
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*/ |
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X(mov_reg_imm_8) |
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{ |
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*((uint8_t *)ic->arg[2]) = ic->arg[1]; |
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} |
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|
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|
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/* |
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* mov_reg_imm_16, _32 |
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*/ |
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X(mov_reg_imm_16) |
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{ |
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reg(ic->arg[2]) &= ~0xffff; |
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reg(ic->arg[2]) |= ic->arg[1]; |
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} |
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X(mov_reg_imm_32) |
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{ |
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reg(ic->arg[2]) = (uint32_t)ic->arg[1]; |
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} |
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|
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|
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/*****************************************************************************/ |
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|
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|
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X(end_of_page) |
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{ |
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/* Update the PC: (offset 0, but on the next page) */ |
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cpu->pc &= ~(X86_IC_ENTRIES_PER_PAGE-1); |
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cpu->pc += X86_IC_ENTRIES_PER_PAGE; |
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|
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/* Find the new physical page and update the translation pointers: */ |
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x86_pc_to_pointers(cpu); |
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|
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/* end_of_page doesn't count as an executed instruction: */ |
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cpu->n_translated_instrs --; |
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} |
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|
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|
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/*****************************************************************************/ |
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|
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|
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#ifdef GET_NEXT_BYTE |
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#undef GET_NEXT_BYTE |
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#endif |
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#ifdef MODE32 |
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#define GET_NEXT_BYTE get_next_byte32 |
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#else |
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#define GET_NEXT_BYTE get_next_byte64 |
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#endif |
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/* Get the next instruction byte; return 1 on success, 0 on failure */ |
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int GET_NEXT_BYTE(struct cpu *cpu, unsigned char *byte, MODE_uint_t addr) |
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{ |
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unsigned char *page; |
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|
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/* Read the instruction word from memory: */ |
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#ifdef MODE32 |
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page = cpu->cd.x86.host_load[addr >> 12]; |
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#else |
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{ |
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const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1; |
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const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1; |
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const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1; |
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uint32_t x1 = (addr >> (64-DYNTRANS_L1N)) & mask1; |
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uint32_t x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2; |
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uint32_t x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N- |
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DYNTRANS_L3N)) & mask3; |
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struct DYNTRANS_L2_64_TABLE *l2 = cpu->cd.x86.l1_64[x1]; |
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struct DYNTRANS_L3_64_TABLE *l3 = l2->l3[x2]; |
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page = l3->host_load[x3]; |
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} |
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#endif |
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|
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if (page != NULL) { |
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/* fatal("TRANSLATION HIT!\n"); */ |
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(*byte) = page[addr & 0xfff]; |
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} else { |
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/* fatal("TRANSLATION MISS!\n"); */ |
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if (!cpu->memory_rw(cpu, cpu->mem, addr, byte, |
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1, MEM_READ, CACHE_INSTRUCTION)) { |
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/* exception occurred, or similar */ |
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return 0; |
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} |
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} |
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|
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return 1; |
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} |
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|
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|
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#ifndef GNB |
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#define GNB { if (len >= sizeof(ib)) \ |
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goto bad; \ |
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if (!GET_NEXT_BYTE(cpu, &ib[len++], addr++)) \ |
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goto gnb_failed; \ |
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} |
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#endif |
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|
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|
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#ifndef GET_OP |
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#define GET_OP opimm = 0; \ |
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{ \ |
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int i; \ |
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for (i=0; i<oplen; i++) { \ |
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GNB; \ |
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opimm |= (ib[len-1] << (i*8)); \ |
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} \ |
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} |
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#endif |
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|
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|
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/* |
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* x86_instr_to_be_translated(): |
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* |
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* Translate an instruction word into an x86_instr_call. ic is filled in with |
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* valid data for the translated instruction, or a "nothing" instruction if |
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* there was a translation failure. The newly translated instruction is then |
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* executed. |
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*/ |
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X(to_be_translated) |
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{ |
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MODE_uint_t addr, orig_addr, low_pc; |
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int main_opcode, secondary_opcode, len, mode16, oplen; |
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uint32_t opimm; |
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unsigned char ib[17]; |
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/* void (*samepage_function)(struct cpu *, struct x86_instr_call *); */ |
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|
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/* Figure out the (virtual) address of the instruction: */ |
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low_pc = ((size_t)ic - (size_t)cpu->cd.x86.cur_ic_page) |
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/ sizeof(struct x86_instr_call); |
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addr = cpu->pc & ~(X86_IC_ENTRIES_PER_PAGE-1); |
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addr += low_pc; |
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cpu->pc = addr; |
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orig_addr = addr; |
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|
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if (!cpu->cd.x86.descr_cache[X86_S_CS].valid) { |
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fatal("x86_cpu_run_instr(): Invalid CS descriptor?\n"); |
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exit(1); |
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} |
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|
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cpu->cd.x86.cursegment = X86_S_CS; |
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cpu->cd.x86.seg_override = 0; |
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|
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|
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#define DYNTRANS_TO_BE_TRANSLATED_HEAD |
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#include "cpu_dyntrans.c" |
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#undef DYNTRANS_TO_BE_TRANSLATED_HEAD |
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|
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|
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/* |
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* Translate the instruction: |
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*/ |
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|
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ic->arg[0] = len = 0; |
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|
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if (LONG_MODE) { |
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fatal("LONG MODE: TODO\n"); |
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goto bad; |
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} |
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|
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mode16 = REAL_MODE; |
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|
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/* Parse prefix bytes, and get the main (first) opcode byte: */ |
| 290 |
for (;;) { |
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GNB; main_opcode = ib[len - 1]; |
| 292 |
if (main_opcode == 0x66) { |
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mode16 = !mode16; |
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} else { |
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/* Found a non-prefix byte? Then break. */ |
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break; |
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} |
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} |
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|
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oplen = mode16? sizeof(uint16_t) : sizeof(uint32_t); |
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|
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switch (main_opcode) { |
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|
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case 0x0f: |
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GNB; secondary_opcode = ib[len-1]; |
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switch (secondary_opcode) { |
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|
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case 0xa2: |
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ic->f = instr(cpuid); |
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break; |
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|
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default:fatal("unimplemented 0x0f opcode 0x%02x\n", |
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secondary_opcode); |
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goto bad; |
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} |
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break; |
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|
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case 0x40: /* inc ax etc. */ |
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case 0x41: |
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case 0x42: |
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case 0x43: |
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case 0x44: |
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case 0x45: |
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case 0x46: |
| 325 |
case 0x47: |
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if (mode16) { |
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switch (main_opcode) { |
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case 0x40: ic->f = instr(inc_ax); break; |
| 329 |
case 0x41: ic->f = instr(inc_cx); break; |
| 330 |
case 0x42: ic->f = instr(inc_dx); break; |
| 331 |
case 0x43: ic->f = instr(inc_bx); break; |
| 332 |
case 0x44: ic->f = instr(inc_sp); break; |
| 333 |
case 0x45: ic->f = instr(inc_bp); break; |
| 334 |
case 0x46: ic->f = instr(inc_si); break; |
| 335 |
case 0x47: ic->f = instr(inc_di); break; |
| 336 |
} |
| 337 |
} else { |
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switch (main_opcode) { |
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case 0x40: ic->f = instr(inc_eax); break; |
| 340 |
case 0x41: ic->f = instr(inc_ecx); break; |
| 341 |
case 0x42: ic->f = instr(inc_edx); break; |
| 342 |
case 0x43: ic->f = instr(inc_ebx); break; |
| 343 |
case 0x44: ic->f = instr(inc_esp); break; |
| 344 |
case 0x45: ic->f = instr(inc_ebp); break; |
| 345 |
case 0x46: ic->f = instr(inc_esi); break; |
| 346 |
case 0x47: ic->f = instr(inc_edi); break; |
| 347 |
} |
| 348 |
} |
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break; |
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|
| 351 |
case 0x90: /* nop */ |
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ic->f = instr(nop); |
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break; |
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|
| 355 |
case 0xb0: /* mov al,imm etc. */ |
| 356 |
case 0xb1: |
| 357 |
case 0xb2: |
| 358 |
case 0xb3: |
| 359 |
case 0xb4: |
| 360 |
case 0xb5: |
| 361 |
case 0xb6: |
| 362 |
case 0xb7: |
| 363 |
GNB; |
| 364 |
ic->arg[1] = ib[len - 1]; |
| 365 |
/* Calculate for little endian first: */ |
| 366 |
ic->arg[2] = (size_t)&cpu->cd.x86.r[main_opcode & 3]; |
| 367 |
if (main_opcode >= 0xb4) |
| 368 |
ic->arg[2] ++; |
| 369 |
#ifdef HOST_BIG_ENDIAN |
| 370 |
/* Switch byte order: */ |
| 371 |
ic->arg[2] = (ic->arg[2] & ~(sizeof(uint64_t)-1)) + |
| 372 |
sizeof(uint64_t) - 1 - (ic->arg[2] & (sizeof(uint64_t)-1)); |
| 373 |
#endif |
| 374 |
ic->f = instr(mov_reg_imm_8); |
| 375 |
break; |
| 376 |
|
| 377 |
case 0xb8: /* mov ax,imm etc. */ |
| 378 |
case 0xb9: |
| 379 |
case 0xba: |
| 380 |
case 0xbb: |
| 381 |
case 0xbc: |
| 382 |
case 0xbd: |
| 383 |
case 0xbe: |
| 384 |
case 0xbf: |
| 385 |
GET_OP; |
| 386 |
ic->arg[1] = opimm; |
| 387 |
ic->arg[2] = (size_t)&cpu->cd.x86.r[main_opcode - 0xb8]; |
| 388 |
if (mode16) |
| 389 |
ic->f = instr(mov_reg_imm_16); |
| 390 |
else |
| 391 |
ic->f = instr(mov_reg_imm_32); |
| 392 |
break; |
| 393 |
|
| 394 |
case 0xf8: /* clc */ |
| 395 |
case 0xf9: /* stc */ |
| 396 |
case 0xfa: /* cli */ |
| 397 |
case 0xfb: /* sti */ |
| 398 |
case 0xfc: /* cld */ |
| 399 |
case 0xfd: /* std */ |
| 400 |
switch (main_opcode) { |
| 401 |
case 0xf8: ic->f = instr(sti); break; |
| 402 |
case 0xf9: ic->f = instr(stc); break; |
| 403 |
case 0xfa: ic->f = instr(cli); break; |
| 404 |
case 0xfb: ic->f = instr(sti); break; |
| 405 |
case 0xfc: ic->f = instr(cld); break; |
| 406 |
case 0xfd: ic->f = instr(std); break; |
| 407 |
} |
| 408 |
break; |
| 409 |
|
| 410 |
default:goto bad; |
| 411 |
} |
| 412 |
|
| 413 |
|
| 414 |
if (((addr-1) & ~0xfff) != (orig_addr & ~0xfff)) { |
| 415 |
fatal("Instruction crosses page boundary. TODO\n"); |
| 416 |
exit(1); |
| 417 |
} |
| 418 |
|
| 419 |
if (len > sizeof(ib)) { |
| 420 |
fatal("INTERNAL ERROR in cpu_x86_instr.c! len = %i\n", len); |
| 421 |
exit(1); |
| 422 |
} |
| 423 |
|
| 424 |
ic->arg[0] = len; |
| 425 |
goto ok; |
| 426 |
|
| 427 |
|
| 428 |
/* We get here if get_next_byte failed (i.e. an excepion occured while |
| 429 |
crossing a page-boundary...) */ |
| 430 |
gnb_failed: |
| 431 |
ic->f = instr(to_be_translated); |
| 432 |
ic->arg[0] = 0; |
| 433 |
/* The program counter etc. should already have been updated. */ |
| 434 |
return; |
| 435 |
|
| 436 |
ok: |
| 437 |
|
| 438 |
#define DYNTRANS_TO_BE_TRANSLATED_TAIL |
| 439 |
#include "cpu_dyntrans.c" |
| 440 |
#undef DYNTRANS_TO_BE_TRANSLATED_TAIL |
| 441 |
} |
| 442 |
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