src/cpus/cpu_sparc_instr_loadstore.c

/*
 *  Copyright (C) 2006  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright
 *     notice, this list of conditions and the following disclaimer in the
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_sparc_instr_loadstore.c,v 1.2 2006/07/02 11:10:20 debug Exp $
 *
 *  SPARC load/store instructions; the following args are used:
 *  
 *  arg[0] = pointer to the register to load to or store from
 *  arg[1] = pointer to the base register
 *  arg[2] = if LS_USE_IMM is defined:  an int32_t immediate offset
 *           otherwise:                 pointer to the offset register
 */


void LS_GENERIC_N(struct cpu *cpu, struct sparc_instr_call *ic)
{
        MODE_int_t addr = reg(ic->arg[1]) +
#ifdef LS_USE_IMM
            (int32_t)ic->arg[2];
#else
            reg(ic->arg[2]);
#endif
        uint8_t data[LS_SIZE];
#ifdef LS_LOAD
        uint64_t x;
#endif

        /*  Synchronize the PC:  */
        int low_pc = ((size_t)ic - (size_t)cpu->cd.sparc.cur_ic_page)
            / sizeof(struct sparc_instr_call);
        cpu->pc &= ~((SPARC_IC_ENTRIES_PER_PAGE - 1)
            << SPARC_INSTR_ALIGNMENT_SHIFT);
        cpu->pc += (low_pc << SPARC_INSTR_ALIGNMENT_SHIFT);

#ifndef LS_1
        /*  Check alignment:  */
        if (addr & (LS_SIZE - 1)) {
                fatal("TODO: sparc dyntrans alignment exception, size = %i,"
                    " addr = %016"PRIx64", pc = %016"PRIx64"\n", LS_SIZE,
                    (uint64_t) addr, cpu->pc);

                /*  TODO: Generalize this into a abort_call, or similar:  */
                cpu->running = 0;
                cpu->dead = 1;
                debugger_n_steps_left_before_interaction = 0;
                cpu->running_translated = 0;
                cpu->cd.sparc.next_ic = &nothing_call;
                return;
        }
#endif

#ifdef LS_LOAD
        if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
            MEM_READ, CACHE_DATA)) {
                /*  Exception.  */
                return;
        }
        x = memory_readmax64(cpu, data, LS_SIZE);
#ifdef LS_SIGNED
#ifdef LS_1
        x = (int8_t)x;
#endif
#ifdef LS_2
        x = (int16_t)x;
#endif
#ifdef LS_4
        x = (int32_t)x;
#endif
#endif
        reg(ic->arg[0]) = x;
#else   /*  LS_STORE:  */
        memory_writemax64(cpu, data, LS_SIZE, reg(ic->arg[0]));
        if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
            MEM_WRITE, CACHE_DATA)) {
                /*  Exception.  */
                return;
        }
#endif
}


void LS_N(struct cpu *cpu, struct sparc_instr_call *ic)
{
        MODE_uint_t addr = reg(ic->arg[1]) +
#ifdef LS_USE_IMM
            (int32_t)ic->arg[2];
#else
            reg(ic->arg[2]);
#endif
        unsigned char *p;
#ifdef MODE32
#ifdef LS_LOAD
        p = cpu->cd.sparc.host_load[addr >> 12];
#else
        p = cpu->cd.sparc.host_store[addr >> 12];
#endif
#else   /*  !MODE32  */
        const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
        const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
        const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
        uint32_t x1, x2, x3;
        struct DYNTRANS_L2_64_TABLE *l2;
        struct DYNTRANS_L3_64_TABLE *l3;

        x1 = (addr >> (64-DYNTRANS_L1N)) & mask1;
        x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
        x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
        /*  fatal("X3: addr=%016"PRIx64" x1=%x x2=%x x3=%x\n",
            (uint64_t) addr, (int) x1, (int) x2, (int) x3);  */
        l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
        /*  fatal("  l2 = %p\n", l2);  */
        l3 = l2->l3[x2];
        /*  fatal("  l3 = %p\n", l3);  */
#ifdef LS_LOAD
        p = l3->host_load[x3];
#else
        p = l3->host_store[x3];
#endif
        /*  fatal("  p = %p\n", p);  */
#endif

        if (p == NULL
#ifndef LS_1
            || addr & (LS_SIZE - 1)
#endif
            ) {
                LS_GENERIC_N(cpu, ic);
                return;
        }

        addr &= 0xfff;

#ifdef LS_LOAD
        /*  Load:  */

#ifdef LS_1
        reg(ic->arg[0]) =
#ifdef LS_SIGNED
            (int8_t)
#endif
            p[addr];
#endif  /*  LS_1  */

#ifdef LS_2
        reg(ic->arg[0]) =
#ifdef LS_SIGNED
            (int16_t)
#endif
#ifdef HOST_BIG_ENDIAN
            ( *(uint16_t *)(p + addr) );
#else
            ((p[addr]<<8) + p[addr+1]);
#endif
#endif  /*  LS_2  */

#ifdef LS_4
        reg(ic->arg[0]) =
#ifdef LS_SIGNED
            (int32_t)
#else
            (uint32_t)
#endif
#ifdef HOST_BIG_ENDIAN
            ( *(uint32_t *)(p + addr) );
#else
            ((p[addr]<<24) + (p[addr+1]<<16) + (p[addr+2]<<8) + p[addr+3]);
#endif
#endif  /*  LS_4  */

#ifdef LS_8
        *((uint64_t *)ic->arg[0]) =
#ifdef HOST_BIG_ENDIAN
            ( *(uint64_t *)(p + addr) );
#else
            ((uint64_t)p[addr] << 56) + ((uint64_t)p[addr+1] << 48) +
            ((uint64_t)p[addr+2] << 40) + ((uint64_t)p[addr+3] << 32) +
            ((uint64_t)p[addr+4] << 24) +
            (p[addr+5] << 16) + (p[addr+6] << 8) + p[addr+7];
#endif
#endif  /*  LS_8  */

#else
        /*  Store: */

#ifdef LS_1
        p[addr] = reg(ic->arg[0]);
#endif
#ifdef LS_2
        { uint32_t x = reg(ic->arg[0]);
#ifdef HOST_BIG_ENDIAN
        *((uint16_t *)(p+addr)) = x; }
#else
        p[addr] = x >> 8; p[addr+1] = x; }
#endif
#endif  /*  LS_2  */
#ifdef LS_4
        { uint32_t x = reg(ic->arg[0]);
#ifdef HOST_BIG_ENDIAN
        *((uint32_t *)(p+addr)) = x; }
#else
        p[addr] = x >> 24; p[addr+1] = x >> 16; 
        p[addr+2] = x >> 8; p[addr+3] = x; }
#endif
#endif  /*  LS_4  */
#ifdef LS_8
        { uint64_t x = *(uint64_t *)(ic->arg[0]);
#ifdef HOST_BIG_ENDIAN
        *((uint64_t *)(p+addr)) = x; }
#else
        p[addr]   = x >> 56; p[addr+1] = x >> 48; p[addr+2] = x >> 40;
        p[addr+3] = x >> 32; p[addr+4] = x >> 24; p[addr+5] = x >> 16;
        p[addr+6] = x >> 8;  p[addr+7] = x; }
#endif
#endif  /*  LS_8  */

#endif  /*  store  */
}

1	/*
2	* Copyright (C) 2006 Anders Gavare. All rights reserved.
3	*
4	* Redistribution and use in source and binary forms, with or without
5	* modification, are permitted provided that the following conditions are met:
6	*
7	* 1. Redistributions of source code must retain the above copyright
8	* notice, this list of conditions and the following disclaimer.
9	* 2. Redistributions in binary form must reproduce the above copyright
10	* notice, this list of conditions and the following disclaimer in the
11	* documentation and/or other materials provided with the distribution.
12	* 3. The name of the author may not be used to endorse or promote products
13	* derived from this software without specific prior written permission.
14	*
15	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25	* SUCH DAMAGE.
26	*
27	*
28	* $Id: cpu_sparc_instr_loadstore.c,v 1.2 2006/07/02 11:10:20 debug Exp $
29	*
30	* SPARC load/store instructions; the following args are used:
31	*
32	* arg[0] = pointer to the register to load to or store from
33	* arg[1] = pointer to the base register
34	* arg[2] = if LS_USE_IMM is defined: an int32_t immediate offset
35	* otherwise: pointer to the offset register
36	*/
37
38
39	void LS_GENERIC_N(struct cpu cpu, struct sparc_instr_call ic)
40	{
41	MODE_int_t addr = reg(ic->arg[1]) +
42	#ifdef LS_USE_IMM
43	(int32_t)ic->arg[2];
44	#else
45	reg(ic->arg[2]);
46	#endif
47	uint8_t data[LS_SIZE];
48	#ifdef LS_LOAD
49	uint64_t x;
50	#endif
51
52	/* Synchronize the PC: */
53	int low_pc = ((size_t)ic - (size_t)cpu->cd.sparc.cur_ic_page)
54	/ sizeof(struct sparc_instr_call);
55	cpu->pc &= ~((SPARC_IC_ENTRIES_PER_PAGE - 1)
56	<< SPARC_INSTR_ALIGNMENT_SHIFT);
57	cpu->pc += (low_pc << SPARC_INSTR_ALIGNMENT_SHIFT);
58
59	#ifndef LS_1
60	/* Check alignment: */
61	if (addr & (LS_SIZE - 1)) {
62	fatal("TODO: sparc dyntrans alignment exception, size = %i,"
63	" addr = %016"PRIx64", pc = %016"PRIx64"\n", LS_SIZE,
64	(uint64_t) addr, cpu->pc);
65
66	/* TODO: Generalize this into a abort_call, or similar: */
67	cpu->running = 0;
68	cpu->dead = 1;
69	debugger_n_steps_left_before_interaction = 0;
70	cpu->running_translated = 0;
71	cpu->cd.sparc.next_ic = &nothing_call;
72	return;
73	}
74	#endif
75
76	#ifdef LS_LOAD
77	if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
78	MEM_READ, CACHE_DATA)) {
79	/* Exception. */
80	return;
81	}
82	x = memory_readmax64(cpu, data, LS_SIZE);
83	#ifdef LS_SIGNED
84	#ifdef LS_1
85	x = (int8_t)x;
86	#endif
87	#ifdef LS_2
88	x = (int16_t)x;
89	#endif
90	#ifdef LS_4
91	x = (int32_t)x;
92	#endif
93	#endif
94	reg(ic->arg[0]) = x;
95	#else /* LS_STORE: */
96	memory_writemax64(cpu, data, LS_SIZE, reg(ic->arg[0]));
97	if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
98	MEM_WRITE, CACHE_DATA)) {
99	/* Exception. */
100	return;
101	}
102	#endif
103	}
104
105
106	void LS_N(struct cpu cpu, struct sparc_instr_call ic)
107	{
108	MODE_uint_t addr = reg(ic->arg[1]) +
109	#ifdef LS_USE_IMM
110	(int32_t)ic->arg[2];
111	#else
112	reg(ic->arg[2]);
113	#endif
114	unsigned char *p;
115	#ifdef MODE32
116	#ifdef LS_LOAD
117	p = cpu->cd.sparc.host_load[addr >> 12];
118	#else
119	p = cpu->cd.sparc.host_store[addr >> 12];
120	#endif
121	#else /* !MODE32 */
122	const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
123	const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
124	const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
125	uint32_t x1, x2, x3;
126	struct DYNTRANS_L2_64_TABLE *l2;
127	struct DYNTRANS_L3_64_TABLE *l3;
128
129	x1 = (addr >> (64-DYNTRANS_L1N)) & mask1;
130	x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
131	x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
132	/* fatal("X3: addr=%016"PRIx64" x1=%x x2=%x x3=%x\n",
133	(uint64_t) addr, (int) x1, (int) x2, (int) x3); */
134	l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
135	/* fatal(" l2 = %p\n", l2); */
136	l3 = l2->l3[x2];
137	/* fatal(" l3 = %p\n", l3); */
138	#ifdef LS_LOAD
139	p = l3->host_load[x3];
140	#else
141	p = l3->host_store[x3];
142	#endif
143	/* fatal(" p = %p\n", p); */
144	#endif
145
146	if (p == NULL
147	#ifndef LS_1
148	\|\| addr & (LS_SIZE - 1)
149	#endif
150	) {
151	LS_GENERIC_N(cpu, ic);
152	return;
153	}
154
155	addr &= 0xfff;
156
157	#ifdef LS_LOAD
158	/* Load: */
159
160	#ifdef LS_1
161	reg(ic->arg[0]) =
162	#ifdef LS_SIGNED
163	(int8_t)
164	#endif
165	p[addr];
166	#endif /* LS_1 */
167
168	#ifdef LS_2
169	reg(ic->arg[0]) =
170	#ifdef LS_SIGNED
171	(int16_t)
172	#endif
173	#ifdef HOST_BIG_ENDIAN
174	( (uint16_t )(p + addr) );
175	#else
176	((p[addr]<<8) + p[addr+1]);
177	#endif
178	#endif /* LS_2 */
179
180	#ifdef LS_4
181	reg(ic->arg[0]) =
182	#ifdef LS_SIGNED
183	(int32_t)
184	#else
185	(uint32_t)
186	#endif
187	#ifdef HOST_BIG_ENDIAN
188	( (uint32_t )(p + addr) );
189	#else
190	((p[addr]<<24) + (p[addr+1]<<16) + (p[addr+2]<<8) + p[addr+3]);
191	#endif
192	#endif /* LS_4 */
193
194	#ifdef LS_8
195	((uint64_t )ic->arg[0]) =
196	#ifdef HOST_BIG_ENDIAN
197	( (uint64_t )(p + addr) );
198	#else
199	((uint64_t)p[addr] << 56) + ((uint64_t)p[addr+1] << 48) +
200	((uint64_t)p[addr+2] << 40) + ((uint64_t)p[addr+3] << 32) +
201	((uint64_t)p[addr+4] << 24) +
202	(p[addr+5] << 16) + (p[addr+6] << 8) + p[addr+7];
203	#endif
204	#endif /* LS_8 */
205
206	#else
207	/* Store: */
208
209	#ifdef LS_1
210	p[addr] = reg(ic->arg[0]);
211	#endif
212	#ifdef LS_2
213	{ uint32_t x = reg(ic->arg[0]);
214	#ifdef HOST_BIG_ENDIAN
215	((uint16_t )(p+addr)) = x; }
216	#else
217	p[addr] = x >> 8; p[addr+1] = x; }
218	#endif
219	#endif /* LS_2 */
220	#ifdef LS_4
221	{ uint32_t x = reg(ic->arg[0]);
222	#ifdef HOST_BIG_ENDIAN
223	((uint32_t )(p+addr)) = x; }
224	#else
225	p[addr] = x >> 24; p[addr+1] = x >> 16;
226	p[addr+2] = x >> 8; p[addr+3] = x; }
227	#endif
228	#endif /* LS_4 */
229	#ifdef LS_8
230	{ uint64_t x = (uint64_t )(ic->arg[0]);
231	#ifdef HOST_BIG_ENDIAN
232	((uint64_t )(p+addr)) = x; }
233	#else
234	p[addr] = x >> 56; p[addr+1] = x >> 48; p[addr+2] = x >> 40;
235	p[addr+3] = x >> 32; p[addr+4] = x >> 24; p[addr+5] = x >> 16;
236	p[addr+6] = x >> 8; p[addr+7] = x; }
237	#endif
238	#endif /* LS_8 */
239
240	#endif /* store */
241	}
242