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/* |
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* Copyright (C) 2006 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_mips_instr_loadstore.c,v 1.11 2006/05/20 08:03:30 debug Exp $ |
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* |
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* MIPS load/store instructions; the following args are used: |
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* |
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* arg[0] = pointer to the register to load to or store from |
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* arg[1] = pointer to the base register |
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* arg[2] = offset (as an int32_t) |
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* |
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* The GENERIC function always checks for alignment, and supports both big |
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* and little endian byte order. |
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* |
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* The quick function is included twice (big/little endian) for each |
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* GENERIC function. |
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*/ |
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|
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|
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#ifdef LS_INCLUDE_GENERIC |
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void LS_GENERIC_N(struct cpu *cpu, struct mips_instr_call *ic) |
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{ |
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MODE_int_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2]; |
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uint8_t data[LS_SIZE]; |
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#ifdef LS_LOAD |
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uint64_t x; |
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#endif |
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|
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/* Synchronize the PC: */ |
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int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page) |
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/ sizeof(struct mips_instr_call); |
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cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT); |
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cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT); |
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|
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#ifndef LS_1 |
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/* Check alignment: */ |
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if (addr & (LS_SIZE - 1)) { |
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fatal("TODO: mips dyntrans alignment exception, size = %i," |
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" addr = %016"PRIx64", pc = %016"PRIx64"\n", LS_SIZE, |
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(uint64_t) addr, cpu->pc); |
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|
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/* TODO: Generalize this into a abort_call, or similar: */ |
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cpu->running = 0; |
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cpu->dead = 1; |
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debugger_n_steps_left_before_interaction = 0; |
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cpu->running_translated = 0; |
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cpu->cd.mips.next_ic = ¬hing_call; |
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return; |
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} |
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#endif |
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|
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#ifdef LS_LOAD |
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if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data), |
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MEM_READ, CACHE_DATA)) { |
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/* Exception. */ |
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return; |
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} |
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x = memory_readmax64(cpu, data, LS_SIZE); |
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#ifdef LS_SIGNED |
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#ifdef LS_1 |
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x = (int8_t)x; |
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#endif |
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#ifdef LS_2 |
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x = (int16_t)x; |
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#endif |
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#ifdef LS_4 |
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x = (int32_t)x; |
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#endif |
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#endif |
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reg(ic->arg[0]) = x; |
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#else /* LS_STORE: */ |
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memory_writemax64(cpu, data, LS_SIZE, reg(ic->arg[0])); |
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if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data), |
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MEM_WRITE, CACHE_DATA)) { |
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/* Exception. */ |
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return; |
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} |
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#endif |
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} |
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#endif /* LS_INCLUDE_GENERIC */ |
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|
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|
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void LS_N(struct cpu *cpu, struct mips_instr_call *ic) |
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{ |
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MODE_uint_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2]; |
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unsigned char *p; |
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#ifdef MODE32 |
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#ifdef LS_LOAD |
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p = cpu->cd.mips.host_load[addr >> 12]; |
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#else |
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p = cpu->cd.mips.host_store[addr >> 12]; |
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#endif |
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#else /* !MODE32 */ |
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const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1; |
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const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1; |
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const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1; |
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uint32_t x1, x2, x3; |
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struct DYNTRANS_L2_64_TABLE *l2; |
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struct DYNTRANS_L3_64_TABLE *l3; |
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|
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x1 = (addr >> (64-DYNTRANS_L1N)) & mask1; |
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x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2; |
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x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3; |
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/* fatal("X3: addr=%016"PRIx64" x1=%x x2=%x x3=%x\n", |
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(uint64_t) addr, (int) x1, (int) x2, (int) x3); */ |
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l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1]; |
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/* fatal(" l2 = %p\n", l2); */ |
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l3 = l2->l3[x2]; |
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/* fatal(" l3 = %p\n", l3); */ |
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#ifdef LS_LOAD |
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p = l3->host_load[x3]; |
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#else |
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p = l3->host_store[x3]; |
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#endif |
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/* fatal(" p = %p\n", p); */ |
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#endif |
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|
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if (p == NULL |
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#ifndef LS_1 |
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|| addr & (LS_SIZE - 1) |
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#endif |
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) { |
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LS_GENERIC_N(cpu, ic); |
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return; |
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} |
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|
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addr &= 0xfff; |
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|
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#ifdef LS_LOAD |
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/* Load: */ |
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|
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#ifdef LS_1 |
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reg(ic->arg[0]) = |
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#ifdef LS_SIGNED |
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(int8_t) |
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#endif |
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p[addr]; |
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#endif /* LS_1 */ |
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|
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#ifdef LS_2 |
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reg(ic->arg[0]) = |
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#ifdef LS_SIGNED |
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(int16_t) |
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#endif |
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#ifdef LS_BE |
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#ifdef HOST_BIG_ENDIAN |
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( *(uint16_t *)(p + addr) ); |
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#else |
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((p[addr]<<8) + p[addr+1]); |
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#endif |
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#else |
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#ifdef HOST_LITTLE_ENDIAN |
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( *(uint16_t *)(p + addr) ); |
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#else |
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(p[addr] + (p[addr+1]<<8)); |
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#endif |
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#endif |
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#endif /* LS_2 */ |
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|
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#ifdef LS_4 |
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reg(ic->arg[0]) = |
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#ifdef LS_SIGNED |
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(int32_t) |
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#else |
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(uint32_t) |
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#endif |
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#ifdef LS_BE |
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#ifdef HOST_BIG_ENDIAN |
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( *(uint32_t *)(p + addr) ); |
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#else |
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((p[addr]<<24) + (p[addr+1]<<16) + (p[addr+2]<<8) + p[addr+3]); |
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#endif |
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#else |
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#ifdef HOST_LITTLE_ENDIAN |
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( *(uint32_t *)(p + addr) ); |
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#else |
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(p[addr] + (p[addr+1]<<8) + (p[addr+2]<<16) + (p[addr+3]<<24)); |
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#endif |
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#endif |
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#endif /* LS_4 */ |
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|
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#ifdef LS_8 |
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*((uint64_t *)ic->arg[0]) = |
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#ifdef LS_BE |
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#ifdef HOST_BIG_ENDIAN |
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( *(uint64_t *)(p + addr) ); |
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#else |
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((uint64_t)p[addr] << 56) + ((uint64_t)p[addr+1] << 48) + |
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((uint64_t)p[addr+2] << 40) + ((uint64_t)p[addr+3] << 32) + |
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((uint64_t)p[addr+4] << 24) + |
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(p[addr+5] << 16) + (p[addr+6] << 8) + p[addr+7]; |
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#endif |
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#else |
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#ifdef HOST_LITTLE_ENDIAN |
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( *(uint64_t *)(p + addr) ); |
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#else |
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p[addr+0] + (p[addr+1] << 8) + (p[addr+2] << 16) + |
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((uint64_t)p[addr+3] << 24) + ((uint64_t)p[addr+4] << 32) + |
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((uint64_t)p[addr+5] << 40) + ((uint64_t)p[addr+6] << 48) + |
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((uint64_t)p[addr+7] << 56); |
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#endif |
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#endif |
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#endif /* LS_8 */ |
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|
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#else |
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/* Store: */ |
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|
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#ifdef LS_1 |
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p[addr] = reg(ic->arg[0]); |
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#endif |
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#ifdef LS_2 |
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{ uint32_t x = reg(ic->arg[0]); |
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#ifdef LS_BE |
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#ifdef HOST_BIG_ENDIAN |
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*((uint16_t *)(p+addr)) = x; } |
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#else |
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p[addr] = x >> 8; p[addr+1] = x; } |
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#endif |
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#else |
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#ifdef HOST_LITTLE_ENDIAN |
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*((uint16_t *)(p+addr)) = x; } |
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#else |
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p[addr] = x; p[addr+1] = x >> 8; } |
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#endif |
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#endif |
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#endif /* LS_2 */ |
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#ifdef LS_4 |
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{ uint32_t x = reg(ic->arg[0]); |
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#ifdef LS_BE |
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#ifdef HOST_BIG_ENDIAN |
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*((uint32_t *)(p+addr)) = x; } |
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#else |
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p[addr] = x >> 24; p[addr+1] = x >> 16; |
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p[addr+2] = x >> 8; p[addr+3] = x; } |
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#endif |
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#else |
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#ifdef HOST_LITTLE_ENDIAN |
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*((uint32_t *)(p+addr)) = x; } |
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#else |
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p[addr] = x; p[addr+1] = x >> 8; |
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p[addr+2] = x >> 16; p[addr+3] = x >> 24; } |
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#endif |
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#endif |
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#endif /* LS_4 */ |
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#ifdef LS_8 |
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{ uint64_t x = *(uint64_t *)(ic->arg[0]); |
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#ifdef LS_BE |
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#ifdef HOST_BIG_ENDIAN |
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*((uint64_t *)(p+addr)) = x; } |
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#else |
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p[addr] = x >> 56; p[addr+1] = x >> 48; p[addr+2] = x >> 40; |
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p[addr+3] = x >> 32; p[addr+4] = x >> 24; p[addr+5] = x >> 16; |
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p[addr+6] = x >> 8; p[addr+7] = x; } |
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#endif |
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#else |
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#ifdef HOST_LITTLE_ENDIAN |
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*((uint64_t *)(p+addr)) = x; } |
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#else |
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p[addr] = x; p[addr+1] = x >> 8; p[addr+2] = x >> 16; |
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p[addr+3] = x >> 24; p[addr+4] = x >> 32; p[addr+5] = x >> 40; |
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p[addr+6] = x >> 48; p[addr+7] = x >> 56; } |
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#endif |
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#endif |
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#endif /* LS_8 */ |
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|
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#endif /* store */ |
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} |
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