Annotation of /upstream/0.4.1/src/cpus/README_DYNTRANS

$Id: README_DYNTRANS,v 1.9 2006/03/15 20:34:05 debug Exp $

-------------------------------------------------------------------

PPC optimizations TODO:

        find high-level bottlenecks!

        inline cr0 field calculation

        load/store with r1 as base?

        multiple load/stores in a row (especially with base = r1)

        almost all branches are of the "general" form now, they don't
                need to be.

        combinations of compare + branch, similar to arm?

-------------------------------------------------------------------


Dyntrans TODO:

  x)  Make sure that all of these could work, at least in theory:

                        Instruction                     Word            Delay
        Arch.:          length:                         size:           slot:
        ------          -------                         -----           -----
        Alpha           32-bit                          64              no
        ARM             32-bit, 16-bit (Thumb)          32              no
        Atmel AVR       16-bit + variable               8               no
        F-CPU           ?                               ?               ?
        H8              16-bit                          8/16            no
        HPPA            32-bit                          64/32           yes
        i960            32-bit + variable               32              ?
        IA64            128-bit                         64              no
        M68K            16-bit + variable               32              no
        M88K            ?                               32 (?)          ?
        MIPS            32-bit, 16-bit (MIPS16)         64/32           yes
        OpenRISC        ?                               ?               ?
        PC532           ?                               32 (?)          ?
        POWER/PPC       32-bit                          64/32           no
        SH              32-bit, 16-bit (SHcompact)      64/32           yes(*)
        SPARC           32-bit                          64/32           yes
        x86             8-bit + variable                64/32/16        no
        VAX             8-bit + variable                32              no

        (*) Delay slot in SHcompact?


  x)  call/return address cache?

  x)  instr_call sequence analysis support? (For handtuning combinations.)

  x)  opcode statistics support?
                TODO: is instr_call statistics enough?

  x)  load/stores:
                o)  perhaps refactor/reuse common load/store code?
                o)  support for archs that allow transparent
                    unaligned load/stores (ppc, x86 etc)
                o)  alignment checks ==> exceptions
                o)  native byte order ==> faster loads, etc.

  x)  actual cache emulation

  x)  SMP: detect when an instruction such as ll/sc or cas is used,
            and "synchronize" approximately the number of executed instructions
            (or cycles) across all CPUs.

  x)  support for variable-length instructions (x86, m68k, i960, ...)
                Solution:  don't increase the next_ic between every
                        instruction, but let each instruction's handler do
                        that for itself.
                Problem: what about instructions crossing a (virtual)
                        page boundary? They cannot be translated once
                        and for all :( and must be interpreted slowly!

  x)  support for THUMB, MIPS16, userland SH  (arm, mips, sh)

  x)  support for Delay slots!  (mips, sparc, hppa, SHcompact?)

  x)  various register-window archs (SPARC etc)

  x)  Alpha: hahaha, zapnot and inserts/extracts don't
            compile into very nice code :-|  fix this
                Solution: if short assembly language snippets can be
                compiled on the current host, then compile such snippets
                for alpha_instr_zapnot etc.

  x)  x86: convert to dyntrans. LOTS of stuff to consider.

  x)  88k? vax? pc532? 6502? 6800? etc

1	dpavlin	24	$Id: README_DYNTRANS,v 1.9 2006/03/15 20:34:05 debug Exp $
2	dpavlin	14
3	dpavlin	20	-------------------------------------------------------------------
4
5			PPC optimizations TODO:
6
7			find high-level bottlenecks!
8	dpavlin	22
9	dpavlin	20	inline cr0 field calculation
10
11	dpavlin	22	load/store with r1 as base?
12
13			multiple load/stores in a row (especially with base = r1)
14
15			almost all branches are of the "general" form now, they don't
16			need to be.
17
18			combinations of compare + branch, similar to arm?
19
20	dpavlin	20	-------------------------------------------------------------------
21
22
23
24	dpavlin	14	Dyntrans TODO:
25
26			x) Make sure that all of these could work, at least in theory:
27
28			Instruction Word Delay
29			Arch.: length: size: slot:
30			------ ------- ----- -----
31			Alpha 32-bit 64 no
32			ARM 32-bit, 16-bit (Thumb) 32 no
33	dpavlin	24	Atmel AVR 16-bit + variable 8 no
34	dpavlin	20	F-CPU ? ? ?
35	dpavlin	24	H8 16-bit 8/16 no
36	dpavlin	14	HPPA 32-bit 64/32 yes
37			i960 32-bit + variable 32 ?
38			IA64 128-bit 64 no
39			M68K 16-bit + variable 32 no
40			M88K ? 32 (?) ?
41			MIPS 32-bit, 16-bit (MIPS16) 64/32 yes
42	dpavlin	20	OpenRISC ? ? ?
43	dpavlin	14	PC532 ? 32 (?) ?
44			POWER/PPC 32-bit 64/32 no
45			SH 32-bit, 16-bit (SHcompact) 64/32 yes(*)
46			SPARC 32-bit 64/32 yes
47			x86 8-bit + variable 64/32/16 no
48			VAX 8-bit + variable 32 no
49
50			(*) Delay slot in SHcompact?
51
52
53			x) call/return address cache?
54
55			x) instr_call sequence analysis support? (For handtuning combinations.)
56
57			x) opcode statistics support?
58			TODO: is instr_call statistics enough?
59
60			x) load/stores:
61	dpavlin	22	o) perhaps refactor/reuse common load/store code?
62	dpavlin	14	o) support for archs that allow transparent
63			unaligned load/stores (ppc, x86 etc)
64			o) alignment checks ==> exceptions
65			o) native byte order ==> faster loads, etc.
66
67			x) actual cache emulation
68
69			x) SMP: detect when an instruction such as ll/sc or cas is used,
70			and "synchronize" approximately the number of executed instructions
71			(or cycles) across all CPUs.
72
73			x) support for variable-length instructions (x86, m68k, i960, ...)
74			Solution: don't increase the next_ic between every
75			instruction, but let each instruction's handler do
76			that for itself.
77			Problem: what about instructions crossing a (virtual)
78			page boundary? They cannot be translated once
79			and for all :( and must be interpreted slowly!
80
81			x) support for THUMB, MIPS16, userland SH (arm, mips, sh)
82
83			x) support for Delay slots! (mips, sparc, hppa, SHcompact?)
84
85			x) various register-window archs (SPARC etc)
86
87			x) Alpha: hahaha, zapnot and inserts/extracts don't
88			compile into very nice code :-\| fix this
89			Solution: if short assembly language snippets can be
90			compiled on the current host, then compile such snippets
91			for alpha_instr_zapnot etc.
92
93			x) x86: convert to dyntrans. LOTS of stuff to consider.
94
95			x) 88k? vax? pc532? 6502? 6800? etc
96