src/include/cpu_alpha.h

#ifndef CPU_ALPHA_H
#define CPU_ALPHA_H

/*
 *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_alpha.h,v 1.30 2006/02/09 22:40:27 debug Exp $
 */

#include "misc.h"


struct cpu_family;

#define ALPHA_V0                0
#define ALPHA_A0                16
#define ALPHA_A1                17
#define ALPHA_A2                18
#define ALPHA_A3                19
#define ALPHA_A4                20
#define ALPHA_A5                21
#define ALPHA_RA                26
#define ALPHA_T12               27
#define ALPHA_SP                30
#define ALPHA_ZERO              31
#define N_ALPHA_REGS            32

#define ALPHA_REG_NAMES         {                               \
        "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",         \
        "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp",         \
        "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",         \
        "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero"     }


#define ALPHA_N_IC_ARGS                 3
#define ALPHA_INSTR_ALIGNMENT_SHIFT     2
#define ALPHA_IC_ENTRIES_SHIFT          11
#define ALPHA_IC_ENTRIES_PER_PAGE       (1 << ALPHA_IC_ENTRIES_SHIFT)
#define ALPHA_PC_TO_IC_ENTRY(a)         (((a)>>ALPHA_INSTR_ALIGNMENT_SHIFT) \
                                        & (ALPHA_IC_ENTRIES_PER_PAGE-1))
#define ALPHA_ADDR_TO_PAGENR(a)         ((a) >> (ALPHA_IC_ENTRIES_SHIFT \
                                        + ALPHA_INSTR_ALIGNMENT_SHIFT))

struct alpha_instr_call {
        void    (*f)(struct cpu *, struct alpha_instr_call *);
        size_t  arg[ALPHA_N_IC_ARGS];
};

/*  Translation cache struct for each physical page:  */
struct alpha_tc_physpage {
        struct alpha_instr_call ics[ALPHA_IC_ENTRIES_PER_PAGE + 1];
        uint32_t        next_ofs;       /*  or 0 for end of chain  */
        uint32_t        physaddr;
        int             flags;
};


/*
 *  Virtual->physical->host page entry:
 *
 *      13 + 13 + 13 bits = 39 bits (should be enough for most userspace
 *      applications)
 *
 *  There is also an additional check for kernel space addresses.
 */
#define ALPHA_TOPSHIFT                  39
#define ALPHA_TOP_KERNEL                0x1fffff8
#define ALPHA_LEVEL0_SHIFT              26
#define ALPHA_LEVEL0                    8192
#define ALPHA_LEVEL1_SHIFT              13
#define ALPHA_LEVEL1                    8192
struct alpha_vph_page {
        void            *host_load[ALPHA_LEVEL1];
        void            *host_store[ALPHA_LEVEL1];
        uint64_t        phys_addr[ALPHA_LEVEL1];
        struct alpha_tc_physpage *phys_page[ALPHA_LEVEL1];
        int             refcount;
        struct alpha_vph_page   *next;  /*  Freelist, used if refcount = 0.  */
};

#define ALPHA_MAX_VPH_TLB_ENTRIES       128
struct alpha_vpg_tlb_entry {
        unsigned char   valid;
        unsigned char   writeflag;
        int64_t         timestamp;
        uint64_t        vaddr_page;
        uint64_t        paddr_page;
        unsigned char   *host_page;
};

struct alpha_cpu {
        /*
         *  General Purpose Registers:
         */

        uint64_t                r[N_ALPHA_REGS];        /*  Integer  */
        uint64_t                f[N_ALPHA_REGS];        /*  Floating Point  */


        /*  Misc.:  */
        uint64_t                pcc;                    /*  Cycle Counter  */
        uint64_t                ipl;
        uint64_t                sysvalue;
        uint64_t                load_linked_addr;
        int                     ll_flag;


        /*
         *  Instruction translation cache:
         */
        DYNTRANS_ITC(alpha)

        /*
         *  Hardcoded Alpha virtual -> physical -> host address translation:
         */
        VPH_TLBS(alpha,ALPHA)
        struct alpha_vph_page   *vph_default_page;
        struct alpha_vph_page   *vph_next_free_page;
        struct alpha_vph_table  *vph_next_free_table;
        struct alpha_vph_page   *vph_table0[ALPHA_LEVEL0];
        struct alpha_vph_page   *vph_table0_kernel[ALPHA_LEVEL0];
};


/*  cpu_alpha.c:  */
void alpha_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
        unsigned char *host_page, int writeflag, uint64_t paddr_page);
void alpha_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
void alpha_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
int alpha_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
        unsigned char *data, size_t len, int writeflag, int cache_flags);
int alpha_userland_memory_rw(struct cpu *cpu, struct memory *mem,
        uint64_t vaddr, unsigned char *data, size_t len, int writeflag,
        int cache_flags);
int alpha_cpu_family_init(struct cpu_family *);

/*  cpu_alpha_palcode.c:  */
void alpha_palcode_name(uint32_t palcode, char *buf, size_t buflen);
void alpha_palcode(struct cpu *cpu, uint32_t palcode);


#endif  /*  CPU_ALPHA_H  */
1	#ifndef CPU_ALPHA_H
2	#define CPU_ALPHA_H
3
4	/*
5	* Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
6	*
7	* Redistribution and use in source and binary forms, with or without
8	* modification, are permitted provided that the following conditions are met:
9	*
10	* 1. Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.
12	* 2. Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	* 3. The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.
17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28	* SUCH DAMAGE.
29	*
30	*
31	* $Id: cpu_alpha.h,v 1.30 2006/02/09 22:40:27 debug Exp $
32	*/
33
34	#include "misc.h"
35
36
37	struct cpu_family;
38
39	#define ALPHA_V0 0
40	#define ALPHA_A0 16
41	#define ALPHA_A1 17
42	#define ALPHA_A2 18
43	#define ALPHA_A3 19
44	#define ALPHA_A4 20
45	#define ALPHA_A5 21
46	#define ALPHA_RA 26
47	#define ALPHA_T12 27
48	#define ALPHA_SP 30
49	#define ALPHA_ZERO 31
50	#define N_ALPHA_REGS 32
51
52	#define ALPHA_REG_NAMES { \
53	"v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", \
54	"t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", \
55	"a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", \
56	"t10", "t11", "ra", "t12", "at", "gp", "sp", "zero" }
57
58
59	#define ALPHA_N_IC_ARGS 3
60	#define ALPHA_INSTR_ALIGNMENT_SHIFT 2
61	#define ALPHA_IC_ENTRIES_SHIFT 11
62	#define ALPHA_IC_ENTRIES_PER_PAGE (1 << ALPHA_IC_ENTRIES_SHIFT)
63	#define ALPHA_PC_TO_IC_ENTRY(a) (((a)>>ALPHA_INSTR_ALIGNMENT_SHIFT) \
64	& (ALPHA_IC_ENTRIES_PER_PAGE-1))
65	#define ALPHA_ADDR_TO_PAGENR(a) ((a) >> (ALPHA_IC_ENTRIES_SHIFT \
66	+ ALPHA_INSTR_ALIGNMENT_SHIFT))
67
68	struct alpha_instr_call {
69	void (f)(struct cpu , struct alpha_instr_call *);
70	size_t arg[ALPHA_N_IC_ARGS];
71	};
72
73	/* Translation cache struct for each physical page: */
74	struct alpha_tc_physpage {
75	struct alpha_instr_call ics[ALPHA_IC_ENTRIES_PER_PAGE + 1];
76	uint32_t next_ofs; /* or 0 for end of chain */
77	uint32_t physaddr;
78	int flags;
79	};
80
81
82	/*
83	* Virtual->physical->host page entry:
84	*
85	* 13 + 13 + 13 bits = 39 bits (should be enough for most userspace
86	* applications)
87	*
88	* There is also an additional check for kernel space addresses.
89	*/
90	#define ALPHA_TOPSHIFT 39
91	#define ALPHA_TOP_KERNEL 0x1fffff8
92	#define ALPHA_LEVEL0_SHIFT 26
93	#define ALPHA_LEVEL0 8192
94	#define ALPHA_LEVEL1_SHIFT 13
95	#define ALPHA_LEVEL1 8192
96	struct alpha_vph_page {
97	void *host_load[ALPHA_LEVEL1];
98	void *host_store[ALPHA_LEVEL1];
99	uint64_t phys_addr[ALPHA_LEVEL1];
100	struct alpha_tc_physpage *phys_page[ALPHA_LEVEL1];
101	int refcount;
102	struct alpha_vph_page next; / Freelist, used if refcount = 0. */
103	};
104
105	#define ALPHA_MAX_VPH_TLB_ENTRIES 128
106	struct alpha_vpg_tlb_entry {
107	unsigned char valid;
108	unsigned char writeflag;
109	int64_t timestamp;
110	uint64_t vaddr_page;
111	uint64_t paddr_page;
112	unsigned char *host_page;
113	};
114
115	struct alpha_cpu {
116	/*
117	* General Purpose Registers:
118	*/
119
120	uint64_t r[N_ALPHA_REGS]; /* Integer */
121	uint64_t f[N_ALPHA_REGS]; /* Floating Point */
122
123
124	/* Misc.: */
125	uint64_t pcc; /* Cycle Counter */
126	uint64_t ipl;
127	uint64_t sysvalue;
128	uint64_t load_linked_addr;
129	int ll_flag;
130
131
132	/*
133	* Instruction translation cache:
134	*/
135	DYNTRANS_ITC(alpha)
136
137	/*
138	* Hardcoded Alpha virtual -> physical -> host address translation:
139	*/
140	VPH_TLBS(alpha,ALPHA)
141	struct alpha_vph_page *vph_default_page;
142	struct alpha_vph_page *vph_next_free_page;
143	struct alpha_vph_table *vph_next_free_table;
144	struct alpha_vph_page *vph_table0[ALPHA_LEVEL0];
145	struct alpha_vph_page *vph_table0_kernel[ALPHA_LEVEL0];
146	};
147
148
149	/* cpu_alpha.c: */
150	void alpha_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
151	unsigned char *host_page, int writeflag, uint64_t paddr_page);
152	void alpha_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
153	void alpha_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
154	int alpha_memory_rw(struct cpu cpu, struct memory mem, uint64_t vaddr,
155	unsigned char *data, size_t len, int writeflag, int cache_flags);
156	int alpha_userland_memory_rw(struct cpu cpu, struct memory mem,
157	uint64_t vaddr, unsigned char *data, size_t len, int writeflag,
158	int cache_flags);
159	int alpha_cpu_family_init(struct cpu_family *);
160
161	/* cpu_alpha_palcode.c: */
162	void alpha_palcode_name(uint32_t palcode, char *buf, size_t buflen);
163	void alpha_palcode(struct cpu *cpu, uint32_t palcode);
164
165
166	#endif /* CPU_ALPHA_H */