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/* GXemul: $Id: armreg.h,v 1.2 2006/02/05 10:26:36 debug Exp $ */ |
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/* $NetBSD: armreg.h,v 1.33 2005/07/20 14:38:11 nonaka Exp $ */ |
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|
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/* |
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* Copyright (c) 1998, 2001 Ben Harris |
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* Copyright (c) 1994-1996 Mark Brinicombe. |
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* Copyright (c) 1994 Brini. |
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* All rights reserved. |
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* |
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* This code is derived from software written for Brini by Mark Brinicombe |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed by Brini. |
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* 4. The name of the company nor the name of the author may be used to |
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* endorse or promote products derived from this software without specific |
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* prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED |
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, |
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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*/ |
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|
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#ifndef _ARM_ARMREG_H |
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#define _ARM_ARMREG_H |
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|
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/* |
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* ARM Process Status Register |
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* |
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* The picture in the ARM manuals looks like this: |
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* 3 3 2 2 2 2 |
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* 1 0 9 8 7 6 8 7 6 5 4 0 |
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* +-+-+-+-+-+-------------------------------------+-+-+-+---------+ |
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* |N|Z|C|V|Q| reserved |I|F|T|M M M M M| |
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* | | | | | | | | | |4 3 2 1 0| |
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* +-+-+-+-+-+-------------------------------------+-+-+-+---------+ |
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*/ |
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|
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#define PSR_FLAGS 0xf0000000 /* flags */ |
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#define PSR_N_bit (1 << 31) /* negative */ |
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#define PSR_Z_bit (1 << 30) /* zero */ |
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#define PSR_C_bit (1 << 29) /* carry */ |
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#define PSR_V_bit (1 << 28) /* overflow */ |
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|
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#define PSR_Q_bit (1 << 27) /* saturation */ |
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|
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#define I32_bit (1 << 7) /* IRQ disable */ |
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#define F32_bit (1 << 6) /* FIQ disable */ |
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|
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#define PSR_T_bit (1 << 5) /* Thumb state */ |
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#define PSR_J_bit (1 << 24) /* Java mode */ |
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|
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#define PSR_MODE 0x0000001f /* mode mask */ |
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#define PSR_USR26_MODE 0x00000000 |
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#define PSR_FIQ26_MODE 0x00000001 |
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#define PSR_IRQ26_MODE 0x00000002 |
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#define PSR_SVC26_MODE 0x00000003 |
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#define PSR_USR32_MODE 0x00000010 |
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#define PSR_FIQ32_MODE 0x00000011 |
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#define PSR_IRQ32_MODE 0x00000012 |
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#define PSR_SVC32_MODE 0x00000013 |
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#define PSR_ABT32_MODE 0x00000017 |
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#define PSR_UND32_MODE 0x0000001b |
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#define PSR_SYS32_MODE 0x0000001f |
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#define PSR_32_MODE 0x00000010 |
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|
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#define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */ |
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#define PSR_IN_32_MODE(psr) ((psr) & PSR_32_MODE) |
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|
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/* In 26-bit modes, the PSR is stuffed into R15 along with the PC. */ |
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|
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#define R15_MODE 0x00000003 |
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#define R15_MODE_USR 0x00000000 |
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#define R15_MODE_FIQ 0x00000001 |
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#define R15_MODE_IRQ 0x00000002 |
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#define R15_MODE_SVC 0x00000003 |
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|
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#define R15_PC 0x03fffffc |
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|
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#define R15_FIQ_DISABLE 0x04000000 |
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#define R15_IRQ_DISABLE 0x08000000 |
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|
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#define R15_FLAGS 0xf0000000 |
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#define R15_FLAG_N 0x80000000 |
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#define R15_FLAG_Z 0x40000000 |
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#define R15_FLAG_C 0x20000000 |
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#define R15_FLAG_V 0x10000000 |
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|
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/* |
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* Co-processor 15: The system control co-processor. |
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*/ |
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|
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#define ARM_CP15_CPU_ID 0 |
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|
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/* |
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* The CPU ID register is theoretically structured, but the definitions of |
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* the fields keep changing. |
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*/ |
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|
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/* The high-order byte is always the implementor */ |
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#define CPU_ID_IMPLEMENTOR_MASK 0xff000000 |
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#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ |
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#define CPU_ID_DEC 0x44000000 /* 'D' */ |
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#define CPU_ID_INTEL 0x69000000 /* 'i' */ |
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#define CPU_ID_TI 0x54000000 /* 'T' */ |
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|
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/* How to decide what format the CPUID is in. */ |
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#define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) |
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#define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) |
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#define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) |
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|
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/* On ARM3 and ARM6, this byte holds the foundry ID. */ |
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#define CPU_ID_FOUNDRY_MASK 0x00ff0000 |
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#define CPU_ID_FOUNDRY_VLSI 0x00560000 |
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|
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/* On ARM7 it holds the architecture and variant (sub-model) */ |
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#define CPU_ID_7ARCH_MASK 0x00800000 |
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#define CPU_ID_7ARCH_V3 0x00000000 |
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#define CPU_ID_7ARCH_V4T 0x00800000 |
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#define CPU_ID_7VARIANT_MASK 0x007f0000 |
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|
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/* On more recent ARMs, it does the same, but in a different format */ |
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#define CPU_ID_ARCH_MASK 0x000f0000 |
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#define CPU_ID_ARCH_V3 0x00000000 |
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#define CPU_ID_ARCH_V4 0x00010000 |
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#define CPU_ID_ARCH_V4T 0x00020000 |
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#define CPU_ID_ARCH_V5 0x00030000 |
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#define CPU_ID_ARCH_V5T 0x00040000 |
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#define CPU_ID_ARCH_V5TE 0x00050000 |
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#define CPU_ID_ARCH_V5TEJ 0x00060000 |
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#define CPU_ID_ARCH_V6 0x00070000 |
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#define CPU_ID_VARIANT_MASK 0x00f00000 |
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|
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/* Next three nybbles are part number */ |
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#define CPU_ID_PARTNO_MASK 0x0000fff0 |
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|
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/* Intel XScale has sub fields in part number */ |
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#define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ |
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#define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ |
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#define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ |
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|
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/* And finally, the revision number. */ |
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#define CPU_ID_REVISION_MASK 0x0000000f |
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|
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/* Individual CPUs are probably best IDed by everything but the revision. */ |
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#define CPU_ID_CPU_MASK 0xfffffff0 |
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|
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/* Fake CPU IDs for ARMs without CP15 */ |
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#define CPU_ID_ARM2 0x41560200 |
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#define CPU_ID_ARM250 0x41560250 |
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|
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/* Pre-ARM7 CPUs -- [15:12] == 0 */ |
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#define CPU_ID_ARM3 0x41560300 |
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#define CPU_ID_ARM600 0x41560600 |
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#define CPU_ID_ARM610 0x41560610 |
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#define CPU_ID_ARM620 0x41560620 |
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|
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/* ARM7 CPUs -- [15:12] == 7 */ |
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#define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ |
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#define CPU_ID_ARM710 0x41007100 |
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#define CPU_ID_ARM7500 0x41027100 /* XXX This is a guess. */ |
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#define CPU_ID_ARM710A 0x41047100 /* inc ARM7100 */ |
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#define CPU_ID_ARM7500FE 0x41077100 |
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#define CPU_ID_ARM710T 0x41807100 |
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#define CPU_ID_ARM720T 0x41807200 |
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#define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ |
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#define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ |
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|
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/* Post-ARM7 CPUs */ |
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#define CPU_ID_ARM810 0x41018100 |
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#define CPU_ID_ARM920T 0x41129200 |
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#define CPU_ID_ARM922T 0x41029220 |
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#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ |
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#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ |
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#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ |
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#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ |
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#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ |
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#define CPU_ID_ARM1022ES 0x4105a220 |
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#define CPU_ID_ARM1026EJS 0x4106a260 |
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#define CPU_ID_ARM1136JS 0x4107b360 |
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#define CPU_ID_ARM1136JSR1 0x4117b360 |
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#define CPU_ID_SA110 0x4401a100 |
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#define CPU_ID_SA1100 0x4401a110 |
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#define CPU_ID_TI925T 0x54029250 |
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#define CPU_ID_SA1110 0x6901b110 |
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#define CPU_ID_IXP1200 0x6901c120 |
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#define CPU_ID_80200 0x69052000 |
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#define CPU_ID_PXA250 0x69052100 /* sans core revision */ |
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#define CPU_ID_PXA210 0x69052120 |
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#define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ |
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#define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ |
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#define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ |
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#define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ |
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#define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ |
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#define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ |
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#define CPU_ID_PXA27X 0x69054110 |
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#define CPU_ID_80321_400 0x69052420 |
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#define CPU_ID_80321_600 0x69052430 |
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#define CPU_ID_80321_400_B0 0x69052c20 |
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#define CPU_ID_80321_600_B0 0x69052c30 |
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#define CPU_ID_80219_400 0x69052e20 |
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#define CPU_ID_80219_600 0x69052e30 |
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#define CPU_ID_IXP425_533 0x690541c0 |
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#define CPU_ID_IXP425_400 0x690541d0 |
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#define CPU_ID_IXP425_266 0x690541f0 |
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|
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/* ARM3-specific coprocessor 15 registers */ |
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#define ARM3_CP15_FLUSH 1 |
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#define ARM3_CP15_CONTROL 2 |
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#define ARM3_CP15_CACHEABLE 3 |
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#define ARM3_CP15_UPDATEABLE 4 |
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#define ARM3_CP15_DISRUPTIVE 5 |
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|
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/* ARM3 Control register bits */ |
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#define ARM3_CTL_CACHE_ON 0x00000001 |
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#define ARM3_CTL_SHARED 0x00000002 |
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#define ARM3_CTL_MONITOR 0x00000004 |
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|
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/* |
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* Post-ARM3 CP15 registers: |
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* |
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* 1 Control register |
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* |
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* 2 Translation Table Base |
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* |
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* 3 Domain Access Control |
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* |
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* 4 Reserved |
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* |
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* 5 Fault Status |
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* |
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* 6 Fault Address |
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* |
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* 7 Cache/write-buffer Control |
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* |
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* 8 TLB Control |
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* |
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* 9 Cache Lockdown |
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* |
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* 10 TLB Lockdown |
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* |
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* 11 Reserved |
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* |
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* 12 Reserved |
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* |
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* 13 Process ID (for FCSE) |
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* |
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* 14 Reserved |
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* |
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* 15 Implementation Dependent |
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*/ |
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|
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/* Some of the definitions below need cleaning up for V3/V4 architectures */ |
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|
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/* CPU control register (CP15 register 1) */ |
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#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ |
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#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ |
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#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ |
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#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ |
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#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ |
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#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ |
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#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ |
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#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ |
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#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ |
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#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ |
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#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ |
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#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ |
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#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ |
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#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ |
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#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ |
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#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ |
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|
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#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE |
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|
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/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */ |
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#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ |
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#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ |
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#define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ |
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#define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ |
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#define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ |
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#define XSCALE_AUXCTL_MD_MASK 0x00000030 |
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|
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/* Cache type register definitions */ |
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#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ |
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#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ |
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#define CPU_CT_S (1U << 24) /* split cache */ |
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#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ |
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|
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#define CPU_CT_CTYPE_WT 0 /* write-through */ |
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#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ |
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#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ |
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#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ |
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#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ |
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|
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#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ |
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#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ |
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#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ |
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#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ |
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|
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/* Fault status register definitions */ |
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|
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#define FAULT_TYPE_MASK 0x0f |
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#define FAULT_USER 0x10 |
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|
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#define FAULT_WRTBUF_0 0x00 /* Vector Exception */ |
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#define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ |
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#define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ |
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#define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ |
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#define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ |
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#define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ |
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#define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ |
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#define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ |
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#define FAULT_ALIGN_0 0x01 /* Alignment */ |
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#define FAULT_ALIGN_1 0x03 /* Alignment */ |
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#define FAULT_TRANS_S 0x05 /* Translation -- Section */ |
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#define FAULT_TRANS_P 0x07 /* Translation -- Page */ |
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#define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ |
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#define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ |
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#define FAULT_PERM_S 0x0d /* Permission -- Section */ |
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#define FAULT_PERM_P 0x0f /* Permission -- Page */ |
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|
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#define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ |
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|
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/* |
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* Address of the vector page, low and high versions. |
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*/ |
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#define ARM_VECTORS_LOW 0x00000000U |
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#define ARM_VECTORS_HIGH 0xffff0000U |
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|
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/* |
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* ARM Instructions |
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* |
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* 3 3 2 2 2 |
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* 1 0 9 8 7 0 |
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* +-------+-------------------------------------------------------+ |
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* | cond | instruction dependent | |
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* |c c c c| | |
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* +-------+-------------------------------------------------------+ |
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*/ |
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|
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#define INSN_SIZE 4 /* Always 4 bytes */ |
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#define INSN_COND_MASK 0xf0000000 /* Condition mask */ |
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#define INSN_COND_AL 0xe0000000 /* Always condition */ |
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|
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#define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ |
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|
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#endif |
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