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/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_v3.c,v 1.4 2006/02/18 17:55:25 debug Exp $ |
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* |
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* V3 Semiconductor PCI controller. |
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* |
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* See NetBSD's src/sys/arch/algor/pci/ for details. |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "bus_pci.h" |
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#include "cpu.h" |
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#include "device.h" |
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#include "devices.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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|
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|
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DEVICE_ACCESS(v3_pci) |
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{ |
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uint64_t idata = 0, odata = 0; |
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int bus, dev, func, reg; |
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struct v3_data *d = extra; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN); |
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|
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/* Decompose the tag: */ |
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relative_addr &= 0xfffff; |
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relative_addr |= ((d->lb_map0 & 0xfff0) << 16); |
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bus = 0; |
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for (dev=24; dev<32; dev++) |
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if (relative_addr & (1 << dev)) |
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break; |
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dev -= 24; |
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if (dev == 8) { |
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fatal("[ v3_pci: NO DEVICE? ]\n"); |
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dev = 0; |
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} |
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func = (relative_addr >> 8) & 7; |
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reg = relative_addr & 0xfc; |
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bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg); |
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|
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/* Pass semi-direct PCI accesses onto bus_pci: */ |
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bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ? |
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&odata : &idata, len, writeflag); |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata); |
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|
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return 1; |
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} |
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|
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|
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DEVICE_ACCESS(v3) |
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{ |
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struct v3_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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|
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switch (relative_addr) { |
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|
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case 0x06: /* PCI stat */ |
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break; |
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|
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case 0x08: /* Revision */ |
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odata = 4; |
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break; |
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|
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case 0x18: /* PCI DMA base 1 */ |
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odata = 0x11000000; |
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break; |
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|
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case 0x5e: /* LB MAP0 */ |
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if (writeflag == MEM_READ) |
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odata = d->lb_map0; |
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else |
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d->lb_map0 = idata; |
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break; |
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|
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case 0x62: /* PCI mem base 1 */ |
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odata = 0x1100; |
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break; |
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|
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case 0x64: /* L2 BASE */ |
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odata = 1; /* pci i/o enable */ |
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break; |
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|
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case 0x66: /* Map 2 */ |
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odata = 0x1d00; |
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break; |
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|
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default:if (writeflag == MEM_WRITE) { |
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fatal("[ v3: unimplemented write to " |
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"offset 0x%x: data=0x%x ]\n", (int) |
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relative_addr, (int)idata); |
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} else { |
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fatal("[ v3: unimplemented read from " |
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"offset 0x%x ]\n", (int)relative_addr); |
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} |
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} |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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struct v3_data *dev_v3_init(struct machine *machine, struct memory *mem) |
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{ |
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struct v3_data *d; |
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|
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d = malloc(sizeof(struct v3_data)); |
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if (d == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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memset(d, 0, sizeof(struct v3_data)); |
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|
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/* Register a PCI bus: */ |
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d->pci_data = bus_pci_init( |
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machine, |
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0 /* pciirq: TODO */, |
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0x1d000000, /* pci device io offset */ |
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0x11000000, /* pci device mem offset: TODO */ |
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0x00000000, /* PCI portbase: TODO */ |
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0x00000000, /* PCI membase: TODO */ |
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0x00000000, /* PCI irqbase: TODO */ |
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0x1d000000, /* ISA portbase */ |
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0x10000000, /* ISA membase */ |
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8); /* ISA irqbase */ |
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|
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switch (machine->machine_type) { |
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case MACHINE_ALGOR: |
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bus_pci_add(machine, d->pci_data, mem, 0, 2, 0, "piix3_isa"); |
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bus_pci_add(machine, d->pci_data, mem, 0, 2, 1, "piix3_ide"); |
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break; |
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default:fatal("!\n! WARNING: v3 for non-implemented machine" |
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" type %i\n!\n", machine->machine_type); |
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exit(1); |
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} |
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|
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/* PCI configuration space: */ |
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memory_device_register(mem, "v3_pci", 0x1ee00000, 0x100000, |
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dev_v3_pci_access, d, DM_DEFAULT, NULL); |
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|
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/* PCI controller: */ |
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memory_device_register(mem, "v3", 0x1ef00000, 0x1000, |
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dev_v3_access, d, DM_DEFAULT, NULL); |
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|
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return d; |
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} |
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|