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/* |
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* Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_rd94.c,v 1.34 2006/02/09 20:02:59 debug Exp $ |
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* |
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* Used by NEC-RD94, -R94, and -R96. |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "bus_pci.h" |
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#include "cop0.h" |
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#include "cpu.h" |
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#include "cpu_mips.h" |
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#include "device.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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|
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#include "rd94.h" |
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|
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|
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#define RD94_TICK_SHIFT 14 |
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|
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#define DEV_RD94_LENGTH 0x1000 |
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|
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struct rd94_data { |
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struct pci_data *pci_data; |
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uint32_t reg[DEV_RD94_LENGTH / 4]; |
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int pciirq; |
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|
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int intmask; |
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int interval; |
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int interval_start; |
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}; |
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|
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|
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/* |
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* dev_rd94_tick(): |
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*/ |
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void dev_rd94_tick(struct cpu *cpu, void *extra) |
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{ |
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struct rd94_data *d = extra; |
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|
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/* TODO: hm... intmask !=0 ? */ |
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if (d->interval_start > 0 && d->interval > 0 && d->intmask != 0) { |
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d->interval --; |
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if (d->interval <= 0) { |
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debug("[ rd94: interval timer interrupt ]\n"); |
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cpu_interrupt(cpu, 5); |
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} |
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} |
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} |
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|
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|
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/* |
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* dev_rd94_access(): |
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*/ |
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DEVICE_ACCESS(rd94) |
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{ |
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struct rd94_data *d = (struct rd94_data *) extra; |
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uint64_t idata = 0, odata = 0; |
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int regnr, bus, dev, func, pcireg; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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|
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regnr = relative_addr / sizeof(uint32_t); |
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|
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switch (relative_addr) { |
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|
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case RD94_SYS_CONFIG: |
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if (writeflag == MEM_WRITE) { |
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fatal("[ rd94: write to CONFIG: 0x%llx ]\n", |
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(long long)idata); |
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} else { |
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odata = 0; |
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fatal("[ rd94: read from CONFIG: 0x%llx ]\n", |
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(long long)odata); |
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} |
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break; |
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|
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case RD94_SYS_INTSTAT1: /* LB (Local Bus ???) */ |
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if (writeflag == MEM_WRITE) { |
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} else { |
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/* Return value is (irq level + 1) << 2 */ |
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odata = (8+1) << 2; |
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|
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/* Ugly hack: */ |
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if ((cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] & 0x800) |
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== 0) |
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odata = 0; |
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} |
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debug("[ rd94: intstat1 ]\n"); |
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/* cpu_interrupt_ack(cpu, 3); */ |
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break; |
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|
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case RD94_SYS_INTSTAT2: /* PCI/EISA */ |
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if (writeflag == MEM_WRITE) { |
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} else { |
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odata = 0; /* TODO */ |
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} |
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debug("[ rd94: intstat2 ]\n"); |
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/* cpu_interrupt_ack(cpu, 4); */ |
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break; |
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|
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case RD94_SYS_INTSTAT3: /* IT (Interval Timer) */ |
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if (writeflag == MEM_WRITE) { |
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} else { |
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odata = 0; /* return value does not matter? */ |
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} |
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debug("[ rd94: intstat3 ]\n"); |
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cpu_interrupt_ack(cpu, 5); |
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d->interval = d->interval_start; |
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break; |
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|
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case RD94_SYS_INTSTAT4: /* IPI */ |
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if (writeflag == MEM_WRITE) { |
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} else { |
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odata = 0; /* return value does not matter? */ |
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} |
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fatal("[ rd94: intstat4 ]\n"); |
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cpu_interrupt_ack(cpu, 6); |
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break; |
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|
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case RD94_SYS_CPUID: |
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if (writeflag == MEM_WRITE) { |
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fatal("[ rd94: write to CPUID: 0x%llx ]\n", |
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(long long)idata); |
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} else { |
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odata = cpu->cpu_id; |
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fatal("[ rd94: read from CPUID: 0x%llx ]\n", |
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(long long)odata); |
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} |
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break; |
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|
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case RD94_SYS_EXT_IMASK: |
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if (writeflag == MEM_WRITE) { |
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d->intmask = idata; |
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} else { |
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odata = d->intmask; |
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} |
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break; |
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|
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case RD94_SYS_IT_VALUE: |
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if (writeflag == MEM_WRITE) { |
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d->interval = d->interval_start = idata; |
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debug("[ rd94: setting Interval Timer value to %i ]\n", |
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(int)idata); |
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} else { |
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odata = d->interval_start; |
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/* TODO: or d->interval ? */; |
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} |
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break; |
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|
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case RD94_SYS_PCI_CONFADDR: |
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bus_pci_decompose_1(idata, &bus, &dev, &func, &pcireg); |
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bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, pcireg); |
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break; |
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|
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case RD94_SYS_PCI_CONFDATA: |
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bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ? |
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&odata : &idata, len, writeflag); |
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break; |
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|
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default:if (writeflag == MEM_WRITE) { |
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fatal("[ rd94: unimplemented write to address 0x%x, " |
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"data=0x%02x ]\n", (int)relative_addr, (int)idata); |
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} else { |
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fatal("[ rd94: unimplemented read from address 0x%x" |
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" ]\n", (int)relative_addr); |
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} |
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} |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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DEVINIT(rd94) |
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{ |
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struct rd94_data *d = malloc(sizeof(struct rd94_data)); |
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if (d == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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memset(d, 0, sizeof(struct rd94_data)); |
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d->pciirq = devinit->irq_nr; |
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d->pci_data = bus_pci_init(devinit->machine, d->pciirq, |
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0,0, 0,0,0, 0,0,0); |
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|
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memory_device_register(devinit->machine->memory, devinit->name, |
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devinit->addr, DEV_RD94_LENGTH, |
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dev_rd94_access, (void *)d, DM_DEFAULT, NULL); |
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|
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machine_add_tickfunction(devinit->machine, dev_rd94_tick, |
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d, RD94_TICK_SHIFT); |
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|
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devinit->return_ptr = d->pci_data; |
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|
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return 1; |
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} |
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