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/* |
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* Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_dec5800.c,v 1.18 2006/01/01 13:17:16 debug Exp $ |
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* |
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* Emulation of devices found in a DECsystem 58x0, where x is the number |
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* of CPUs in the system. (The CPU board is called KN5800 by Ultrix.) |
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* |
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* o) timers and misc stuff |
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* o) BI (Backplane Interconnect) |
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* o) CCA (Console Communication Area) |
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* o) XMI (Extended Memory Interconnect) |
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* |
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* TODO: This hardware is not very easy to find docs about. |
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* Perhaps VAX 6000/300 docs? |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "console.h" |
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#include "cpu.h" |
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#include "devices.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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|
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|
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/* |
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* dev_dec5800_tick(): |
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*/ |
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void dev_dec5800_tick(struct cpu *cpu, void *extra) |
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{ |
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struct dec5800_data *d = extra; |
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|
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/* Timer interrupts? */ |
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if (d->csr & 0x8000) { |
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debug("[ dec5800: timer interrupt! ]\n"); |
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|
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/* Set timer interrupt pending bit: */ |
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d->csr |= 0x20000000; |
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|
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cpu_interrupt(cpu, 3); |
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} |
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} |
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|
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|
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/* |
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* dev_dec5800_vectors_access(): |
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*/ |
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DEVICE_ACCESS(dec5800_vectors) |
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{ |
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uint64_t idata = 0, odata = 0; |
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struct dec5800_data *d = extra; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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|
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if (writeflag == MEM_READ) { |
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/* TODO */ |
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/* 0xfc = transmit interrupt, 0xf8 = receive interrupt, |
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0x80 = IPI */ |
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odata = d->vector_0x50; |
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/* odata = 0xfc; */ |
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debug("[ dec5800_vectors: read from 0x%02x: 0x%02x ]\n", |
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(int)relative_addr, (int)odata); |
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} else { |
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d->vector_0x50 = idata; |
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debug("[ dec5800_vectors: write to 0x%02x: 0x%02x ]\n", |
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(int)relative_addr, (int)idata); |
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} |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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/* |
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* dev_dec5800_access(): |
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*/ |
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DEVICE_ACCESS(dec5800) |
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{ |
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uint64_t idata = 0, odata = 0; |
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struct dec5800_data *d = extra; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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|
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/* Lowest 4 bits of csr contain cpu id: */ |
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d->csr = (d->csr & ~0xf) | (cpu->cpu_id & 0xf); |
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|
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switch (relative_addr) { |
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case 0x0000: /* csr */ |
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if (writeflag == MEM_READ) { |
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odata = d->csr; |
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odata ^= random() & 0x10000; |
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debug("[ dec5800: read from csr: 0x%08x ]\n", |
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(int)odata); |
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} else { |
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d->csr = idata; |
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|
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/* Ack. timer interrupts: */ |
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d->csr &= ~0x20000000; |
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cpu_interrupt_ack(cpu, 3); |
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|
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debug("[ dec5800: write to csr: 0x%08x ]\n", |
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(int)idata); |
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} |
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break; |
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default: |
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if (writeflag==MEM_READ) { |
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debug("[ dec5800: read from 0x%08lx ]\n", |
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(long)relative_addr); |
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} else { |
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debug("[ dec5800: write to 0x%08lx: 0x%08x ]\n", |
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(long)relative_addr, (int)idata); |
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} |
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} |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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/* |
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* dev_dec5800_init(): |
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*/ |
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struct dec5800_data *dev_dec5800_init(struct machine *machine, |
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struct memory *mem, uint64_t baseaddr) |
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{ |
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struct dec5800_data *d; |
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|
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d = malloc(sizeof(struct dec5800_data)); |
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if (d == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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memset(d, 0, sizeof(struct dec5800_data)); |
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|
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memory_device_register(mem, "dec5800", baseaddr, |
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DEV_DEC5800_LENGTH, dev_dec5800_access, d, DM_DEFAULT, NULL); |
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memory_device_register(mem, "dec5800_vectors", |
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baseaddr + 0x30000000, 0x100, dev_dec5800_vectors_access, |
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d, DM_DEFAULT, NULL); |
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machine_add_tickfunction(machine, dev_dec5800_tick, d, 14); |
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|
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return d; |
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} |
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|
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|
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/*****************************************************************************/ |
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|
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|
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#include "bireg.h" |
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|
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struct decbi_data { |
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int csr[NNODEBI]; |
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}; |
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|
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|
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/* |
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* dev_decbi_access(): |
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*/ |
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DEVICE_ACCESS(decbi) |
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{ |
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uint64_t idata = 0, odata = 0; |
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int node_nr; |
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struct decbi_data *d = extra; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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|
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relative_addr += BI_NODESIZE; /* HACK */ |
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|
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node_nr = relative_addr / BI_NODESIZE; |
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relative_addr &= (BI_NODESIZE - 1); |
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|
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/* TODO: This "1" here is the max node number in actual use. */ |
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if (node_nr > 1 || node_nr >= NNODEBI) |
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return 0; |
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|
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switch (relative_addr) { |
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case BIREG_DTYPE: |
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if (writeflag==MEM_READ) { |
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/* |
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* This is a list of the devices in our BI slots: |
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*/ |
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switch (node_nr) { |
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case 1: odata = BIDT_KDB50; break; /* Disk */ |
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/* case 2: odata = BIDT_DEBNA; break; */ |
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/* BIDT_DEBNA = Ethernet */ |
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/* case 3: odata = BIDT_MS820; break; */ |
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/* BIDT_MS820 = Memory */ |
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default: |
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/* No device. */ |
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odata = 0; |
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} |
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|
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debug("[ decbi: (node %i) read from BIREG_DTYPE:" |
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" 0x%x ]\n", node_nr, (int)odata); |
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} else { |
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debug("[ decbi: (node %i) attempt to write to " |
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"BIREG_DTYPE: 0x%08x ]\n", node_nr, (int)idata); |
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} |
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break; |
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case BIREG_VAXBICSR: |
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if (writeflag==MEM_READ) { |
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odata = (d->csr[node_nr] & ~BICSR_NODEMASK) | node_nr; |
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debug("[ decbi: (node %i) read from BIREG_" |
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"VAXBICSR: 0x%x ]\n", node_nr, (int)odata); |
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} else { |
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d->csr[node_nr] = idata; |
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debug("[ decbi: (node %i) attempt to write to " |
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"BIREG_VAXBICSR: 0x%08x ]\n", node_nr, (int)idata); |
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} |
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break; |
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case 0xf4: |
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if (writeflag==MEM_READ) { |
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odata = 0xffff; /* ? */ |
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debug("[ decbi: (node %i) read from 0xf4: " |
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"0x%x ]\n", node_nr, (int)odata); |
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} else { |
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debug("[ decbi: (node %i) attempt to write " |
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"to 0xf4: 0x%08x ]\n", node_nr, (int)idata); |
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} |
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break; |
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default: |
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if (writeflag==MEM_READ) { |
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debug("[ decbi: (node %i) read from unimplemented " |
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"0x%08lx ]\n", node_nr, (long)relative_addr, |
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(int)odata); |
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} else { |
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debug("[ decbi: (node %i) write to unimplemented " |
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"0x%08lx: 0x%08x ]\n", node_nr, |
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(long)relative_addr, (int)idata); |
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} |
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} |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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/* |
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* dev_decbi_init(): |
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*/ |
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void dev_decbi_init(struct memory *mem, uint64_t baseaddr) |
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{ |
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struct decbi_data *d; |
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|
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d = malloc(sizeof(struct decbi_data)); |
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if (d == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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memset(d, 0, sizeof(struct decbi_data)); |
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|
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memory_device_register(mem, "decbi", baseaddr + 0x2000, |
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DEV_DECBI_LENGTH - 0x2000, dev_decbi_access, d, DM_DEFAULT, NULL); |
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} |
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|
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|
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/*****************************************************************************/ |
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|
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|
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/* |
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* CCA, "Console Communication Area" for a DEC 5800 SMP system. |
| 299 |
*/ |
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|
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struct deccca_data { |
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int dummy; |
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}; |
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|
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|
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/* |
| 307 |
* dev_deccca_access(): |
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*/ |
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DEVICE_ACCESS(deccca) |
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{ |
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uint64_t idata = 0, odata = 0; |
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/* struct deccca_data *d = extra; */ |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
| 316 |
|
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switch (relative_addr) { |
| 318 |
case 6: |
| 319 |
case 7: |
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/* CCA "ID" bytes? These must be here, or Ultrix complains. */ |
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if (writeflag == MEM_READ) |
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odata = 67; |
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break; |
| 324 |
case 8: |
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if (writeflag == MEM_READ) |
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odata = cpu->machine->ncpus; |
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break; |
| 328 |
case 20: |
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if (writeflag == MEM_READ) |
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odata = (1 << cpu->machine->ncpus) - 1; |
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/* one bit for each cpu */ |
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break; |
| 333 |
case 28: |
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if (writeflag == MEM_READ) |
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odata = (1 << cpu->machine->ncpus) - 1; |
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/* one bit for each enabled(?) cpu */ |
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break; |
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default: |
| 339 |
if (writeflag==MEM_READ) { |
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debug("[ deccca: read from 0x%08lx ]\n", |
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(long)relative_addr); |
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} else { |
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debug("[ deccca: write to 0x%08lx: 0x%08x ]\n", |
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(long)relative_addr, (int)idata); |
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} |
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} |
| 347 |
|
| 348 |
if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
| 350 |
|
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return 1; |
| 352 |
} |
| 353 |
|
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|
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/* |
| 356 |
* dev_deccca_init(): |
| 357 |
*/ |
| 358 |
void dev_deccca_init(struct memory *mem, uint64_t baseaddr) |
| 359 |
{ |
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struct deccca_data *d; |
| 361 |
|
| 362 |
d = malloc(sizeof(struct deccca_data)); |
| 363 |
if (d == NULL) { |
| 364 |
fprintf(stderr, "out of memory\n"); |
| 365 |
exit(1); |
| 366 |
} |
| 367 |
memset(d, 0, sizeof(struct deccca_data)); |
| 368 |
|
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memory_device_register(mem, "deccca", baseaddr, DEV_DECCCA_LENGTH, |
| 370 |
dev_deccca_access, d, DM_DEFAULT, NULL); |
| 371 |
} |
| 372 |
|
| 373 |
|
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/*****************************************************************************/ |
| 375 |
|
| 376 |
|
| 377 |
/* |
| 378 |
* DEC 5800 XMI (this has to do with SMP...) |
| 379 |
*/ |
| 380 |
|
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#include "xmireg.h" |
| 382 |
|
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struct decxmi_data { |
| 384 |
uint32_t reg_0xc[NNODEXMI]; |
| 385 |
}; |
| 386 |
|
| 387 |
|
| 388 |
/* |
| 389 |
* dev_decxmi_access(): |
| 390 |
*/ |
| 391 |
DEVICE_ACCESS(decxmi) |
| 392 |
{ |
| 393 |
uint64_t idata = 0, odata = 0; |
| 394 |
int node_nr; |
| 395 |
struct decxmi_data *d = extra; |
| 396 |
|
| 397 |
if (writeflag == MEM_WRITE) |
| 398 |
idata = memory_readmax64(cpu, data, len); |
| 399 |
|
| 400 |
node_nr = relative_addr / XMI_NODESIZE; |
| 401 |
relative_addr &= (XMI_NODESIZE - 1); |
| 402 |
|
| 403 |
if (node_nr >= cpu->machine->ncpus + 1 || node_nr >= NNODEXMI) |
| 404 |
return 0; |
| 405 |
|
| 406 |
switch (relative_addr) { |
| 407 |
case XMI_TYPE: |
| 408 |
if (writeflag == MEM_READ) { |
| 409 |
/* |
| 410 |
* The first node is an XMI->BI adapter node, and then |
| 411 |
* there are n CPU nodes. |
| 412 |
*/ |
| 413 |
odata = XMIDT_ISIS; |
| 414 |
if (node_nr == 0) |
| 415 |
odata = XMIDT_DWMBA; |
| 416 |
|
| 417 |
debug("[ decxmi: (node %i) read from XMI_TYPE: " |
| 418 |
"0x%08x ]\n", node_nr, (int)odata); |
| 419 |
} else |
| 420 |
debug("[ decxmi: (node %i) write to XMI_TYPE: " |
| 421 |
"0x%08x ]\n", node_nr, (int)idata); |
| 422 |
break; |
| 423 |
case XMI_BUSERR: |
| 424 |
if (writeflag == MEM_READ) { |
| 425 |
odata = 0; |
| 426 |
debug("[ decxmi: (node %i) read from XMI_BUSERR: " |
| 427 |
"0x%08x ]\n", node_nr, (int)odata); |
| 428 |
} else |
| 429 |
debug("[ decxmi: (node %i) write to XMI_BUSERR: " |
| 430 |
"0x%08x ]\n", node_nr, (int)idata); |
| 431 |
break; |
| 432 |
case XMI_FAIL: |
| 433 |
if (writeflag == MEM_READ) { |
| 434 |
odata = 0; |
| 435 |
debug("[ decxmi: (node %i) read from XMI_FAIL: " |
| 436 |
"0x%08x ]\n", node_nr, (int)odata); |
| 437 |
} else |
| 438 |
debug("[ decxmi: (node %i) write to XMI_FAIL: " |
| 439 |
"0x%08x ]\n", node_nr, (int)idata); |
| 440 |
break; |
| 441 |
case 0xc: |
| 442 |
if (writeflag == MEM_READ) { |
| 443 |
odata = d->reg_0xc[node_nr]; |
| 444 |
debug("[ decxmi: (node %i) read from REG 0xC: " |
| 445 |
"0x%08x ]\n", node_nr, (int)odata); |
| 446 |
} else { |
| 447 |
d->reg_0xc[node_nr] = idata; |
| 448 |
debug("[ decxmi: (node %i) write to REG 0xC: " |
| 449 |
"0x%08x ]\n", node_nr, (int)idata); |
| 450 |
} |
| 451 |
break; |
| 452 |
default: |
| 453 |
if (writeflag==MEM_READ) { |
| 454 |
debug("[ decxmi: (node %i) read from unimplemented " |
| 455 |
"0x%08lx ]\n", node_nr, (long)relative_addr, |
| 456 |
(int)odata); |
| 457 |
} else { |
| 458 |
debug("[ decxmi: (node %i) write to unimplemented " |
| 459 |
"0x%08lx: 0x%08x ]\n", node_nr, |
| 460 |
(long)relative_addr, (int)idata); |
| 461 |
} |
| 462 |
} |
| 463 |
|
| 464 |
if (writeflag == MEM_READ) |
| 465 |
memory_writemax64(cpu, data, len, odata); |
| 466 |
|
| 467 |
return 1; |
| 468 |
} |
| 469 |
|
| 470 |
|
| 471 |
/* |
| 472 |
* dev_decxmi_init(): |
| 473 |
*/ |
| 474 |
void dev_decxmi_init(struct memory *mem, uint64_t baseaddr) |
| 475 |
{ |
| 476 |
struct decxmi_data *d; |
| 477 |
|
| 478 |
d = malloc(sizeof(struct decxmi_data)); |
| 479 |
if (d == NULL) { |
| 480 |
fprintf(stderr, "out of memory\n"); |
| 481 |
exit(1); |
| 482 |
} |
| 483 |
memset(d, 0, sizeof(struct decxmi_data)); |
| 484 |
|
| 485 |
memory_device_register(mem, "decxmi", baseaddr, DEV_DECXMI_LENGTH, |
| 486 |
dev_decxmi_access, d, DM_DEFAULT, NULL); |
| 487 |
} |
| 488 |
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