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/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_arm_instr_dpi.c,v 1.16 2005/11/19 18:53:07 debug Exp $ |
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* |
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* |
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* ARM Data Processing Instructions |
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* -------------------------------- |
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* |
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* xxxx000a aaaSnnnn ddddcccc ctttmmmm Register form |
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* xxxx001a aaaSnnnn ddddrrrr bbbbbbbb Immediate form |
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* |
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* 4 bits to select which instruction, one of the following: |
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* |
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* 0000 and 1000 tst |
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* 0001 eor 1001 teq |
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* 0010 sub 1010 cmp |
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* 0011 rsb 1011 cmn |
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* 0100 add 1100 orr |
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* 0101 adc 1101 mov |
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* 0110 sbc 1110 bic |
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* 0111 rsc 1111 mvn |
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* |
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* 1 bit to select Status flag update. |
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* |
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* 1 bit to select Register form or Immediate form. |
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* |
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* 1 bit to select if the PC register is used. |
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* |
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* Each function must also (as always) be repeated for each possible ARM |
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* condition code (15 in total). Total: 1920 functions. |
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* |
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* NOTE: This does not include any special common cases, which might be |
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* nice to have. Examples: comparing against zero, moving common |
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* constants. |
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* |
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* See src/tools/generate_arm_dpi.c for more details. |
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*/ |
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|
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|
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/* |
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* arg[0] = pointer to rn |
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* arg[1] = int32_t immediate value OR ptr to a reg_func() function |
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* arg[2] = pointer to rd |
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*/ |
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void A__NAME(struct cpu *cpu, struct arm_instr_call *ic) |
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{ |
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#if defined(A__RSB) || defined(A__RSC) |
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#define VAR_A b |
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#define VAR_B a |
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#else |
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#define VAR_A a |
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#define VAR_B b |
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#endif |
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|
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#ifdef A__REG |
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uint32_t (*reg_func)(struct cpu *, struct arm_instr_call *) |
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= (void *)(size_t)ic->arg[1]; |
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#endif |
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|
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#ifdef A__S |
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uint32_t c32; |
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#endif |
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#if defined(A__CMP) || defined(A__CMN) || defined(A__ADC) || defined(A__ADD) \ |
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|| defined(A__RSC) || defined(A__RSC) || defined(A__SBC) || defined(A__SUB) |
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#ifdef A__S |
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uint64_t |
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#else |
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uint32_t |
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#endif |
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#else |
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uint32_t |
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#endif |
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VAR_B = |
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#ifdef A__REG |
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reg_func(cpu, ic) |
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#else |
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#ifdef A__REGSHORT |
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reg(ic->arg[1]) |
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#else |
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ic->arg[1] |
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#endif |
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#endif |
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, c64 |
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#if !defined(A__MOV) && !defined(A__MVN) |
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, VAR_A = reg(ic->arg[0]) |
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#endif |
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; |
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|
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#if defined(A__MOV) || defined(A__MVN) || defined(A__TST) || defined(A__TEQ) \ |
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|| defined(A__AND) || defined(A__BIC) || defined(A__EOR) || defined(A__ORR) |
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#if !defined(A__REG) && defined(A__S) |
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/* |
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* TODO: This is not 100% correct, but should work with "recommended" |
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* ARM code: Immediate values larger than 255 are encoded with |
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* rotation. If the S-bit is set, then the carry bit is set to the |
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* highest bit of the operand. |
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* |
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* TODO 2: Perhaps this check should be moved out from here, and into |
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* cpu_arm_instr.c. (More correct, and higher performance.) |
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*/ |
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if (VAR_B > 255) { |
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if (VAR_B & 0x80000000) |
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cpu->cd.arm.flags |= ARM_F_C; |
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else |
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cpu->cd.arm.flags &= ~ARM_F_C; |
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} |
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#endif |
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#endif |
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|
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|
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#if !defined(A__MOV) && !defined(A__MVN) |
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#ifdef A__PC |
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if (ic->arg[0] == (size_t)&cpu->cd.arm.r[ARM_PC]) { |
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uint32_t low_pc = ((size_t)ic - (size_t) |
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cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call); |
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VAR_A = cpu->pc & ~((ARM_IC_ENTRIES_PER_PAGE-1) |
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<< ARM_INSTR_ALIGNMENT_SHIFT); |
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VAR_A += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT) + 8; |
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} |
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#endif |
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#endif |
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|
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/* |
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* Perform the operation: |
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*/ |
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#if defined(A__AND) || defined(A__TST) |
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c64 = a & b; |
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#endif |
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#if defined(A__EOR) || defined(A__TEQ) |
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c64 = a ^ b; |
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#endif |
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#if defined(A__SUB) || defined(A__CMP) || defined(A__RSB) |
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c64 = a - b; |
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#endif |
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#if defined(A__ADD) || defined(A__CMN) |
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c64 = a + b; |
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#endif |
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#if defined(A__ADC) |
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c64 = a + b + (cpu->cd.arm.flags & ARM_F_C? 1 : 0); |
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#endif |
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#if defined(A__SBC) || defined(A__RSC) |
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b += (cpu->cd.arm.flags & ARM_F_C? 0 : 1); |
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c64 = a - b; |
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#endif |
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#if defined(A__ORR) |
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c64 = a | b; |
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#endif |
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#if defined(A__MOV) |
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c64 = b; |
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#endif |
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#if defined(A__BIC) |
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c64 = a & ~b; |
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#endif |
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#if defined(A__MVN) |
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c64 = ~b; |
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#endif |
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|
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|
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#if defined(A__CMP) || defined(A__CMN) || defined(A__TST) || defined(A__TEQ) |
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/* No write to rd for compare/test. */ |
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#else |
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#ifdef A__PC |
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if (ic->arg[2] == (size_t)&cpu->cd.arm.r[ARM_PC]) { |
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#ifndef A__S |
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uint32_t old_pc = cpu->pc; |
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uint32_t mask_within_page = ((ARM_IC_ENTRIES_PER_PAGE-1) |
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<< ARM_INSTR_ALIGNMENT_SHIFT) | |
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((1 << ARM_INSTR_ALIGNMENT_SHIFT) - 1); |
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#endif |
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cpu->pc = (uint32_t)c64; |
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#ifdef A__S |
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/* Copy the right SPSR into CPSR: */ |
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arm_save_register_bank(cpu); |
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switch (cpu->cd.arm.cpsr & ARM_FLAG_MODE) { |
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case ARM_MODE_FIQ32: |
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cpu->cd.arm.cpsr = cpu->cd.arm.spsr_fiq; break; |
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case ARM_MODE_IRQ32: |
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cpu->cd.arm.cpsr = cpu->cd.arm.spsr_irq; break; |
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case ARM_MODE_SVC32: |
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cpu->cd.arm.cpsr = cpu->cd.arm.spsr_svc; break; |
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case ARM_MODE_ABT32: |
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cpu->cd.arm.cpsr = cpu->cd.arm.spsr_abt; break; |
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case ARM_MODE_UND32: |
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cpu->cd.arm.cpsr = cpu->cd.arm.spsr_und; break; |
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} |
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cpu->cd.arm.flags = cpu->cd.arm.cpsr >> 28; |
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arm_load_register_bank(cpu); |
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#else |
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if ((old_pc & ~mask_within_page) == |
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((uint32_t)cpu->pc & ~mask_within_page)) { |
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cpu->cd.arm.next_ic = cpu->cd.arm.cur_ic_page + |
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((cpu->pc & mask_within_page) >> |
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ARM_INSTR_ALIGNMENT_SHIFT); |
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} else |
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#endif |
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quick_pc_to_pointers(cpu); |
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return; |
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} else |
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reg(ic->arg[2]) = c64; |
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#else |
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reg(ic->arg[2]) = c64; |
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#endif |
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#endif |
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|
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|
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/* |
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* Status flag update (if the S-bit is set): |
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*/ |
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#ifdef A__S |
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c32 = c64; |
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cpu->cd.arm.flags |
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#if defined(A__CMP) || defined(A__CMN) || defined(A__ADC) || defined(A__ADD) \ |
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|| defined(A__RSB) || defined(A__RSC) || defined(A__SBC) || defined(A__SUB) |
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= 0; |
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#else |
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&= ~(ARM_F_Z | ARM_F_N); |
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#endif |
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|
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#if defined(A__CMP) || defined(A__RSB) || defined(A__SUB) || \ |
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defined(A__RSC) || defined(A__SBC) |
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if ((uint32_t)a >= (uint32_t)b) |
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cpu->cd.arm.flags |= ARM_F_C; |
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#else |
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#if defined(A__ADC) || defined(A__ADD) || defined(A__CMN) |
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if (c32 != c64) |
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cpu->cd.arm.flags |= ARM_F_C; |
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#endif |
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#endif |
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|
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if (c32 == 0) |
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cpu->cd.arm.flags |= ARM_F_Z; |
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|
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if ((int32_t)c32 < 0) |
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cpu->cd.arm.flags |= ARM_F_N; |
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|
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/* Calculate the Overflow bit: */ |
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#if defined(A__CMP) || defined(A__CMN) || defined(A__ADC) || defined(A__ADD) \ |
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|| defined(A__RSB) || defined(A__RSC) || defined(A__SBC) || defined(A__SUB) |
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{ |
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int v = 0; |
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#if defined(A__ADD) || defined(A__CMN) |
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if (((int32_t)a >= 0 && (int32_t)b >= 0 && |
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(int32_t)c32 < 0) || |
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((int32_t)a < 0 && (int32_t)b < 0 && |
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(int32_t)c32 >= 0)) |
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v = 1; |
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#else |
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#if defined(A__SUB) || defined(A__RSB) || defined(A__CMP) || \ |
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defined(A__RSC) || defined(A__SBC) |
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if (((int32_t)a >= 0 && (int32_t)b < 0 && |
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(int32_t)c32 < 0) || |
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((int32_t)a < 0 && (int32_t)b >= 0 && |
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(int32_t)c32 >= 0)) |
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v = 1; |
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#endif |
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#endif |
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if (v) |
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cpu->cd.arm.flags |= ARM_F_V; |
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} |
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#endif |
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#endif /* A__S */ |
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|
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#undef VAR_A |
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#undef VAR_B |
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} |
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|
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|
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void A__NAME__eq(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (cpu->cd.arm.flags & ARM_F_Z) A__NAME(cpu, ic); } |
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void A__NAME__ne(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME(cpu, ic); } |
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void A__NAME__cs(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (cpu->cd.arm.flags & ARM_F_C) A__NAME(cpu, ic); } |
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void A__NAME__cc(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (!(cpu->cd.arm.flags & ARM_F_C)) A__NAME(cpu, ic); } |
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void A__NAME__mi(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (cpu->cd.arm.flags & ARM_F_N) A__NAME(cpu, ic); } |
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void A__NAME__pl(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (!(cpu->cd.arm.flags & ARM_F_N)) A__NAME(cpu, ic); } |
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void A__NAME__vs(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (cpu->cd.arm.flags & ARM_F_V) A__NAME(cpu, ic); } |
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void A__NAME__vc(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (!(cpu->cd.arm.flags & ARM_F_V)) A__NAME(cpu, ic); } |
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|
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#ifndef BLAHURG |
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#define BLAHURG |
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extern uint8_t condition_hi[16]; |
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extern uint8_t condition_ge[16]; |
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extern uint8_t condition_gt[16]; |
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#endif |
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|
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void A__NAME__hi(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (condition_hi[cpu->cd.arm.flags]) A__NAME(cpu, ic); } |
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void A__NAME__ls(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (!condition_hi[cpu->cd.arm.flags]) A__NAME(cpu, ic); } |
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void A__NAME__ge(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (condition_ge[cpu->cd.arm.flags]) A__NAME(cpu, ic); } |
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void A__NAME__lt(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (!condition_ge[cpu->cd.arm.flags]) A__NAME(cpu, ic); } |
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void A__NAME__gt(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (condition_gt[cpu->cd.arm.flags]) A__NAME(cpu, ic); } |
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void A__NAME__le(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (!condition_gt[cpu->cd.arm.flags]) A__NAME(cpu, ic); } |
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