src/include/cpu_avr.h

#ifndef CPU_AVR_H
#define CPU_AVR_H

/*
 *  Copyright (C) 2005  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_avr.h,v 1.10 2005/11/16 21:15:19 debug Exp $
 */

#include "misc.h"


struct cpu_family;

#define N_AVR_REGS              32

#define AVR_N_IC_ARGS                   2
#define AVR_INSTR_ALIGNMENT_SHIFT       1
#define AVR_IC_ENTRIES_SHIFT            11
#define AVR_IC_ENTRIES_PER_PAGE         (1 << AVR_IC_ENTRIES_SHIFT)
#define AVR_PC_TO_IC_ENTRY(a)           (((a)>>AVR_INSTR_ALIGNMENT_SHIFT) \
                                        & (AVR_IC_ENTRIES_PER_PAGE-1))
#define AVR_ADDR_TO_PAGENR(a)           ((a) >> (AVR_IC_ENTRIES_SHIFT \
                                        + AVR_INSTR_ALIGNMENT_SHIFT))

struct avr_instr_call {
        void    (*f)(struct cpu *, struct avr_instr_call *);
        int     len;
        size_t  arg[AVR_N_IC_ARGS];
};

/*  Translation cache struct for each physical page:  */
struct avr_tc_physpage {
        struct avr_instr_call ics[AVR_IC_ENTRIES_PER_PAGE + 1];
        uint32_t        next_ofs;       /*  or 0 for end of chain  */
        uint32_t        physaddr;
        int             flags;
};


#define AVR_N_VPH_ENTRIES       1048576

#define AVR_MAX_VPH_TLB_ENTRIES         256
struct avr_vpg_tlb_entry {
        unsigned char   valid;
        unsigned char   writeflag;
        uint32_t        vaddr_page;
        uint32_t        paddr_page;
        unsigned char   *host_page;
};


#define SREG_NAMES      "cznvshti"

#define AVR_SREG_C              0x01    /*  Carry flag  */
#define AVR_SREG_Z              0x02    /*  Zero flag  */
#define AVR_SREG_N              0x04    /*  Negative flag  */
#define AVR_SREG_V              0x08    /*  Overflow flag  */
#define AVR_SREG_S              0x10    /*  Signed test  */
#define AVR_SREG_H              0x20    /*  Half carry flag  */
#define AVR_SREG_T              0x40    /*  Transfer bit  */
#define AVR_SREG_I              0x80    /*  Interrupt enable/disable  */


struct avr_cpu {
        uint32_t        pc_mask;

        /*
         *  General Purpose Registers:
         */
        uint8_t         r[N_AVR_REGS];

        /*  Status register:  */
        uint8_t         sreg;

        /*
         *  In order to keep an accurate cycle count, this variable should be
         *  increased for those instructions that take longer than 1 cycle to
         *  execute. The total number of executed cycles is extra_cycles PLUS
         *  the number of executed instructions.
         */
        int64_t         extra_cycles;


        /*
         *  Instruction translation cache:
         */

        /*  cur_ic_page is a pointer to an array of AVR_IC_ENTRIES_PER_PAGE
            instruction call entries. next_ic points to the next such
            call to be executed.  */
        struct avr_tc_physpage  *cur_physpage;
        struct avr_instr_call   *cur_ic_page;
        struct avr_instr_call   *next_ic;

        void                    (*combination_check)(struct cpu *,
                                    struct avr_instr_call *, int low_addr);

        /*
         *  Virtual -> physical -> host address translation:
         *
         *  host_load and host_store point to arrays of AVR_N_VPH_ENTRIES
         *  pointers (to host pages); phys_addr points to an array of
         *  AVR_N_VPH_ENTRIES uint32_t.
         */

        struct avr_vpg_tlb_entry        vph_tlb_entry[AVR_MAX_VPH_TLB_ENTRIES];
        unsigned char                   *host_load[AVR_N_VPH_ENTRIES];
        unsigned char                   *host_store[AVR_N_VPH_ENTRIES];
        uint32_t                        phys_addr[AVR_N_VPH_ENTRIES];
        struct avr_tc_physpage          *phys_page[AVR_N_VPH_ENTRIES];

        uint32_t                        phystranslation[AVR_N_VPH_ENTRIES/32];
        uint8_t                         vaddr_to_tlbindex[AVR_N_VPH_ENTRIES];
};


/*  cpu_avr.c:  */
void avr_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
        unsigned char *host_page, int writeflag, uint64_t paddr_page);
void avr_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
void avr_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
int avr_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
        unsigned char *data, size_t len, int writeflag, int cache_flags);
int avr_cpu_family_init(struct cpu_family *);


#endif  /*  CPU_AVR_H  */
1	#ifndef CPU_AVR_H
2	#define CPU_AVR_H
3
4	/*
5	* Copyright (C) 2005 Anders Gavare. All rights reserved.
6	*
7	* Redistribution and use in source and binary forms, with or without
8	* modification, are permitted provided that the following conditions are met:
9	*
10	* 1. Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.
12	* 2. Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	* 3. The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.
17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28	* SUCH DAMAGE.
29	*
30	*
31	* $Id: cpu_avr.h,v 1.10 2005/11/16 21:15:19 debug Exp $
32	*/
33
34	#include "misc.h"
35
36
37	struct cpu_family;
38
39	#define N_AVR_REGS 32
40
41	#define AVR_N_IC_ARGS 2
42	#define AVR_INSTR_ALIGNMENT_SHIFT 1
43	#define AVR_IC_ENTRIES_SHIFT 11
44	#define AVR_IC_ENTRIES_PER_PAGE (1 << AVR_IC_ENTRIES_SHIFT)
45	#define AVR_PC_TO_IC_ENTRY(a) (((a)>>AVR_INSTR_ALIGNMENT_SHIFT) \
46	& (AVR_IC_ENTRIES_PER_PAGE-1))
47	#define AVR_ADDR_TO_PAGENR(a) ((a) >> (AVR_IC_ENTRIES_SHIFT \
48	+ AVR_INSTR_ALIGNMENT_SHIFT))
49
50	struct avr_instr_call {
51	void (f)(struct cpu , struct avr_instr_call *);
52	int len;
53	size_t arg[AVR_N_IC_ARGS];
54	};
55
56	/* Translation cache struct for each physical page: */
57	struct avr_tc_physpage {
58	struct avr_instr_call ics[AVR_IC_ENTRIES_PER_PAGE + 1];
59	uint32_t next_ofs; /* or 0 for end of chain */
60	uint32_t physaddr;
61	int flags;
62	};
63
64
65	#define AVR_N_VPH_ENTRIES 1048576
66
67	#define AVR_MAX_VPH_TLB_ENTRIES 256
68	struct avr_vpg_tlb_entry {
69	unsigned char valid;
70	unsigned char writeflag;
71	uint32_t vaddr_page;
72	uint32_t paddr_page;
73	unsigned char *host_page;
74	};
75
76
77	#define SREG_NAMES "cznvshti"
78
79	#define AVR_SREG_C 0x01 /* Carry flag */
80	#define AVR_SREG_Z 0x02 /* Zero flag */
81	#define AVR_SREG_N 0x04 /* Negative flag */
82	#define AVR_SREG_V 0x08 /* Overflow flag */
83	#define AVR_SREG_S 0x10 /* Signed test */
84	#define AVR_SREG_H 0x20 /* Half carry flag */
85	#define AVR_SREG_T 0x40 /* Transfer bit */
86	#define AVR_SREG_I 0x80 /* Interrupt enable/disable */
87
88
89	struct avr_cpu {
90	uint32_t pc_mask;
91
92	/*
93	* General Purpose Registers:
94	*/
95	uint8_t r[N_AVR_REGS];
96
97	/* Status register: */
98	uint8_t sreg;
99
100	/*
101	* In order to keep an accurate cycle count, this variable should be
102	* increased for those instructions that take longer than 1 cycle to
103	* execute. The total number of executed cycles is extra_cycles PLUS
104	* the number of executed instructions.
105	*/
106	int64_t extra_cycles;
107
108
109	/*
110	* Instruction translation cache:
111	*/
112
113	/* cur_ic_page is a pointer to an array of AVR_IC_ENTRIES_PER_PAGE
114	instruction call entries. next_ic points to the next such
115	call to be executed. */
116	struct avr_tc_physpage *cur_physpage;
117	struct avr_instr_call *cur_ic_page;
118	struct avr_instr_call *next_ic;
119
120	void (combination_check)(struct cpu ,
121	struct avr_instr_call *, int low_addr);
122
123	/*
124	* Virtual -> physical -> host address translation:
125	*
126	* host_load and host_store point to arrays of AVR_N_VPH_ENTRIES
127	* pointers (to host pages); phys_addr points to an array of
128	* AVR_N_VPH_ENTRIES uint32_t.
129	*/
130
131	struct avr_vpg_tlb_entry vph_tlb_entry[AVR_MAX_VPH_TLB_ENTRIES];
132	unsigned char *host_load[AVR_N_VPH_ENTRIES];
133	unsigned char *host_store[AVR_N_VPH_ENTRIES];
134	uint32_t phys_addr[AVR_N_VPH_ENTRIES];
135	struct avr_tc_physpage *phys_page[AVR_N_VPH_ENTRIES];
136
137	uint32_t phystranslation[AVR_N_VPH_ENTRIES/32];
138	uint8_t vaddr_to_tlbindex[AVR_N_VPH_ENTRIES];
139	};
140
141
142	/* cpu_avr.c: */
143	void avr_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
144	unsigned char *host_page, int writeflag, uint64_t paddr_page);
145	void avr_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
146	void avr_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
147	int avr_memory_rw(struct cpu cpu, struct memory mem, uint64_t vaddr,
148	unsigned char *data, size_t len, int writeflag, int cache_flags);
149	int avr_cpu_family_init(struct cpu_family *);
150
151
152	#endif /* CPU_AVR_H */