src/include/bus_pci.h

#ifndef BUS_PCI_H
#define BUS_PCI_H

/*
 *  Copyright (C) 2004-2005  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: bus_pci.h,v 1.23 2005/11/23 23:31:37 debug Exp $
 */

#include "misc.h"
#include "pcireg.h"

struct machine;
struct memory;

struct pci_device;

#ifndef BUS_PCI_C
struct pci_data;
#else

struct pci_data {
        /*  IRQ nr of the controller itself.  */
        int             irq_nr;

        /*
         *  Default I/O port, memory, and irq bases for PCI and legacy ISA
         *  devices, and the base address for actual (emulated) devices:
         *
         *  pci_portbase etc are what is stored in the device configuration
         *  registers. This address + pci_actual_{io,mem}_offset is where the
         *  emulated device should be registered.
         */
        uint64_t        pci_actual_io_offset;
        uint64_t        pci_actual_mem_offset;

        uint64_t        pci_portbase;
        uint64_t        pci_membase;
        int             pci_irqbase;

        uint64_t        isa_portbase;
        uint64_t        isa_membase;
        int             isa_irqbase;

        /*  Current base when allocating space for PCI devices:  */
        uint64_t        cur_pci_portbase;
        uint64_t        cur_pci_membase;

        /*  Current (indirect) addr/data access:  */
        uint32_t        pci_addr;
        int             last_was_write_ffffffff;

        struct pci_device *first_device;
};

#define PCI_CFG_MEM_SIZE        0x100

struct pci_device {
        struct pci_device       *next;
        struct pci_data         *pcibus;
        char                    *name;
        int                     bus, device, function;
        unsigned char           cfg_mem[PCI_CFG_MEM_SIZE];
        unsigned char           cfg_mem_size[PCI_CFG_MEM_SIZE];
};

#define PCIINIT(name)   void pciinit_ ## name(struct machine *machine,  \
        struct memory *mem, struct pci_device *pd)

/*
 *  Store little-endian config data in the pci_data struct's cfg_mem[]
 *  or cfg_mem_size[], respectively.
 */
#define PCI_SET_DATA(ofs,value) {                                       \
        pd->cfg_mem[(ofs)]     = (value) & 255;                         \
        pd->cfg_mem[(ofs) + 1] = ((value) >> 8) & 255;                  \
        pd->cfg_mem[(ofs) + 2] = ((value) >> 16) & 255;                 \
        pd->cfg_mem[(ofs) + 3] = ((value) >> 24) & 255;                 \
        }
#define PCI_SET_DATA_SIZE(ofs,value)    {                               \
        pd->cfg_mem_size[(ofs)]     = (value) & 255;                    \
        pd->cfg_mem_size[(ofs) + 1] = ((value) >> 8) & 255;             \
        pd->cfg_mem_size[(ofs) + 2] = ((value) >> 16) & 255;            \
        pd->cfg_mem_size[(ofs) + 3] = ((value) >> 24) & 255;            \
        }

#endif

#define BUS_PCI_ADDR    0xcf8
#define BUS_PCI_DATA    0xcfc


/*  bus_pci.c:  */
int bus_pci_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr,
        uint64_t *data, int len, int writeflag, struct pci_data *pci_data);
void bus_pci_add(struct machine *machine, struct pci_data *pci_data,
        struct memory *mem, int bus, int device, int function, char *name);
struct pci_data *bus_pci_init(int irq_nr,
        uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset,
        uint64_t pci_portbase, uint64_t pci_membase, int pci_irqbase,
        uint64_t isa_portbase, uint64_t isa_membase, int isa_irqbase);


#endif  /*  BUS_PCI_H  */
1	#ifndef BUS_PCI_H
2	#define BUS_PCI_H
3
4	/*
5	* Copyright (C) 2004-2005 Anders Gavare. All rights reserved.
6	*
7	* Redistribution and use in source and binary forms, with or without
8	* modification, are permitted provided that the following conditions are met:
9	*
10	* 1. Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.
12	* 2. Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	* 3. The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.
17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28	* SUCH DAMAGE.
29	*
30	*
31	* $Id: bus_pci.h,v 1.23 2005/11/23 23:31:37 debug Exp $
32	*/
33
34	#include "misc.h"
35	#include "pcireg.h"
36
37	struct machine;
38	struct memory;
39
40	struct pci_device;
41
42	#ifndef BUS_PCI_C
43	struct pci_data;
44	#else
45
46	struct pci_data {
47	/* IRQ nr of the controller itself. */
48	int irq_nr;
49
50	/*
51	* Default I/O port, memory, and irq bases for PCI and legacy ISA
52	* devices, and the base address for actual (emulated) devices:
53	*
54	* pci_portbase etc are what is stored in the device configuration
55	* registers. This address + pci_actual_{io,mem}_offset is where the
56	* emulated device should be registered.
57	*/
58	uint64_t pci_actual_io_offset;
59	uint64_t pci_actual_mem_offset;
60
61	uint64_t pci_portbase;
62	uint64_t pci_membase;
63	int pci_irqbase;
64
65	uint64_t isa_portbase;
66	uint64_t isa_membase;
67	int isa_irqbase;
68
69	/* Current base when allocating space for PCI devices: */
70	uint64_t cur_pci_portbase;
71	uint64_t cur_pci_membase;
72
73	/* Current (indirect) addr/data access: */
74	uint32_t pci_addr;
75	int last_was_write_ffffffff;
76
77	struct pci_device *first_device;
78	};
79
80	#define PCI_CFG_MEM_SIZE 0x100
81
82	struct pci_device {
83	struct pci_device *next;
84	struct pci_data *pcibus;
85	char *name;
86	int bus, device, function;
87	unsigned char cfg_mem[PCI_CFG_MEM_SIZE];
88	unsigned char cfg_mem_size[PCI_CFG_MEM_SIZE];
89	};
90
91	#define PCIINIT(name) void pciinit_ ## name(struct machine *machine, \
92	struct memory mem, struct pci_device pd)
93
94	/*
95	* Store little-endian config data in the pci_data struct's cfg_mem[]
96	* or cfg_mem_size[], respectively.
97	*/
98	#define PCI_SET_DATA(ofs,value) { \
99	pd->cfg_mem[(ofs)] = (value) & 255; \
100	pd->cfg_mem[(ofs) + 1] = ((value) >> 8) & 255; \
101	pd->cfg_mem[(ofs) + 2] = ((value) >> 16) & 255; \
102	pd->cfg_mem[(ofs) + 3] = ((value) >> 24) & 255; \
103	}
104	#define PCI_SET_DATA_SIZE(ofs,value) { \
105	pd->cfg_mem_size[(ofs)] = (value) & 255; \
106	pd->cfg_mem_size[(ofs) + 1] = ((value) >> 8) & 255; \
107	pd->cfg_mem_size[(ofs) + 2] = ((value) >> 16) & 255; \
108	pd->cfg_mem_size[(ofs) + 3] = ((value) >> 24) & 255; \
109	}
110
111	#endif
112
113	#define BUS_PCI_ADDR 0xcf8
114	#define BUS_PCI_DATA 0xcfc
115
116
117	/* bus_pci.c: */
118	int bus_pci_access(struct cpu cpu, struct memory mem, uint64_t relative_addr,
119	uint64_t data, int len, int writeflag, struct pci_data pci_data);
120	void bus_pci_add(struct machine machine, struct pci_data pci_data,
121	struct memory mem, int bus, int device, int function, char name);
122	struct pci_data *bus_pci_init(int irq_nr,
123	uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset,
124	uint64_t pci_portbase, uint64_t pci_membase, int pci_irqbase,
125	uint64_t isa_portbase, uint64_t isa_membase, int isa_irqbase);
126
127
128	#endif /* BUS_PCI_H */