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dpavlin |
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/* gxemul: $Id: aureg.h,v 1.2 2005/03/05 12:34:02 debug Exp $ */ |
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/* $NetBSD: aureg.h,v 1.4 2003/11/08 05:49:08 simonb Exp $ */ |
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#ifndef AUREG_H |
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#define AUREG_H |
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/* |
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* Copyright 2002 Wasabi Systems, Inc. |
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* All rights reserved. |
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* |
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* Written by Simon Burge for Wasabi Systems, Inc. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed for the NetBSD Project by |
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* Wasabi Systems, Inc. |
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse |
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* or promote products derived from this software without specific prior |
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* written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC |
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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/* ********************************************************************* |
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* Naming schemes for constants in these files: |
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* |
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* M_xxx MASK constant (identifies bits in a register). |
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* For multi-bit fields, all bits in the field will |
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* be set. |
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* |
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* K_xxx "Code" constant (value for data in a multi-bit |
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* field). The value is right justified. |
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* |
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* V_xxx "Value" constant. This is the same as the |
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* corresponding "K_xxx" constant, except it is |
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* shifted to the correct position in the register. |
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* |
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* S_xxx SHIFT constant. This is the number of bits that |
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* a field value (code) needs to be shifted |
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* (towards the left) to put the value in the right |
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* position for the register. |
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* |
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* A_xxx ADDRESS constant. This will be a physical |
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* address. Use the MIPS_PHYS_TO_KSEG1 macro to |
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* generate a K1SEG address. |
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* |
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* R_xxx RELATIVE offset constant. This is an offset from |
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* an A_xxx constant (usually the first register in |
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* a group). |
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* |
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* G_xxx(X) GET value. This macro obtains a multi-bit field |
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* from a register, masks it, and shifts it to |
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* the bottom of the register (retrieving a K_xxx |
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* value, for example). |
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* |
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* V_xxx(X) VALUE. This macro computes the value of a |
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* K_xxx constant shifted to the correct position |
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* in the register. |
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********************************************************************* */ |
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#if !defined(__ASSEMBLER__) |
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#define _MAKE64(x) ((uint64_t)(x)) |
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#define _MAKE32(x) ((uint32_t)(x)) |
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#else |
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#define _MAKE64(x) (x) |
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#define _MAKE32(x) (x) |
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#endif |
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/* Make a mask for 1 bit at position 'n' */ |
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#define _MAKEMASK1_64(n) (_MAKE64(1) << _MAKE64(n)) |
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#define _MAKEMASK1_32(n) (_MAKE32(1) << _MAKE32(n)) |
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/* Make a mask for 'v' bits at position 'n' */ |
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#define _MAKEMASK_64(v,n) (_MAKE64((_MAKE64(1)<<(v))-1) << _MAKE64(n)) |
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#define _MAKEMASK_32(v,n) (_MAKE32((_MAKE32(1)<<(v))-1) << _MAKE32(n)) |
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/* Make a value at 'v' at bit position 'n' */ |
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#define _MAKEVALUE_64(v,n) (_MAKE64(v) << _MAKE64(n)) |
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#define _MAKEVALUE_32(v,n) (_MAKE32(v) << _MAKE32(n)) |
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#define _GETVALUE_64(v,n,m) ((_MAKE64(v) & _MAKE64(m)) >> _MAKE64(n)) |
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#define _GETVALUE_32(v,n,m) ((_MAKE32(v) & _MAKE32(m)) >> _MAKE32(n)) |
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/************************************************************************/ |
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/******************** AC97 Controller registers *********************/ |
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/************************************************************************/ |
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#define AC97_BASE 0x10000000 |
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#define AC97_CONFIG 0x00 |
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#define M_AC97CFG_RS _MAKEMASK1_32(0) |
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#define M_AC97CFG_SN _MAKEMASK1_32(1) |
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#define M_AC97CFG_SG _MAKEMASK1_32(2) |
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#define S_AC97CFG_XS _MAKE32(12) |
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#define M_AC97CFG_XS _MAKEMASK_32(10) |
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#define V_AC97CFG_XS(x) _MAKEVALUE_32(x, S_AC97CFG_XS) |
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#define G_AC97CFG_XS(x) _GETVALUE_32(x, S_AC97CFG_XS, M_AC97CFG_XS) |
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#define S_AC97CFG_RC _MAKE32(12) |
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#define M_AC97CFG_RC _MAKEMASK_32(10) |
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#define V_AC97CFG_RC(x) _MAKEVALUE_32(x, S_AC97CFG_RC) |
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#define G_AC97CFG_RC(x) _GETVALUE_32(x, S_AC97CFG_RC, M_AC97CFG_RC) |
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#define AC97_STATUS 0x04 |
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#define M_AC97STAT_RF _MAKEMASK1_32(0) |
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#define M_AC97STAT_RE _MAKEMASK1_32(1) |
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#define M_AC97STAT_TF _MAKEMASK1_32(3) |
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#define M_AC97STAT_TE _MAKEMASK1_32(4) |
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#define M_AC97STAT_CP _MAKEMASK1_32(6) |
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#define M_AC97STAT_RD _MAKEMASK1_32(7) |
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#define M_AC97STAT_RO _MAKEMASK1_32(8) |
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#define M_AC97STAT_RU _MAKEMASK1_32(9) |
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#define M_AC97STAT_XO _MAKEMASK1_32(10) |
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#define M_AC97STAT_XU _MAKEMASK1_32(11) |
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#define AC97_DATA 0x08 |
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#define S_AC97DATA_DATA _MAKE32(0) |
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#define M_AC97DATA_DATA _MAKEMASK_32(16) |
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#define V_AC97DATA_DATA(x) _MAKEVALUE_32(x, S_AC97DATA_DATA) |
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#define G_AC97DATA_DATA(x) _GETVALUE_32(x, S_AC97DATA_DATA, M_AC97DATA_DATA) |
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#define AC97_COMMAND 0x0c |
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#define S_AC97CMD_INDEX _MAKE32(0) |
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#define M_AC97CMD_INDEX _MAKEMASK_32(7) |
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#define V_AC97CMD_INDEX(x) _MAKEVALUE_32(x, S_AC97CMD_INDEX) |
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#define G_AC97CMD_INDEX(x) _GETVALUE_32(x, S_AC97CMD_INDEX, M_AC97CMD_INDEX) |
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#define M_AC97CMD_RW _MAKEMASK1_32(7) |
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#define S_AC97CMD_DATA _MAKE32(16) |
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#define M_AC97CMD_DATA _MAKEMASK_32(16) |
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#define V_AC97CMD_DATA(x) _MAKEVALUE_32(x, S_AC97CMD_DATA) |
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#define G_AC97CMD_DATA(x) _GETVALUE_32(x, S_AC97CMD_DATA, M_AC97CMD_DATA) |
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#define AC97_COMMAND_RESPONSE 0x0c |
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#define S_AC97CMDRESP_DATA _MAKE32(0) |
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#define M_AC97CMDRESP_DATA _MAKEMASK_32(16) |
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#define V_AC97CMDRESP_DATA(x) _MAKEVALUE_32(x, S_AC97CMDRESP_DATA) |
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#define G_AC97CMDRESP_DATA(x) _GETVALUE_32(x, S_AC97CMDRESP_DATA, M_AC97CMDRESP_DATA) |
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#define AC97_ENABLE 0x10 |
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#define M_AC97EN_CE _MAKEMASK1_32(0) |
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#define M_AC97EN_D _MAKEMASK1_32(1) |
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#define AC97_SIZE 0x14 /* size of register set */ |
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/************************************************************************/ |
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/*********************** USB Host registers *************************/ |
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/************************************************************************/ |
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#define USBH_BASE 0x10100000 |
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#define USBH_ENABLE 0x7fffc |
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#define UE_RD 0x00000010 /* reset done */ |
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#define UE_CE 0x00000008 /* clock enable */ |
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#define UE_E 0x00000004 /* enable */ |
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#define UE_C 0x00000002 /* coherent */ |
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#define UE_BE 0x00000001 /* big-endian */ |
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#define USBH_SIZE 0x80000 /* size of register set */ |
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/************************************************************************/ |
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/********************** USB Device registers ************************/ |
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/************************************************************************/ |
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#define USBD_BASE 0x10200000 |
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/************************************************************************/ |
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/************************* IRDA registers ***************************/ |
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/************************************************************************/ |
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#define IRDA_BASE 0x10300000 |
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/************************************************************************/ |
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/****************** Interrupt Controller registers ******************/ |
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/************************************************************************/ |
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#define IC0_BASE 0x10400000 |
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#define IC1_BASE 0x11800000 |
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/* |
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* The *_READ registers read the current value of the register |
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* The *_SET registers set to 1 all bits that are written 1 |
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* The *_CLEAR registers clear to zero all bits that are written as 1 |
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*/ |
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#define IC_CONFIG0_READ 0x40 /* See table below */ |
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#define IC_CONFIG0_SET 0x40 |
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#define IC_CONFIG0_CLEAR 0x44 |
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#define IC_CONFIG1_READ 0x48 /* See table below */ |
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#define IC_CONFIG1_SET 0x48 |
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#define IC_CONFIG1_CLEAR 0x4c |
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#define IC_CONFIG2_READ 0x50 /* See table below */ |
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#define IC_CONFIG2_SET 0x50 |
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#define IC_CONFIG2_CLEAR 0x54 |
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#define IC_REQUEST0_INT 0x54 /* Show active interrupts on request 0 */ |
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#define IC_SOURCE_READ 0x58 /* Interrupt source */ |
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#define IC_SOURCE_SET 0x58 /* 0 - test bit used as source */ |
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#define IC_SOURCE_CLEAR 0x5c /* 1 - peripheral/GPIO used as source */ |
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#define IC_REQUEST1_INT 0x5c /* Show active interrupts on request 1 */ |
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#define IC_ASSIGN_REQUEST_READ 0x60 /* Assigns the interrupt to one of the */ |
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#define IC_ASSIGN_REQUEST_SET 0x60 /* CPU requests (0 - assign to request 1, */ |
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#define IC_ASSIGN_REQUEST_CLEAR 0x64 /* 1 - assign to request 0) */ |
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#define IC_WAKEUP_READ 0x68 /* Controls whether the interrupt can */ |
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#define IC_WAKEUP_SET 0x68 /* cause a wakeup from IDLE */ |
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#define IC_WAKEUP_CLEAR 0x6c |
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#define IC_MASK_READ 0x70 /* Enables/Disables the interrupt */ |
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#define IC_MASK_SET 0x70 |
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#define IC_MASK_CLEAR 0x74 |
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#define IC_RISING_EDGE_DETECT 0x78 /* Check/clear rising edge interrupts */ |
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#define IC_RISING_EDGE_DETECT_CLEAR 0x78 |
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#define IC_FAILLING_EDGE_DETECT 0x7c /* Check/clear falling edge interrupts */ |
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#define IC_FAILLING_EDGE_DETECT_CLEAR 0x7c |
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#define IC_TEST_BIT 0x80 /* single bit source select testing register */ |
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/* |
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* Interrupt Configuration Register Functions |
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* |
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* Cfg2[n] Cfg1[n] Cfg0[n] Function |
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* 0 0 0 Interrupts Disabled |
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* 0 0 1 Rising Edge Enabled |
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* 0 1 0 Falling Edge Enabled |
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* 0 1 1 Rising and Falling Edge Enabled |
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* 1 0 0 Interrupts Disabled |
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* 1 0 1 High Level Enabled |
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* 1 1 0 Low Level Enabled |
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* 1 1 1 Both Levels and Both Edges Enabled |
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*/ |
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/************************************************************************/ |
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/********************** Ethernet MAC registers **********************/ |
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/************************************************************************/ |
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#define MAC0_BASE 0x10500000 |
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#define MAC1_BASE 0x10510000 |
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#define MACx_SIZE 0x28 |
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#define AU1500_MAC0_BASE 0x11500000 /* Grr, difference on Au1500 */ |
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#define AU1500_MAC1_BASE 0x11510000 /* Grr, difference on Au1500 */ |
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#if 0 |
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#define MAC_CONTROL 0x00 /* operation mode and address filter */ |
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#define MC_RA 0x80000000 /* Receive All */ |
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#define MC_EM 0x40000000 /* Endian Mode - data buffer is big endian */ |
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#define MC_DRO 0x00800000 /* Disable Receive Own */ |
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#define MC_LM_MASK 0x00600000 /* Loopback Operating Mode - mask */ |
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#define MC_LM_NORMAL 0x00600000 |
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#define MC_LM_INTERNAL 0x00400000 |
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#define MC_LM_EXTERNAL 0x00200000 |
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#define MC_F 0x00100000 /* Full duplex mode */ |
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#define MC_PM 0x00080000 /* Pall all Multicast */ |
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#define MC_PR 0x00040000 /* Promiscious Mode */ |
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#define MC_IF 0x00020000 /* Inverse Filtering */ |
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#define MC_PB 0x00010000 /* Pass Bad frames */ |
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#define MC_HO 0x00008000 /* Hash Only filtering mode */ |
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#define MC_HP 0x00002000 /* Hash/Perfect filtering mode */ |
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#define MC_LC 0x00001000 /* Late Collision control */ |
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#define MC_DB 0x00000800 /* Disable Broadcast frames */ |
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#define MC_DR 0x00000400 /* Disable Retry */ |
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#define MC_AP 0x00000100 /* Automatic Pad stripping */ |
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#define MC_BL_MASK 0x000000c0 /* Backoff Limit mask */ |
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#define MC_BL_SHIFT 6 |
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#define MC_DC 0x00000020 /* Deferral Check */ |
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#define MC_TE 0x00000008 /* Transmitter Enable */ |
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#define MC_RE 0x00000004 /* Receiver Enable */ |
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#define MAC_ADDRESS_HIGH 0x04 /* high 16 bits of the MAC address */ |
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#define MAC_ADDRESS_LOW 0x08 /* lower 32 bits of the MAC address */ |
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#define MAC_MCAST_HASH_HIGH 0x0c /* high 16 bits of mcat hash address */ |
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#define MAC_MCAST_HASH_LOW 0x10 /* low 32 bits of mcat hash address */ |
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#define MAC_MII_CONTROL 0x14 /* control of PHY management interface */ |
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#define MMC_PHY_ADDR_MASK 0x0000f800 /* PHY Address mask */ |
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#define MMC_PHY_ADDR_SHIFT 11 |
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#define MMC_MIIREG_MASK 0x000007c0 /* MII Register mask */ |
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#define MMC_MIIREG_SHIFT 6 |
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#define MMC_MW 0x00000002 /* MII Write */ |
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#define MMC_MB 0x00000001 /* MII Busy */ |
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#define MAC_MII_DATA 0x18 /* data to/from PHY */ |
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#define MAC_FLOW_CONTROL 0x1c /* frame generation control */ |
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#define MFC_PT_MASK 0xffff0000 /* Pause Time mask */ |
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#define MFC_PT_SHIFT 16 |
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#define MFC_PC 0x00000004 /* Pass Control frame */ |
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#define MFC_FE 0x00000002 /* Flow Control enable */ |
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#define MFC_FB 0x00000001 /* Flow control Busy */ |
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#define MAC_VLAN1_TAG 0x20 /* VLAN1 tag */ |
| 317 |
|
|
#define MAC_VLAN2_TAG 0x24 /* VLAN2 tag */ |
| 318 |
|
|
#endif |
| 319 |
|
|
|
| 320 |
|
|
#define MAC0_ENABLE 0x10520000 |
| 321 |
|
|
#define MAC1_ENABLE 0x10520004 |
| 322 |
|
|
#define MACENx_SIZE 0x04 |
| 323 |
|
|
|
| 324 |
|
|
#define AU1500_MAC0_ENABLE 0x11520000 /* Grr, difference on Au1500 */ |
| 325 |
|
|
#define AU1500_MAC1_ENABLE 0x11520004 /* Grr, difference on Au1500 */ |
| 326 |
|
|
|
| 327 |
|
|
#if 0 |
| 328 |
|
|
#define ME_DR 0x40 /* DMA reset */ |
| 329 |
|
|
#define ME_R2 0x20 /* Reset2 */ |
| 330 |
|
|
#define ME_R1 0x10 /* Reset1 */ |
| 331 |
|
|
#define ME_C 0x08 /* Cacheable */ |
| 332 |
|
|
#define ME_TS 0x04 /* Toss */ |
| 333 |
|
|
#define ME_R0 0x02 /* Reset0 */ |
| 334 |
|
|
#define ME_EN 0x01 /* Clock Enable */ |
| 335 |
|
|
#endif |
| 336 |
|
|
|
| 337 |
|
|
#define MAC0_DMA_BASE 0x14004000 |
| 338 |
|
|
#define MAC1_DMA_BASE 0x14004200 |
| 339 |
|
|
#define MACx_DMA_SIZE 0x140 |
| 340 |
|
|
#if 0 |
| 341 |
|
|
#define MAC_TXDMA 0x000 |
| 342 |
|
|
#define MAC_RXDMA 0x100 |
| 343 |
|
|
#define MAC_TXQLEN 4 |
| 344 |
|
|
#define MAC_RXQLEN 4 |
| 345 |
|
|
|
| 346 |
|
|
/* MAC Transmit Status registers */ |
| 347 |
|
|
#define MTS_PR 0x80000000 /* Packet Retry */ |
| 348 |
|
|
#define MTS_HB 0x00004000 /* ?!?? */ |
| 349 |
|
|
#define MTS_CC_MASK 0x00003c00 /* Collision Count mask */ |
| 350 |
|
|
#define MTS_CC_SHIFT 10 |
| 351 |
|
|
#define MTS_LO 0x00000200 /* Late collision Observed */ |
| 352 |
|
|
#define MTS_DF 0x00000100 /* Deferred */ |
| 353 |
|
|
#define MTS_UR 0x00000080 /* Underrun */ |
| 354 |
|
|
#define MTS_EC 0x00000040 /* Excessive Collisions */ |
| 355 |
|
|
#define MTS_LC 0x00000020 /* Late Collision */ |
| 356 |
|
|
#define MTS_ED 0x00000010 /* Excessive Deferral */ |
| 357 |
|
|
#define MFS_LS 0x00000008 /* LoSs of carrier */ |
| 358 |
|
|
#define MFS_NC 0x00000004 /* No Carrier */ |
| 359 |
|
|
#define MFS_JT 0x00000002 /* Jabber Timeout */ |
| 360 |
|
|
#define MFS_FA 0x00000001 /* Frame Aborted */ |
| 361 |
|
|
|
| 362 |
|
|
/* MAC Transmit Buffer Address/Enable registers */ |
| 363 |
|
|
#define MTBAE_ADDR_MASK 0xffffffe0 /* Buffer address */ |
| 364 |
|
|
#define MTBAE_CB_MASK 0x0000000c /* Current (DMA) Buffer */ |
| 365 |
|
|
#define MTBAE_CB_SHIFT 2 |
| 366 |
|
|
#define MTBAE_DONE 0x00000002 /* transation DONE */ |
| 367 |
|
|
#define MTBAE_EN 0x00000001 /* MAC DMA Enable */ |
| 368 |
|
|
|
| 369 |
|
|
/* MAC Transmit Buffer Length registers */ |
| 370 |
|
|
#define MTBL_LEN_MASK 0x000007ff /* buffer LENgth */ |
| 371 |
|
|
#define MTBL_LEN_SHIFT 0 |
| 372 |
|
|
|
| 373 |
|
|
/* MAC Receive Status registers */ |
| 374 |
|
|
#define MRS_MI 0x80000000 /* MIssed frame */ |
| 375 |
|
|
#define MRS_PF 0x40000000 /* Packet Filter */ |
| 376 |
|
|
#define MRS_FF 0x20000000 /* Filtering Fail */ |
| 377 |
|
|
#define MRS_BF 0x10000000 /* Broadcast Frame */ |
| 378 |
|
|
#define MRS_MF 0x08000000 /* Multicast Frame */ |
| 379 |
|
|
#define MRS_UC 0x04000000 /* Unsupported Control frame */ |
| 380 |
|
|
#define MRS_CF 0x02000000 /* Control Frame */ |
| 381 |
|
|
#define MRS_LE 0x01000000 /* Length Error */ |
| 382 |
|
|
#define MRS_V2 0x00800000 /* Vlan2 ID */ |
| 383 |
|
|
#define MRS_V1 0x00400000 /* Vlan1 ID */ |
| 384 |
|
|
#define MRS_CR 0x00200000 /* CRC error */ |
| 385 |
|
|
#define MRS_DB 0x00100000 /* Dribbling Bit */ |
| 386 |
|
|
#define MRS_ME 0x00080000 /* MII Error */ |
| 387 |
|
|
#define MRS_FT 0x00040000 /* Frame Type */ |
| 388 |
|
|
#define MRS_CS 0x00020000 /* Collision Seen */ |
| 389 |
|
|
#define MRS_FL 0x00010000 /* Frame too Long */ |
| 390 |
|
|
#define MRS_RF 0x00008000 /* Runt Frame */ |
| 391 |
|
|
#define MRS_WT 0x00004000 /* Watchdog Timeout */ |
| 392 |
|
|
#define MRS_L_MASK 0x00003fff /* frame Length mask*/ |
| 393 |
|
|
#define MRS_L_SHIFT 0 |
| 394 |
|
|
|
| 395 |
|
|
/* MAC Receive Buffer Address/Enable registers */ |
| 396 |
|
|
#define MRBAE_ADDR_MASK 0xffffffe0 /* Buffer address */ |
| 397 |
|
|
#define MRBAE_CB_MASK 0x0000000c /* Current (DMA) Buffer */ |
| 398 |
|
|
#define MRBAE_CB_SHIFT 2 |
| 399 |
|
|
#define MRBAE_DN 0x00000002 /* transation DoNe */ |
| 400 |
|
|
#define MRBAE_EN 0x00000001 /* MAC DMA Enable */ |
| 401 |
|
|
#endif |
| 402 |
|
|
|
| 403 |
|
|
/************************************************************************/ |
| 404 |
|
|
/******************** Secure Digital registers **********************/ |
| 405 |
|
|
/************************************************************************/ |
| 406 |
|
|
#define SD0_BASE 0x10600000 |
| 407 |
|
|
#define SD1_BASE 0x10680000 |
| 408 |
|
|
|
| 409 |
|
|
/************************************************************************/ |
| 410 |
|
|
/************************* I^2S registers ***************************/ |
| 411 |
|
|
/************************************************************************/ |
| 412 |
|
|
#define I2S_BASE 0x11000000 |
| 413 |
|
|
|
| 414 |
|
|
/************************************************************************/ |
| 415 |
|
|
/************************** UART registers **************************/ |
| 416 |
|
|
/************************************************************************/ |
| 417 |
|
|
|
| 418 |
|
|
#define UART0_BASE 0x11100000 |
| 419 |
|
|
#define UART1_BASE 0x11200000 |
| 420 |
|
|
#define UART2_BASE 0x11300000 |
| 421 |
|
|
#define UART3_BASE 0x11400000 |
| 422 |
|
|
|
| 423 |
|
|
#define UART_RXDATA 0x000 /* Received Data FIFO (R) */ |
| 424 |
|
|
#define UART_TXDATA 0x004 /* Transmit Data FIFO (W) */ |
| 425 |
|
|
#define UART_INTERRUPT_ENABLE 0x008 /* Interrupt Enable Register (R/W) */ |
| 426 |
|
|
#define UIE_MIE 0x8 /* Modem Status Interrupt enable */ |
| 427 |
|
|
#define UIE_LIE 0x4 /* Line Status Interrupt enable */ |
| 428 |
|
|
#define UIE_TIE 0x2 /* Transmit Interrupt Enable */ |
| 429 |
|
|
#define UIE_RIE 0x1 /* Receive Interrupt Enable */ |
| 430 |
|
|
#define UART_INTERRUPT_CAUSE 0x00c /* Pending Interrupt Cause Register (R) */ |
| 431 |
|
|
#define UIC_IID_MASK 0xe /* mask for Interrupt IDentifier */ |
| 432 |
|
|
#define UIC_IID_MS 0x0 /* Modem Status */ |
| 433 |
|
|
#define UIC_IID_TBA 0x2 /* Transmit Buffer Available */ |
| 434 |
|
|
#define UIC_IID_RDA 0x4 /* Receive Data Available */ |
| 435 |
|
|
#define UIC_IID_RLS 0x6 /* Receive Line Status */ |
| 436 |
|
|
#define UIC_IID_CTO 0xc /* Character Time Out */ |
| 437 |
|
|
#define UIC_IP 0x1 /* XXX-no?-XXX Interrupt Pending */ |
| 438 |
|
|
#define UART_FIFO_CONTROL 0x010 /* FIFO Control Register (W) */ |
| 439 |
|
|
#define UFC_RFT_0 0x00 /* Receiver FIFO Threshold of 0 chars */ |
| 440 |
|
|
#define UFC_RFT_4 0x40 /* Receiver FIFO Threshold of 4 chars */ |
| 441 |
|
|
#define UFC_RFT_8 0x80 /* Receiver FIFO Threshold of 8 chars */ |
| 442 |
|
|
#define UFC_RFT_12 0xc0 /* Receiver FIFO Threshold of 12 chars */ |
| 443 |
|
|
#define UFC_TFT_0 0x00 /* Transmit FIFO Threshold of 0 chars */ |
| 444 |
|
|
#define UFC_TFT_4 0x10 /* Transmit FIFO Threshold of 4 chars */ |
| 445 |
|
|
#define UFC_TFT_8 0x20 /* Transmit FIFO Threshold of 8 chars */ |
| 446 |
|
|
#define UFC_TFT_12 0x30 /* Transmit FIFO Threshold of 12 chars */ |
| 447 |
|
|
#define UFC_MS 0x08 /* Mode Select */ |
| 448 |
|
|
#define UFC_TR 0x04 /* Transmitter Reset */ |
| 449 |
|
|
#define UFC_RR 0x02 /* Receiver Reset */ |
| 450 |
|
|
#define UFC_FE 0x01 /* FIFO Enable */ |
| 451 |
|
|
#define UART_LINE_CONTROL 0x014 /* Line Control Register (R/W) */ |
| 452 |
|
|
#define ULC_SB 0x40 /* Send Break */ |
| 453 |
|
|
#define ULC_PAR_MASK 0x30 /* mask for PARity select */ |
| 454 |
|
|
#define ULC_PAR_ODD 0x00 /* odd parity */ |
| 455 |
|
|
#define ULC_PAR_EVEN 0x10 /* even parity */ |
| 456 |
|
|
#define ULC_PAR_MARK 0x20 /* mark parity */ |
| 457 |
|
|
#define ULC_PAR_ZERO 0x30 /* zero parity */ |
| 458 |
|
|
#define ULC_PE 0x08 /* Parity Enable */ |
| 459 |
|
|
#define ULC_ST 0x04 /* 1.5 or 2 stop bits */ |
| 460 |
|
|
#define ULC_WLS_MASK 0x03 /* mask for Word Length Select */ |
| 461 |
|
|
#define ULC_WLS_5 0x00 /* 5 bits per serial word */ |
| 462 |
|
|
#define ULC_WLS_6 0x01 /* 6 bits */ |
| 463 |
|
|
#define ULC_WLS_7 0x02 /* 7 bits */ |
| 464 |
|
|
#define ULC_WLS_8 0x03 /* 8 bits */ |
| 465 |
|
|
#define UART_MODEM_CONTROL 0x018 /* Modem Line Control Register (UART 4 only) (R/W) */ |
| 466 |
|
|
#define UMC_LB 0x10 /* Loop Back */ |
| 467 |
|
|
#define UMC_X2 0x08 /* eXternal line 2 state */ |
| 468 |
|
|
#define UMC_X1 0x04 /* eXternal line 1 state */ |
| 469 |
|
|
#define UMC_RT 0x02 /* Request To send */ |
| 470 |
|
|
#define UMC_DT 0x01 /* Data Terminal ready */ |
| 471 |
|
|
#define UART_LINE_STATUS 0x01c /* Line Status Register (R/W) */ |
| 472 |
|
|
#define ULS_RF 0x80 /* Receiver FIFO contains error */ |
| 473 |
|
|
#define ULS_TE 0x40 /* Transmit shift register Empty */ |
| 474 |
|
|
#define ULS_TFE 0x20 /* Transmit FIFO Empty */ |
| 475 |
|
|
#define ULS_BI 0x10 /* Break Indication */ |
| 476 |
|
|
#define ULS_FE 0x08 /* Framing Error */ |
| 477 |
|
|
#define ULS_PE 0x04 /* Parity Error */ |
| 478 |
|
|
#define ULS_OE 0x02 /* Overrun Error */ |
| 479 |
|
|
#define ULS_DR 0x01 /* Data Ready */ |
| 480 |
|
|
#define ULS_RCV_MASK 0x1f /* mask for incoming data or error */ |
| 481 |
|
|
#define UART_MODEM_STATUS 0x020 /* Modem Line Status Register (UART 4 only) (R/W) */ |
| 482 |
|
|
#define UMS_CD 0x80 /* data Carrier Detect */ |
| 483 |
|
|
#define UMS_RI 0x40 /* Ring Indication */ |
| 484 |
|
|
#define UMS_DS 0x20 /* Data Set ready */ |
| 485 |
|
|
#define UMS_CT 0x10 /* Clear To send */ |
| 486 |
|
|
#define UMS_DD 0x08 /* Delta DCD */ |
| 487 |
|
|
#define UMS_TRI 0x04 /* Terminate Ring Indication */ |
| 488 |
|
|
#define UMS_DR 0x02 /* Delta DSR */ |
| 489 |
|
|
#define UMS_DC 0x01 /* Delta CTS */ |
| 490 |
|
|
#define UART_CLOCK_DIVIDER 0x028 /* Baud Rate Clock Divider (16bit) */ |
| 491 |
|
|
#define UART_MODULE_CONTROL 0x100 /* Module Control Register */ |
| 492 |
|
|
#define UMC_CE 0x2 /* Module Clock Enable */ |
| 493 |
|
|
#define UMC_ME 0x1 /* Module Enable */ |
| 494 |
|
|
|
| 495 |
|
|
#define UART_SIZE 0x104 |
| 496 |
|
|
|
| 497 |
|
|
/************************************************************************/ |
| 498 |
|
|
/************************* SSI registers ****************************/ |
| 499 |
|
|
/************************************************************************/ |
| 500 |
|
|
#define SSI0_BASE 0x11600000 |
| 501 |
|
|
#define SSI1_BASE 0x11680000 |
| 502 |
|
|
|
| 503 |
|
|
/************************************************************************/ |
| 504 |
|
|
/************************ GPIO2 registers ***************************/ |
| 505 |
|
|
/************************************************************************/ |
| 506 |
|
|
#define GPIO2_BASE 0x11700000 |
| 507 |
|
|
|
| 508 |
|
|
/************************************************************************/ |
| 509 |
|
|
/****************** Programmable Counter registers ******************/ |
| 510 |
|
|
/************************************************************************/ |
| 511 |
|
|
|
| 512 |
|
|
#define SYS_BASE 0x11900000 |
| 513 |
|
|
|
| 514 |
|
|
#define PC_BASE SYS_BASE |
| 515 |
|
|
|
| 516 |
|
|
#define PC_TRIM0 0x00 /* PC0 Divide (16 bits) */ |
| 517 |
|
|
#define PC_COUNTER_WRITE0 0x04 /* set PC0 */ |
| 518 |
|
|
#define PC_MATCH0_0 0x08 /* match counter & interrupt */ |
| 519 |
|
|
#define PC_MATCH1_0 0x0c /* match counter & interrupt */ |
| 520 |
|
|
#define PC_MATCH2_0 0x10 /* match counter & interrupt */ |
| 521 |
|
|
#define PC_COUNTER_CONTROL 0x14 /* Programmable Counter Control */ |
| 522 |
|
|
#define CC_E1S 0x00800000 /* Enable PC1 write status */ |
| 523 |
|
|
#define CC_T1S 0x00100000 /* Trim PC1 write status */ |
| 524 |
|
|
#define CC_M21 0x00080000 /* Match 2 of PC1 write status */ |
| 525 |
|
|
#define CC_M11 0x00040000 /* Match 1 of PC1 write status */ |
| 526 |
|
|
#define CC_M01 0x00020000 /* Match 0 of PC1 write status */ |
| 527 |
|
|
#define CC_C1S 0x00010000 /* PC1 write status */ |
| 528 |
|
|
#define CC_BP 0x00004000 /* Bypass OSC (use GPIO1) */ |
| 529 |
|
|
#define CC_EN1 0x00002000 /* Enable PC1 */ |
| 530 |
|
|
#define CC_BT1 0x00001000 /* Bypass Trim on PC1 */ |
| 531 |
|
|
#define CC_EN0 0x00000800 /* Enable PC0 */ |
| 532 |
|
|
#define CC_BT0 0x00000400 /* Bypass Trim on PC0 */ |
| 533 |
|
|
#define CC_EO 0x00000100 /* Enable Oscillator */ |
| 534 |
|
|
#define CC_E0S 0x00000080 /* Enable PC0 write status */ |
| 535 |
|
|
#define CC_32S 0x00000020 /* 32.768kHz OSC status */ |
| 536 |
|
|
#define CC_T0S 0x00000010 /* Trim PC0 write status */ |
| 537 |
|
|
#define CC_M20 0x00000008 /* Match 2 of PC0 write status */ |
| 538 |
|
|
#define CC_M10 0x00000004 /* Match 1 of PC0 write status */ |
| 539 |
|
|
#define CC_M00 0x00000002 /* Match 0 of PC0 write status */ |
| 540 |
|
|
#define CC_C0S 0x00000001 /* PC0 write status */ |
| 541 |
|
|
#define PC_COUNTER_READ_0 0x40 /* get PC0 */ |
| 542 |
|
|
#define PC_TRIM1 0x44 /* PC1 Divide (16 bits) */ |
| 543 |
|
|
#define PC_COUNTER_WRITE1 0x48 /* set PC1 */ |
| 544 |
|
|
#define PC_MATCH0_1 0x4c /* match counter & interrupt */ |
| 545 |
|
|
#define PC_MATCH1_1 0x50 /* match counter & interrupt */ |
| 546 |
|
|
#define PC_MATCH2_1 0x54 /* match counter & interrupt */ |
| 547 |
|
|
#define PC_COUNTER_READ_1 0x58 /* get PC1 */ |
| 548 |
|
|
|
| 549 |
|
|
#define PC_SIZE 0x5c /* size of register set */ |
| 550 |
|
|
#define PC_RATE 32768 /* counter rate is 32.768kHz */ |
| 551 |
|
|
|
| 552 |
|
|
/************************************************************************/ |
| 553 |
|
|
/******************* Frequency Generator Registers ******************/ |
| 554 |
|
|
/************************************************************************/ |
| 555 |
|
|
|
| 556 |
|
|
#define SYS_FREQCTRL0 (SYS_BASE + 0x20) |
| 557 |
|
|
#define SFC_FRDIV2(f) (f<<22) /* 29:22. Freq Divider 2 */ |
| 558 |
|
|
#define SFC_FE2 (1<<21) /* Freq generator output enable 2 */ |
| 559 |
|
|
#define SFC_FS2 (1<<20) /* Freq generator source 2 */ |
| 560 |
|
|
#define SFC_FRDIV1(f) (f<<12) /* 19:12. Freq Divider 1 */ |
| 561 |
|
|
#define SFC_FE1 (1<<11) /* Freq generator output enable 1 */ |
| 562 |
|
|
#define SFC_FS1 (1<<10) /* Freq generator source 1 */ |
| 563 |
|
|
#define SFC_FRDIV0(f) (f<<2) /* 9:2. Freq Divider 0 */ |
| 564 |
|
|
#define SFC_FE0 2 /* Freq generator output enable 0 */ |
| 565 |
|
|
#define SFC_FS0 1 /* Freq generator source 0 */ |
| 566 |
|
|
|
| 567 |
|
|
#define SYS_FREQCTRL1 (SYS_BASE + 0x24) |
| 568 |
|
|
#define SFC_FRDIV5(f) (f<<22) /* 29:22. Freq Divider 5 */ |
| 569 |
|
|
#define SFC_FE5 (1<<21) /* Freq generator output enable 5 */ |
| 570 |
|
|
#define SFC_FS5 (1<<20) /* Freq generator source 5 */ |
| 571 |
|
|
#define SFC_FRDIV4(f) (f<<12) /* 19:12. Freq Divider 4 */ |
| 572 |
|
|
#define SFC_FE4 (1<<11) /* Freq generator output enable 4 */ |
| 573 |
|
|
#define SFC_FS4 (1<<10) /* Freq generator source 4 */ |
| 574 |
|
|
#define SFC_FRDIV3(f) (f<<2) /* 9:2. Freq Divider 3 */ |
| 575 |
|
|
#define SFC_FE3 2 /* Freq generator output enable 3 */ |
| 576 |
|
|
#define SFC_FS3 1 /* Freq generator source 3 */ |
| 577 |
|
|
|
| 578 |
|
|
/************************************************************************/ |
| 579 |
|
|
/****************** Clock Source Control Registers ******************/ |
| 580 |
|
|
/************************************************************************/ |
| 581 |
|
|
|
| 582 |
|
|
#define SYS_CLKSRC (SYS_BASE + 0x28) |
| 583 |
|
|
#define SCS_ME1(n) (n<<27) /* EXTCLK1 Clock Mux input select */ |
| 584 |
|
|
#define SCS_ME0(n) (n<<22) /* EXTCLK0 Clock Mux input select */ |
| 585 |
|
|
#define SCS_MPC(n) (n<<17) /* PCI clock mux input select */ |
| 586 |
|
|
#define SCS_MUH(n) (n<<12) /* USB Host clock mux input select */ |
| 587 |
|
|
#define SCS_MUD(n) (n<<7) /* USB Device clock mux input select */ |
| 588 |
|
|
#define SCS_MEx_AUX 0x1 /* Aux clock */ |
| 589 |
|
|
#define SCS_MEx_FREQ0 0x2 /* FREQ0 */ |
| 590 |
|
|
#define SCS_MEx_FREQ1 0x3 /* FREQ1 */ |
| 591 |
|
|
#define SCS_MEx_FREQ2 0x4 /* FREQ2 */ |
| 592 |
|
|
#define SCS_MEx_FREQ3 0x5 /* FREQ3 */ |
| 593 |
|
|
#define SCS_MEx_FREQ4 0x6 /* FREQ4 */ |
| 594 |
|
|
#define SCS_MEx_FREQ5 0x7 /* FREQ5 */ |
| 595 |
|
|
#define SCS_DE1 (1<<26) /* EXTCLK1 clock divider select */ |
| 596 |
|
|
#define SCS_CE1 (1<<25) /* EXTCLK1 clock select */ |
| 597 |
|
|
#define SCS_DE0 (1<<21) /* EXTCLK0 clock divider select */ |
| 598 |
|
|
#define SCS_CE0 (1<<20) /* EXTCLK0 clock select */ |
| 599 |
|
|
#define SCS_DPC (1<<16) /* PCI clock divider select */ |
| 600 |
|
|
#define SCS_CPC (1<<15) /* PCI clock select */ |
| 601 |
|
|
#define SCS_DUH (1<<11) /* USB Host clock divider select */ |
| 602 |
|
|
#define SCS_CUH (1<<10) /* USB Host clock select */ |
| 603 |
|
|
#define SCS_DUD (1<<6) /* USB Device clock divider select */ |
| 604 |
|
|
#define SCS_CUD (1<<5) /* USB Device clock select */ |
| 605 |
|
|
|
| 606 |
|
|
/************************************************************************/ |
| 607 |
|
|
/*************************** PLL Control *****************************/ |
| 608 |
|
|
/************************************************************************/ |
| 609 |
|
|
|
| 610 |
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#define SYS_CPUPLL (SYS_BASE + 0x60) |
| 611 |
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#define SYS_AUXPLL (SYS_BASE + 0x64) |
| 612 |
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| 613 |
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#endif /* AUREG_H */ |
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