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#ifndef CPU_PPC_H |
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#define CPU_PPC_H |
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|
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/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_ppc.h,v 1.38 2005/09/24 23:44:19 debug Exp $ |
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*/ |
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|
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#include "misc.h" |
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|
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|
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struct cpu_family; |
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|
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#define MODE_PPC 0 |
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#define MODE_POWER 1 |
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|
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/* PPC CPU types: */ |
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struct ppc_cpu_type_def { |
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char *name; |
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int pvr; |
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int bits; |
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int flags; |
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int icache_shift; |
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int ilinesize; |
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int iway; |
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int dcache_shift; |
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int dlinesize; |
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int dway; |
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int l2cache_shift; |
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int l2linesize; |
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int l2way; |
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int altivec; |
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|
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/* TODO: POWER vs PowerPC? */ |
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}; |
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|
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/* Flags: */ |
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#define PPC_NOFP 1 |
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/* TODO: Most of these just bogus */ |
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|
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#define PPC_CPU_TYPE_DEFS { \ |
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{ "PPC405GP", 0, 32, PPC_NOFP, 15,5,2, 15,5,2, 20,5,1, 0 }, \ |
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{ "PPC603e", 0, 32, 0, 14,5,4, 14,5,4, 0,0,0, 0 }, \ |
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{ "MPC7400", 0x000c0000, 32, 0, 15,5,2, 15,5,2, 19,5,1, 1 }, \ |
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{ "PPC750", 0x00084202, 32, 0, 15,5,2, 15,5,2, 20,5,1, 0 }, \ |
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{ "G4e", 0, 32, 0, 15,5,8, 15,5,8, 18,5,8, 1 }, \ |
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{ "PPC970", 0x00390000, 64, 0, 16,7,1, 15,7,2, 19,7,1, 1 }, \ |
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{ NULL, 0, 0,0,0,0,0,0,0,0,0,0,0,0 } \ |
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} |
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|
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#define PPC_NGPRS 32 |
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#define PPC_NFPRS 32 |
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|
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|
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#define PPC_N_IC_ARGS 3 |
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#define PPC_INSTR_ALIGNMENT_SHIFT 2 |
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#define PPC_IC_ENTRIES_SHIFT 10 |
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#define PPC_IC_ENTRIES_PER_PAGE (1 << PPC_IC_ENTRIES_SHIFT) |
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#define PPC_PC_TO_IC_ENTRY(a) (((a)>>PPC_INSTR_ALIGNMENT_SHIFT) \ |
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& (PPC_IC_ENTRIES_PER_PAGE-1)) |
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#define PPC_ADDR_TO_PAGENR(a) ((a) >> (PPC_IC_ENTRIES_SHIFT \ |
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+ PPC_INSTR_ALIGNMENT_SHIFT)) |
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|
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struct ppc_instr_call { |
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void (*f)(struct cpu *, struct ppc_instr_call *); |
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size_t arg[PPC_N_IC_ARGS]; |
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}; |
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|
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/* Translation cache struct for each physical page: */ |
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struct ppc_tc_physpage { |
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uint32_t next_ofs; /* or 0 for end of chain */ |
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uint64_t physaddr; |
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int flags; |
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struct ppc_instr_call ics[PPC_IC_ENTRIES_PER_PAGE + 1]; |
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}; |
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|
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#define PPC_N_VPH_ENTRIES 1048576 |
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|
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#define PPC_MAX_VPH_TLB_ENTRIES 256 |
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struct ppc_vpg_tlb_entry { |
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int valid; |
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int writeflag; |
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int64_t timestamp; |
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unsigned char *host_page; |
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uint64_t vaddr_page; |
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uint64_t paddr_page; |
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}; |
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|
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struct ppc_cpu { |
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struct ppc_cpu_type_def cpu_type; |
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|
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uint64_t of_emul_addr; |
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|
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int mode; /* MODE_PPC or MODE_POWER */ |
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int bits; /* 32 or 64 */ |
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|
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uint64_t zero; /* A zero register */ |
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|
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uint32_t cr; /* Condition Register */ |
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uint32_t fpscr; /* FP Status and Control Register */ |
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uint64_t lr; /* Link Register */ |
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uint64_t ctr; /* Count Register */ |
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uint64_t gpr[PPC_NGPRS]; /* General Purpose Registers */ |
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uint64_t xer; /* FP Exception Register */ |
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uint64_t fpr[PPC_NFPRS]; /* Floating-Point Registers */ |
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|
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uint32_t tbl; /* Time Base Lower */ |
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uint32_t tbu; /* Time Base Upper */ |
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uint32_t dec; /* Decrementer */ |
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uint32_t hdec; /* Hypervisor Decrementer */ |
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uint64_t sdr1; /* Storage Descriptor Register */ |
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uint64_t srr0; /* Supervisor save/restore 0 */ |
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uint64_t srr1; /* Supervisor save/restore 1 */ |
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uint64_t ssr0; /* Machine status save/restore |
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register 0 */ |
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uint64_t ssr1; /* Machine status save/restore |
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register 1 */ |
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uint64_t msr; /* Machine state register */ |
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uint64_t sprg0; /* Special Purpose Register G0 */ |
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uint64_t sprg1; /* Special Purpose Register G1 */ |
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uint64_t sprg2; /* Special Purpose Register G2 */ |
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uint64_t sprg3; /* Special Purpose Register G3 */ |
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uint64_t dbsr; /* Debug Status Register */ |
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uint32_t pvr; /* Processor Version Register */ |
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uint32_t pir; /* Processor ID */ |
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|
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/* TODO: 64-bit SRs? (Segment registers) */ |
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uint32_t sr[16]; |
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|
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/* TODO: 64-bit BATs? */ |
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uint32_t ibat_u[4]; |
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uint32_t ibat_l[4]; |
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uint32_t dbat_u[4]; |
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uint32_t dbat_l[4]; |
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|
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uint64_t ll_addr; /* Load-linked / store-conditional */ |
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int ll_bit; |
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|
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|
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/* |
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* Instruction translation cache: |
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*/ |
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|
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/* cur_ic_page is a pointer to an array of PPC_IC_ENTRIES_PER_PAGE |
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instruction call entries. next_ic points to the next such |
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call to be executed. */ |
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struct ppc_tc_physpage *cur_physpage; |
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struct ppc_instr_call *cur_ic_page; |
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struct ppc_instr_call *next_ic; |
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|
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|
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/* |
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* Virtual -> physical -> host address translation: |
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* |
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* host_load and host_store point to arrays of PPC_N_VPH_ENTRIES |
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* pointers (to host pages); phys_addr points to an array of |
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* PPC_N_VPH_ENTRIES uint32_t. |
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*/ |
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|
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struct ppc_vpg_tlb_entry vph_tlb_entry[PPC_MAX_VPH_TLB_ENTRIES]; |
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unsigned char *host_load[PPC_N_VPH_ENTRIES]; |
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unsigned char *host_store[PPC_N_VPH_ENTRIES]; |
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uint32_t phys_addr[PPC_N_VPH_ENTRIES]; |
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struct ppc_tc_physpage *phys_page[PPC_N_VPH_ENTRIES]; |
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}; |
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|
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|
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/* Machine status word bits: (according to Book 3) */ |
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#define PPC_MSR_SF (1ULL << 63) /* Sixty-Four-Bit Mode */ |
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/* bits 62..61 are reserved */ |
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#define PPC_MSR_HV (1ULL << 60) /* Hypervisor */ |
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/* bits 59..17 are reserved */ |
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#define PPC_MSR_ILE (1 << 16) /* Interrupt Little-Endian Mode */ |
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#define PPC_MSR_EE (1 << 15) /* External Interrupt Enable */ |
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#define PPC_MSR_PR (1 << 14) /* Problem State */ |
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#define PPC_MSR_FP (1 << 13) /* Floating-Point Available */ |
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#define PPC_MSR_ME (1 << 12) /* Machine Check Interrupt Enable */ |
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#define PPC_MSR_FE0 (1 << 11) /* Floating-Point Exception Mode 0 */ |
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#define PPC_MSR_SE (1 << 10) /* Single-Step Trace Enable */ |
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#define PPC_MSR_BE (1 << 9) /* Branch Trace Enable */ |
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#define PPC_MSR_FE1 (1 << 8) /* Floating-Point Exception Mode 1 */ |
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#define PPC_MSR_IR (1 << 5) /* Instruction Relocate */ |
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#define PPC_MSR_DR (1 << 4) /* Data Relocate */ |
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#define PPC_MSR_PMM (1 << 2) /* Performance Monitor Mark */ |
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#define PPC_MSR_RI (1 << 1) /* Recoverable Interrupt */ |
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#define PPC_MSR_LE (1) /* Little-Endian Mode */ |
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|
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/* XER bits: */ |
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#define PPC_XER_SO (1 << 31) /* Summary Overflow */ |
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#define PPC_XER_OV (1 << 30) /* Overflow */ |
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#define PPC_XER_CA (1 << 29) /* Carry */ |
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|
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|
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/* cpu_ppc.c: */ |
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void ppc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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void ppc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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void ppc_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int); |
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void ppc32_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int); |
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void ppc_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
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void ppc32_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
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int ppc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
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unsigned char *data, size_t len, int writeflag, int cache_flags); |
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int ppc_cpu_family_init(struct cpu_family *); |
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|
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/* memory_ppc.c: */ |
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int ppc_translate_address(struct cpu *cpu, uint64_t vaddr, |
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uint64_t *return_addr, int flags); |
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|
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#endif /* CPU_PPC_H */ |
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