src/include/cpu_i960.h

#ifndef CPU_I960_H
#define CPU_I960_H

/*
 *  Copyright (C) 2005  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_i960.h,v 1.1 2005/09/07 07:10:17 debug Exp $
 */

#include "misc.h"


struct cpu_family;

#define N_I960_NREGS            32
#define I960_SP         1
#define I960_FP         31

#define I960_N_IC_ARGS                  3
#define I960_INSTR_ALIGNMENT_SHIFT      2
#define I960_IC_ENTRIES_SHIFT           10
#define I960_IC_ENTRIES_PER_PAGE        (1 << I960_IC_ENTRIES_SHIFT)
#define I960_PC_TO_IC_ENTRY(a)          (((a)>>I960_INSTR_ALIGNMENT_SHIFT) \
                                        & (I960_IC_ENTRIES_PER_PAGE-1))
#define I960_ADDR_TO_PAGENR(a)          ((a) >> (I960_IC_ENTRIES_SHIFT \
                                        + I960_INSTR_ALIGNMENT_SHIFT))

struct i960_instr_call {
        void    (*f)(struct cpu *, struct i960_instr_call *);
        size_t  arg[I960_N_IC_ARGS];
};

/*  Translation cache struct for each physical page:  */
struct i960_tc_physpage {
        uint32_t        next_ofs;       /*  or 0 for end of chain  */
        uint32_t        physaddr;
        int             flags;
        struct i960_instr_call ics[I960_IC_ENTRIES_PER_PAGE + 1];
};


#define I960_N_VPH_ENTRIES      1048576

#define I960_MAX_VPH_TLB_ENTRIES                256
struct i960_vpg_tlb_entry {
        int             valid;
        int             writeflag;
        int64_t         timestamp;
        unsigned char   *host_page;
        uint32_t        vaddr_page;
        uint32_t        paddr_page;
};


struct i960_cpu {
        /*
         *  General Purpose Registers:
         */

        uint32_t        r[N_I960_NREGS];


        /*
         *  Instruction translation cache:
         */

        /*  cur_ic_page is a pointer to an array of I960_IC_ENTRIES_PER_PAGE
            instruction call entries. next_ic points to the next such
            call to be executed.  */
        struct i960_tc_physpage *cur_physpage;
        struct i960_instr_call  *cur_ic_page;
        struct i960_instr_call  *next_ic;


        /*
         *  Virtual -> physical -> host address translation:
         *
         *  host_load and host_store point to arrays of I960_N_VPH_ENTRIES
         *  pointers (to host pages); phys_addr points to an array of
         *  I960_N_VPH_ENTRIES uint32_t.
         */

        struct i960_vpg_tlb_entry       vph_tlb_entry[I960_MAX_VPH_TLB_ENTRIES];
        unsigned char                   *host_load[I960_N_VPH_ENTRIES];
        unsigned char                   *host_store[I960_N_VPH_ENTRIES];
        uint32_t                        phys_addr[I960_N_VPH_ENTRIES];
        struct i960_tc_physpage         *phys_page[I960_N_VPH_ENTRIES];
};


/*  cpu_i960.c:  */
void i960_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
        unsigned char *host_page, int writeflag, uint64_t paddr_page);
void i960_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int);
void i960_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
int i960_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
        unsigned char *data, size_t len, int writeflag, int cache_flags);
int i960_cpu_family_init(struct cpu_family *);


#endif  /*  CPU_I960_H  */
1	#ifndef CPU_I960_H
2	#define CPU_I960_H
3
4	/*
5	* Copyright (C) 2005 Anders Gavare. All rights reserved.
6	*
7	* Redistribution and use in source and binary forms, with or without
8	* modification, are permitted provided that the following conditions are met:
9	*
10	* 1. Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.
12	* 2. Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	* 3. The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.
17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28	* SUCH DAMAGE.
29	*
30	*
31	* $Id: cpu_i960.h,v 1.1 2005/09/07 07:10:17 debug Exp $
32	*/
33
34	#include "misc.h"
35
36
37	struct cpu_family;
38
39	#define N_I960_NREGS 32
40	#define I960_SP 1
41	#define I960_FP 31
42
43	#define I960_N_IC_ARGS 3
44	#define I960_INSTR_ALIGNMENT_SHIFT 2
45	#define I960_IC_ENTRIES_SHIFT 10
46	#define I960_IC_ENTRIES_PER_PAGE (1 << I960_IC_ENTRIES_SHIFT)
47	#define I960_PC_TO_IC_ENTRY(a) (((a)>>I960_INSTR_ALIGNMENT_SHIFT) \
48	& (I960_IC_ENTRIES_PER_PAGE-1))
49	#define I960_ADDR_TO_PAGENR(a) ((a) >> (I960_IC_ENTRIES_SHIFT \
50	+ I960_INSTR_ALIGNMENT_SHIFT))
51
52	struct i960_instr_call {
53	void (f)(struct cpu , struct i960_instr_call *);
54	size_t arg[I960_N_IC_ARGS];
55	};
56
57	/* Translation cache struct for each physical page: */
58	struct i960_tc_physpage {
59	uint32_t next_ofs; /* or 0 for end of chain */
60	uint32_t physaddr;
61	int flags;
62	struct i960_instr_call ics[I960_IC_ENTRIES_PER_PAGE + 1];
63	};
64
65
66	#define I960_N_VPH_ENTRIES 1048576
67
68	#define I960_MAX_VPH_TLB_ENTRIES 256
69	struct i960_vpg_tlb_entry {
70	int valid;
71	int writeflag;
72	int64_t timestamp;
73	unsigned char *host_page;
74	uint32_t vaddr_page;
75	uint32_t paddr_page;
76	};
77
78
79	struct i960_cpu {
80	/*
81	* General Purpose Registers:
82	*/
83
84	uint32_t r[N_I960_NREGS];
85
86
87	/*
88	* Instruction translation cache:
89	*/
90
91	/* cur_ic_page is a pointer to an array of I960_IC_ENTRIES_PER_PAGE
92	instruction call entries. next_ic points to the next such
93	call to be executed. */
94	struct i960_tc_physpage *cur_physpage;
95	struct i960_instr_call *cur_ic_page;
96	struct i960_instr_call *next_ic;
97
98
99	/*
100	* Virtual -> physical -> host address translation:
101	*
102	* host_load and host_store point to arrays of I960_N_VPH_ENTRIES
103	* pointers (to host pages); phys_addr points to an array of
104	* I960_N_VPH_ENTRIES uint32_t.
105	*/
106
107	struct i960_vpg_tlb_entry vph_tlb_entry[I960_MAX_VPH_TLB_ENTRIES];
108	unsigned char *host_load[I960_N_VPH_ENTRIES];
109	unsigned char *host_store[I960_N_VPH_ENTRIES];
110	uint32_t phys_addr[I960_N_VPH_ENTRIES];
111	struct i960_tc_physpage *phys_page[I960_N_VPH_ENTRIES];
112	};
113
114
115	/* cpu_i960.c: */
116	void i960_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
117	unsigned char *host_page, int writeflag, uint64_t paddr_page);
118	void i960_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int);
119	void i960_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
120	int i960_memory_rw(struct cpu cpu, struct memory mem, uint64_t vaddr,
121	unsigned char *data, size_t len, int writeflag, int cache_flags);
122	int i960_cpu_family_init(struct cpu_family *);
123
124
125	#endif /* CPU_I960_H */