src/devices/pci_symphony_83c553.c

/*
 *  Copyright (C) 2005  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *   
 *
 *  $Id: pci_symphony_83c553.c,v 1.4 2005/09/30 23:55:57 debug Exp $
 *
 *  Symphony Labs 82C105 PCIIDE controller.
 *  Symphony Labs 83C553 PCI->ISA bridge.
 *
 *  TODO:  These are just dummy devices, so far.
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "bus_pci.h"
#include "device.h"
#include "devices.h"
#include "machine.h"
#include "memory.h"
#include "misc.h"


#define PCI_VENDOR_SYMPHONY             0x10ad
#define PCI_PRODUCT_SYMPHONY_82C105     0x0105
#define PCI_PRODUCT_SYMPHONY_83C553     0x0565


/*
 *  pci_symphony_82c105_rr():
 */
uint32_t pci_symphony_82c105_rr(int reg)
{
        switch (reg) {
        case 0x00:
                return PCI_VENDOR_SYMPHONY +
                    (PCI_PRODUCT_SYMPHONY_82C105 << 16);
        case 0x04:
                return 0xffffffff;      /*  ???  */
        case 0x08:
                /*  Revision  */
                return PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE,
                    PCI_SUBCLASS_MASS_STORAGE_IDE, 0) + 0x05;
        case 0x40:
                /*  APO_IDECONF: channel 0 and 1 enabled  */
                return 0x00000003;
        default:
                return 0;
        }
}


/*
 *  pci_symphony_82c105_init():
 */
void pci_symphony_82c105_init(struct machine *machine, struct memory *mem)
{
        /*
         *  TODO: The check for machine type shouldn't be here?
         */

        switch (machine->machine_type) {

        case MACHINE_NETWINDER:
                device_add(machine, "wdc addr=0x7c0001f0 irq=46");/* primary  */
                device_add(machine, "wdc addr=0x7c000170 irq=47");/* secondary*/
                break;

        default:fatal("pci_symphony_82c105_init(): unimplemented machine "
                    "type %i\n", machine->machine_type);
                exit(1);
        }
}


/*
 *  pci_symphony_83c553_rr():
 */
uint32_t pci_symphony_83c553_rr(int reg)
{
        switch (reg) {
        case 0x00:
                return PCI_VENDOR_SYMPHONY +
                    (PCI_PRODUCT_SYMPHONY_83C553 << 16);
        case 0x04:
                return 0xffffffff;      /*  ???  */
        case 0x08:
                /*  Revision  */
                return PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
                    PCI_SUBCLASS_BRIDGE_ISA, 0) + 0x10;
        case 0x0c:
                /*  Bit 7 of Header-type byte ==> multi-function device  */
                return 0x00800000;
        default:
                return 0;
        }
}


/*
 *  pci_symphony_83c553_init():
 */
void pci_symphony_83c553_init(struct machine *machine, struct memory *mem)
{
}

1	dpavlin	14	/*
2			* Copyright (C) 2005 Anders Gavare. All rights reserved.
3			*
4			* Redistribution and use in source and binary forms, with or without
5			* modification, are permitted provided that the following conditions are met:
6			*
7			* 1. Redistributions of source code must retain the above copyright
8			* notice, this list of conditions and the following disclaimer.
9			* 2. Redistributions in binary form must reproduce the above copyright
10			* notice, this list of conditions and the following disclaimer in the
11			* documentation and/or other materials provided with the distribution.
12			* 3. The name of the author may not be used to endorse or promote products
13			* derived from this software without specific prior written permission.
14			*
15			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25			* SUCH DAMAGE.
26			*
27			*
28			* $Id: pci_symphony_83c553.c,v 1.4 2005/09/30 23:55:57 debug Exp $
29			*
30			* Symphony Labs 82C105 PCIIDE controller.
31			* Symphony Labs 83C553 PCI->ISA bridge.
32			*
33			* TODO: These are just dummy devices, so far.
34			*/
35
36			#include <stdio.h>
37			#include <stdlib.h>
38			#include <string.h>
39
40			#include "bus_pci.h"
41			#include "device.h"
42			#include "devices.h"
43			#include "machine.h"
44			#include "memory.h"
45			#include "misc.h"
46
47
48			#define PCI_VENDOR_SYMPHONY 0x10ad
49			#define PCI_PRODUCT_SYMPHONY_82C105 0x0105
50			#define PCI_PRODUCT_SYMPHONY_83C553 0x0565
51
52
53			/*
54			* pci_symphony_82c105_rr():
55			*/
56			uint32_t pci_symphony_82c105_rr(int reg)
57			{
58			switch (reg) {
59			case 0x00:
60			return PCI_VENDOR_SYMPHONY +
61			(PCI_PRODUCT_SYMPHONY_82C105 << 16);
62			case 0x04:
63			return 0xffffffff; /* ??? */
64			case 0x08:
65			/* Revision */
66			return PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE,
67			PCI_SUBCLASS_MASS_STORAGE_IDE, 0) + 0x05;
68			case 0x40:
69			/* APO_IDECONF: channel 0 and 1 enabled */
70			return 0x00000003;
71			default:
72			return 0;
73			}
74			}
75
76
77			/*
78			* pci_symphony_82c105_init():
79			*/
80			void pci_symphony_82c105_init(struct machine machine, struct memory mem)
81			{
82			/*
83			* TODO: The check for machine type shouldn't be here?
84			*/
85
86			switch (machine->machine_type) {
87
88			case MACHINE_NETWINDER:
89			device_add(machine, "wdc addr=0x7c0001f0 irq=46");/* primary */
90			device_add(machine, "wdc addr=0x7c000170 irq=47");/* secondary*/
91			break;
92
93			default:fatal("pci_symphony_82c105_init(): unimplemented machine "
94			"type %i\n", machine->machine_type);
95			exit(1);
96			}
97			}
98
99
100			/*
101			* pci_symphony_83c553_rr():
102			*/
103			uint32_t pci_symphony_83c553_rr(int reg)
104			{
105			switch (reg) {
106			case 0x00:
107			return PCI_VENDOR_SYMPHONY +
108			(PCI_PRODUCT_SYMPHONY_83C553 << 16);
109			case 0x04:
110			return 0xffffffff; /* ??? */
111			case 0x08:
112			/* Revision */
113			return PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
114			PCI_SUBCLASS_BRIDGE_ISA, 0) + 0x10;
115			case 0x0c:
116			/* Bit 7 of Header-type byte ==> multi-function device */
117			return 0x00800000;
118			default:
119			return 0;
120			}
121			}
122
123
124			/*
125			* pci_symphony_83c553_init():
126			*/
127			void pci_symphony_83c553_init(struct machine machine, struct memory mem)
128			{
129			}
130