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dpavlin |
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/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_footbridge.c,v 1.22 2005/10/07 15:10:02 debug Exp $ |
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* |
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* Footbridge. Used in Netwinder and Cats. |
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* |
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* TODO: Most things. For example: |
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* |
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* o) Add actual support for the fcom serial port. |
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* o) FIQs. |
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* o) Lots of other things. |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include "bus_pci.h" |
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#include "console.h" |
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#include "cpu.h" |
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#include "device.h" |
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#include "devices.h" /* for struct footbridge_data */ |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "dc21285reg.h" |
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#define DEV_FOOTBRIDGE_TICK_SHIFT 14 |
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#define DEV_FOOTBRIDGE_LENGTH 0x400 |
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/* |
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* dev_footbridge_tick(): |
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* |
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* The 4 footbridge timers should decrease every now and then, and cause |
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* interrupts. Periodic interrupts restart as soon as they are acknowledged, |
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* non-periodic interrupts need to be "reloaded" to restart. |
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*/ |
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void dev_footbridge_tick(struct cpu *cpu, void *extra) |
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{ |
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int i; |
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struct footbridge_data *d = (struct footbridge_data *) extra; |
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for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) { |
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int amount = 1 << DEV_FOOTBRIDGE_TICK_SHIFT; |
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if (d->timer_control[i] & TIMER_FCLK_16) |
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amount >>= 4; |
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else if (d->timer_control[i] & TIMER_FCLK_256) |
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amount >>= 8; |
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if (d->timer_tick_countdown[i] == 0) |
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continue; |
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if (d->timer_value[i] > amount) |
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d->timer_value[i] -= amount; |
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else |
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d->timer_value[i] = 0; |
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if (d->timer_value[i] == 0) { |
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d->timer_tick_countdown[i] --; |
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if (d->timer_tick_countdown[i] > 0) |
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continue; |
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if (d->timer_control[i] & TIMER_ENABLE) |
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cpu_interrupt(cpu, IRQ_TIMER_1 + i); |
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d->timer_tick_countdown[i] = 0; |
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} |
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} |
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} |
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/* |
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* dev_footbridge_isa_access(): |
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* |
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* NetBSD seems to read 0x79000000 to find out which ISA interrupt occurred, |
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* a quicker way than dealing with legacy 0x20/0xa0 ISA ports. |
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*/ |
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int dev_footbridge_isa_access(struct cpu *cpu, struct memory *mem, |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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{ |
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/* struct footbridge_data *d = extra; */ |
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uint64_t idata = 0, odata = 0; |
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int x; |
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idata = memory_readmax64(cpu, data, len); |
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if (writeflag == MEM_WRITE) |
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fatal("[ footbridge_isa: WARNING/TODO: write! ]\n"); |
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/* |
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* NetBSD seems to want a value of 0x20 + x, where x is the highest |
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* priority ISA interrupt which is currently asserted and not masked. |
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*/ |
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for (x=0; x<16; x++) { |
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if (x == 2) |
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continue; |
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if (x < 8 && (cpu->machine->isa_pic_data.pic1->irr & |
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~cpu->machine->isa_pic_data.pic1->ier & |
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(1 << x))) |
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break; |
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if (x >= 8 && (cpu->machine->isa_pic_data.pic2->irr & |
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~cpu->machine->isa_pic_data.pic2->ier & |
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(1 << (x&7)))) |
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break; |
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} |
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if (x == 16) |
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fatal("_\n_ SPORADIC but INVALID ISA interrupt\n_\n"); |
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odata = 0x20 + (x & 15); |
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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return 1; |
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} |
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/* |
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* dev_footbridge_pci_access(): |
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* |
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* The Footbridge PCI configuration space is not implemented as "address + |
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* data port" pair, but instead a 24-bit (16 MB) chunk of physical memory |
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* decodes as the address. This function translates that into bus_pci_access |
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* calls. |
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*/ |
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int dev_footbridge_pci_access(struct cpu *cpu, struct memory *mem, |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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{ |
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struct footbridge_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
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int bus, device, function, regnr, res; |
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uint64_t pci_word; |
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idata = memory_readmax64(cpu, data, len); |
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bus = (relative_addr >> 16) & 0xff; |
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device = (relative_addr >> 11) & 0x1f; |
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function = (relative_addr >> 8) & 0x7; |
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regnr = relative_addr & 0xff; |
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if (bus == 255) { |
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fatal("[ footbridge DEBUG ERROR: bus 255 unlikely," |
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" pc (might not be updated) = 0x%08x ]\n", (int)cpu->pc); |
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exit(1); |
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} |
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debug("[ footbridge_pci: %s bus %i, device %i, function " |
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"%i, register %i ]\n", writeflag == MEM_READ? "read from" |
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: "write to", bus, device, function, regnr); |
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if (d->pcibus == NULL) { |
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fatal("dev_footbridge_pci_access(): no PCI bus?\n"); |
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return 0; |
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} |
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pci_word = relative_addr & 0x00ffffff; |
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res = bus_pci_access(cpu, mem, BUS_PCI_ADDR, |
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&pci_word, MEM_WRITE, d->pcibus); |
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if (writeflag == MEM_READ) { |
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res = bus_pci_access(cpu, mem, BUS_PCI_DATA, |
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&pci_word, MEM_READ, d->pcibus); |
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odata = pci_word; |
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} else { |
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pci_word = idata; |
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res = bus_pci_access(cpu, mem, BUS_PCI_DATA, |
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&pci_word, MEM_WRITE, d->pcibus); |
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} |
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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return 1; |
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} |
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/* |
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* dev_footbridge_access(): |
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* |
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* The DC21285 registers. |
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*/ |
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int dev_footbridge_access(struct cpu *cpu, struct memory *mem, |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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{ |
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struct footbridge_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
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int timer_nr = 0; |
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idata = memory_readmax64(cpu, data, len); |
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if (relative_addr >= TIMER_1_LOAD && relative_addr <= TIMER_4_CLEAR) { |
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timer_nr = (relative_addr >> 5) & (N_FOOTBRIDGE_TIMERS - 1); |
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relative_addr &= ~0x060; |
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} |
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switch (relative_addr) { |
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case VENDOR_ID: |
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odata = 0x1011; /* DC21285_VENDOR_ID */ |
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break; |
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case DEVICE_ID: |
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odata = 0x1065; /* DC21285_DEVICE_ID */ |
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break; |
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case REVISION: |
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odata = 3; /* footbridge revision number */ |
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break; |
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case UART_DATA: |
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if (writeflag == MEM_WRITE) |
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console_putchar(d->console_handle, idata); |
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break; |
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case UART_RX_STAT: |
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/* TODO */ |
| 249 |
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odata = 0; |
| 250 |
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break; |
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| 252 |
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case UART_FLAGS: |
| 253 |
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odata = UART_TX_EMPTY; |
| 254 |
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break; |
| 255 |
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| 256 |
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case IRQ_STATUS: |
| 257 |
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if (writeflag == MEM_READ) |
| 258 |
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odata = d->irq_status & d->irq_enable; |
| 259 |
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else { |
| 260 |
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fatal("[ WARNING: footbridge write to irq status? ]\n"); |
| 261 |
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exit(1); |
| 262 |
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} |
| 263 |
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break; |
| 264 |
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| 265 |
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case IRQ_RAW_STATUS: |
| 266 |
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if (writeflag == MEM_READ) |
| 267 |
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odata = d->irq_status; |
| 268 |
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else { |
| 269 |
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fatal("[ footbridge write to irq_raw_status ]\n"); |
| 270 |
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exit(1); |
| 271 |
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} |
| 272 |
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break; |
| 273 |
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| 274 |
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case IRQ_ENABLE_SET: |
| 275 |
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if (writeflag == MEM_WRITE) { |
| 276 |
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d->irq_enable |= idata; |
| 277 |
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cpu_interrupt(cpu, 64); |
| 278 |
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} else { |
| 279 |
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fatal("[ WARNING: footbridge read from " |
| 280 |
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"ENABLE SET? ]\n"); |
| 281 |
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exit(1); |
| 282 |
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odata = d->irq_enable; |
| 283 |
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} |
| 284 |
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break; |
| 285 |
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| 286 |
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case IRQ_ENABLE_CLEAR: |
| 287 |
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if (writeflag == MEM_WRITE) { |
| 288 |
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d->irq_enable &= ~idata; |
| 289 |
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cpu_interrupt(cpu, 64); |
| 290 |
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} else { |
| 291 |
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fatal("[ WARNING: footbridge read from " |
| 292 |
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"ENABLE CLEAR? ]\n"); |
| 293 |
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exit(1); |
| 294 |
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odata = d->irq_enable; |
| 295 |
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} |
| 296 |
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break; |
| 297 |
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| 298 |
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case FIQ_STATUS: |
| 299 |
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if (writeflag == MEM_READ) |
| 300 |
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odata = d->fiq_status & d->fiq_enable; |
| 301 |
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else { |
| 302 |
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fatal("[ WARNING: footbridge write to fiq status? ]\n"); |
| 303 |
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exit(1); |
| 304 |
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} |
| 305 |
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break; |
| 306 |
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| 307 |
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case FIQ_RAW_STATUS: |
| 308 |
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if (writeflag == MEM_READ) |
| 309 |
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odata = d->fiq_status; |
| 310 |
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else { |
| 311 |
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fatal("[ footbridge write to fiq_raw_status ]\n"); |
| 312 |
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exit(1); |
| 313 |
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} |
| 314 |
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break; |
| 315 |
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| 316 |
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case FIQ_ENABLE_SET: |
| 317 |
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if (writeflag == MEM_WRITE) |
| 318 |
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d->fiq_enable |= idata; |
| 319 |
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break; |
| 320 |
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| 321 |
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case FIQ_ENABLE_CLEAR: |
| 322 |
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if (writeflag == MEM_WRITE) |
| 323 |
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d->fiq_enable &= ~idata; |
| 324 |
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break; |
| 325 |
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| 326 |
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case TIMER_1_LOAD: |
| 327 |
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if (writeflag == MEM_READ) |
| 328 |
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odata = d->timer_load[timer_nr]; |
| 329 |
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else { |
| 330 |
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d->timer_value[timer_nr] = |
| 331 |
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d->timer_load[timer_nr] = idata & TIMER_MAX_VAL; |
| 332 |
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debug("[ footbridge: timer %i (1-based), value %i ]\n", |
| 333 |
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timer_nr + 1, (int)d->timer_value[timer_nr]); |
| 334 |
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d->timer_tick_countdown[timer_nr] = 1; |
| 335 |
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cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr); |
| 336 |
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} |
| 337 |
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break; |
| 338 |
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| 339 |
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case TIMER_1_VALUE: |
| 340 |
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if (writeflag == MEM_READ) { |
| 341 |
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dev_footbridge_tick(cpu, d); |
| 342 |
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odata = d->timer_value[timer_nr]; |
| 343 |
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} else |
| 344 |
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d->timer_value[timer_nr] = idata & TIMER_MAX_VAL; |
| 345 |
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break; |
| 346 |
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| 347 |
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case TIMER_1_CONTROL: |
| 348 |
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if (writeflag == MEM_READ) |
| 349 |
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odata = d->timer_control[timer_nr]; |
| 350 |
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else { |
| 351 |
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d->timer_control[timer_nr] = idata; |
| 352 |
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if (idata & TIMER_FCLK_16 && |
| 353 |
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idata & TIMER_FCLK_256) { |
| 354 |
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fatal("TODO: footbridge timer: " |
| 355 |
|
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"both 16 and 256?\n"); |
| 356 |
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exit(1); |
| 357 |
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} |
| 358 |
|
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if (idata & TIMER_ENABLE) { |
| 359 |
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d->timer_value[timer_nr] = |
| 360 |
|
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d->timer_load[timer_nr]; |
| 361 |
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d->timer_tick_countdown[timer_nr] = 1; |
| 362 |
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} |
| 363 |
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cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr); |
| 364 |
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} |
| 365 |
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break; |
| 366 |
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|
| 367 |
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case TIMER_1_CLEAR: |
| 368 |
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if (d->timer_control[timer_nr] & TIMER_MODE_PERIODIC) { |
| 369 |
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d->timer_value[timer_nr] = d->timer_load[timer_nr]; |
| 370 |
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d->timer_tick_countdown[timer_nr] = 1; |
| 371 |
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} |
| 372 |
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|
cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr); |
| 373 |
|
|
break; |
| 374 |
|
|
|
| 375 |
|
|
default:if (writeflag == MEM_READ) { |
| 376 |
|
|
fatal("[ footbridge: read from 0x%x ]\n", |
| 377 |
|
|
(int)relative_addr); |
| 378 |
|
|
} else { |
| 379 |
|
|
fatal("[ footbridge: write to 0x%x: 0x%llx ]\n", |
| 380 |
|
|
(int)relative_addr, (long long)idata); |
| 381 |
|
|
} |
| 382 |
|
|
} |
| 383 |
|
|
|
| 384 |
|
|
if (writeflag == MEM_READ) |
| 385 |
|
|
memory_writemax64(cpu, data, len, odata); |
| 386 |
|
|
|
| 387 |
|
|
return 1; |
| 388 |
|
|
} |
| 389 |
|
|
|
| 390 |
|
|
|
| 391 |
|
|
/* |
| 392 |
|
|
* devinit_footbridge(): |
| 393 |
|
|
*/ |
| 394 |
|
|
int devinit_footbridge(struct devinit *devinit) |
| 395 |
|
|
{ |
| 396 |
|
|
struct footbridge_data *d; |
| 397 |
|
|
uint64_t pci_addr = 0x7b000000; |
| 398 |
|
|
int i; |
| 399 |
|
|
|
| 400 |
|
|
d = malloc(sizeof(struct footbridge_data)); |
| 401 |
|
|
if (d == NULL) { |
| 402 |
|
|
fprintf(stderr, "out of memory\n"); |
| 403 |
|
|
exit(1); |
| 404 |
|
|
} |
| 405 |
|
|
memset(d, 0, sizeof(struct footbridge_data)); |
| 406 |
|
|
|
| 407 |
|
|
/* DC21285 register access: */ |
| 408 |
|
|
memory_device_register(devinit->machine->memory, devinit->name, |
| 409 |
|
|
devinit->addr, DEV_FOOTBRIDGE_LENGTH, |
| 410 |
|
|
dev_footbridge_access, d, MEM_DEFAULT, NULL); |
| 411 |
|
|
|
| 412 |
|
|
/* ISA interrupt status word: */ |
| 413 |
|
|
memory_device_register(devinit->machine->memory, "footbridge_isa", |
| 414 |
|
|
0x79000000, 8, dev_footbridge_isa_access, d, MEM_DEFAULT, NULL); |
| 415 |
|
|
|
| 416 |
|
|
/* The "fcom" console: */ |
| 417 |
|
|
d->console_handle = console_start_slave(devinit->machine, "fcom"); |
| 418 |
|
|
|
| 419 |
|
|
/* A PCI bus: */ |
| 420 |
|
|
d->pcibus = bus_pci_init(devinit->irq_nr); |
| 421 |
|
|
|
| 422 |
|
|
/* ... with some default devices for known machine types: */ |
| 423 |
|
|
switch (devinit->machine->machine_type) { |
| 424 |
|
|
case MACHINE_CATS: |
| 425 |
|
|
bus_pci_add(devinit->machine, d->pcibus, |
| 426 |
|
|
devinit->machine->memory, 0xc0, 7, 0, |
| 427 |
|
|
pci_ali_m1543_init, pci_ali_m1543_rr); |
| 428 |
|
|
bus_pci_add(devinit->machine, d->pcibus, |
| 429 |
|
|
devinit->machine->memory, 0xc0, 16, 0, |
| 430 |
|
|
pci_ali_m5229_init, pci_ali_m5229_rr); |
| 431 |
|
|
break; |
| 432 |
|
|
case MACHINE_NETWINDER: |
| 433 |
|
|
bus_pci_add(devinit->machine, d->pcibus, |
| 434 |
|
|
devinit->machine->memory, 0xc0, 11, 0, |
| 435 |
|
|
pci_symphony_83c553_init, pci_symphony_83c553_rr); |
| 436 |
|
|
bus_pci_add(devinit->machine, d->pcibus, |
| 437 |
|
|
devinit->machine->memory, 0xc0, 11, 1, |
| 438 |
|
|
pci_symphony_82c105_init, pci_symphony_82c105_rr); |
| 439 |
|
|
break; |
| 440 |
|
|
default:fatal("footbridge: unimplemented machine type.\n"); |
| 441 |
|
|
exit(1); |
| 442 |
|
|
} |
| 443 |
|
|
|
| 444 |
|
|
/* PCI configuration space: */ |
| 445 |
|
|
memory_device_register(devinit->machine->memory, |
| 446 |
|
|
"footbridge_pci", pci_addr, 0x1000000, |
| 447 |
|
|
dev_footbridge_pci_access, d, MEM_DEFAULT, NULL); |
| 448 |
|
|
|
| 449 |
|
|
/* Timer ticks: */ |
| 450 |
|
|
for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) { |
| 451 |
|
|
d->timer_control[i] = TIMER_MODE_PERIODIC; |
| 452 |
|
|
d->timer_load[i] = TIMER_MAX_VAL; |
| 453 |
|
|
} |
| 454 |
|
|
machine_add_tickfunction(devinit->machine, |
| 455 |
|
|
dev_footbridge_tick, d, DEV_FOOTBRIDGE_TICK_SHIFT); |
| 456 |
|
|
|
| 457 |
|
|
devinit->return_ptr = d; |
| 458 |
|
|
return 1; |
| 459 |
|
|
} |
| 460 |
|
|
|
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