src/devices/pci_vt82c586.c

/*
 *  Copyright (C) 2004  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *   
 *
 *  $Id: pci_vt82c586.c,v 1.18 2005/09/27 23:18:32 debug Exp $
 *
 *  VIATECH VT82C586 devices:
 *
 *      vt82c586_isa    PCI->ISA bridge
 *      vt82c586_ide    IDE controller
 *
 *  TODO:  This more or less just a dummy device, so far.
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "bus_pci.h"
#include "device.h"
#include "devices.h"
#include "machine.h"
#include "memory.h"
#include "misc.h"


#define PCI_VENDOR_VIATECH                0x1106  /* VIA Technologies */
#define PCI_PRODUCT_VIATECH_VT82C586_IDE  0x1571  /* VT82C586 (Apollo VP)
                                                     IDE Controller */
#define PCI_PRODUCT_VIATECH_VT82C586_ISA  0x0586  /* VT82C586 (Apollo VP)
                                                     PCI-ISA Bridge */


/*
 *  pci_vt82c586_isa_rr():
 */
uint32_t pci_vt82c586_isa_rr(int reg)
{
        /*  NetBSD reads from 0x04, 0x08, 0x3c, 0x0c, 0x2c during init  */

        switch (reg) {
        case 0x00:
                return PCI_VENDOR_VIATECH +
                    (PCI_PRODUCT_VIATECH_VT82C586_ISA << 16);
        case 0x04:
                return 0xffffffff;      /*  ???  */
        case 0x08:
                /*  Revision 37 or 39  */
                return PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
                    PCI_SUBCLASS_BRIDGE_ISA, 0) + 39;
        case 0x0c:
                /*  Bit 7 of Header-type byte ==> multi-function device  */
                return 0x00800000;
        default:
                return 0;
        }
}


/*
 *  pci_vt82c586_isa_init():
 */
void pci_vt82c586_isa_init(struct machine *machine, struct memory *mem)
{
}


/*
 *  pci_vt82c586_ide_rr():
 */
uint32_t pci_vt82c586_ide_rr(int reg)
{
        /*  NetBSD reads from 0x04, 0x08, 0x3c, 0x0c, 0x2c during init  */

        switch (reg) {
        case 0x00:
                return PCI_VENDOR_VIATECH +
                    (PCI_PRODUCT_VIATECH_VT82C586_IDE << 16);
        case 0x04:
                return 0xffffffff;      /*  ???  */
        case 0x08:
                /*  Possibly not correct:  */
                return PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE,
                    PCI_SUBCLASS_MASS_STORAGE_IDE, 0) + 0x01;
        case 0x40:      /*  APO_IDECONF  */
                /*  channel 0 and 1 enabled  */
                return 0x00000003;
        default:
                return 0;
        }
}


/*
 *  pci_vt82c586_ide_init():
 */
void pci_vt82c586_ide_init(struct machine *machine, struct memory *mem)
{
        /*
         *  TODO: The check for machine type shouldn't be here?
         */

        switch (machine->machine_type) {

        case MACHINE_COBALT:
                /*  irq 14,15 (+8)  */
                device_add(machine, "wdc addr=0x100001f0 irq=22");/* primary  */
                device_add(machine, "wdc addr=0x10000170 irq=23");/* secondary*/
                break;

        case MACHINE_EVBMIPS:
                /*  TODO: Irqs...  */
                device_add(machine, "wdc addr=0x180001f0 irq=22");/* primary  */
                device_add(machine, "wdc addr=0x18000170 irq=23");/* secondary*/
                break;

        case MACHINE_NETWINDER:
                /*  TODO: Irqs...  */
                device_add(machine, "wdc addr=0x7c0001f0 irq=46");/* primary  */
                device_add(machine, "wdc addr=0x7c000170 irq=47");/* secondary*/
                break;

        default:fatal("pci_vt82c586_ide_init(): unimplemented machine type\n");
                exit(1);
        }
}

1	dpavlin	4	/*
2			* Copyright (C) 2004 Anders Gavare. All rights reserved.
3			*
4			* Redistribution and use in source and binary forms, with or without
5			* modification, are permitted provided that the following conditions are met:
6			*
7			* 1. Redistributions of source code must retain the above copyright
8			* notice, this list of conditions and the following disclaimer.
9			* 2. Redistributions in binary form must reproduce the above copyright
10			* notice, this list of conditions and the following disclaimer in the
11			* documentation and/or other materials provided with the distribution.
12			* 3. The name of the author may not be used to endorse or promote products
13			* derived from this software without specific prior written permission.
14			*
15			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25			* SUCH DAMAGE.
26			*
27			*
28	dpavlin	14	* $Id: pci_vt82c586.c,v 1.18 2005/09/27 23:18:32 debug Exp $
29	dpavlin	4	*
30			* VIATECH VT82C586 devices:
31			*
32			* vt82c586_isa PCI->ISA bridge
33			* vt82c586_ide IDE controller
34			*
35			* TODO: This more or less just a dummy device, so far.
36			*/
37
38			#include <stdio.h>
39			#include <stdlib.h>
40			#include <string.h>
41
42	dpavlin	14	#include "bus_pci.h"
43			#include "device.h"
44			#include "devices.h"
45	dpavlin	10	#include "machine.h"
46	dpavlin	4	#include "memory.h"
47			#include "misc.h"
48
49
50			#define PCI_VENDOR_VIATECH 0x1106 /* VIA Technologies */
51			#define PCI_PRODUCT_VIATECH_VT82C586_IDE 0x1571 /* VT82C586 (Apollo VP)
52			IDE Controller */
53			#define PCI_PRODUCT_VIATECH_VT82C586_ISA 0x0586 /* VT82C586 (Apollo VP)
54			PCI-ISA Bridge */
55
56
57			/*
58			* pci_vt82c586_isa_rr():
59			*/
60			uint32_t pci_vt82c586_isa_rr(int reg)
61			{
62			/* NetBSD reads from 0x04, 0x08, 0x3c, 0x0c, 0x2c during init */
63
64			switch (reg) {
65			case 0x00:
66			return PCI_VENDOR_VIATECH +
67			(PCI_PRODUCT_VIATECH_VT82C586_ISA << 16);
68			case 0x04:
69			return 0xffffffff; /* ??? */
70			case 0x08:
71			/* Revision 37 or 39 */
72			return PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
73			PCI_SUBCLASS_BRIDGE_ISA, 0) + 39;
74			case 0x0c:
75			/* Bit 7 of Header-type byte ==> multi-function device */
76			return 0x00800000;
77			default:
78			return 0;
79			}
80			}
81
82
83			/*
84			* pci_vt82c586_isa_init():
85			*/
86			void pci_vt82c586_isa_init(struct machine machine, struct memory mem)
87			{
88			}
89
90
91			/*
92			* pci_vt82c586_ide_rr():
93			*/
94			uint32_t pci_vt82c586_ide_rr(int reg)
95			{
96			/* NetBSD reads from 0x04, 0x08, 0x3c, 0x0c, 0x2c during init */
97
98			switch (reg) {
99			case 0x00:
100			return PCI_VENDOR_VIATECH +
101			(PCI_PRODUCT_VIATECH_VT82C586_IDE << 16);
102			case 0x04:
103			return 0xffffffff; /* ??? */
104			case 0x08:
105			/* Possibly not correct: */
106			return PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE,
107			PCI_SUBCLASS_MASS_STORAGE_IDE, 0) + 0x01;
108			case 0x40: /* APO_IDECONF */
109			/* channel 0 and 1 enabled */
110			return 0x00000003;
111			default:
112			return 0;
113			}
114			}
115
116
117			/*
118			* pci_vt82c586_ide_init():
119			*/
120			void pci_vt82c586_ide_init(struct machine machine, struct memory mem)
121			{
122			/*
123	dpavlin	10	* TODO: The check for machine type shouldn't be here?
124	dpavlin	4	*/
125	dpavlin	10
126			switch (machine->machine_type) {
127
128			case MACHINE_COBALT:
129	dpavlin	14	/* irq 14,15 (+8) */
130			device_add(machine, "wdc addr=0x100001f0 irq=22");/* primary */
131			device_add(machine, "wdc addr=0x10000170 irq=23");/* secondary*/
132	dpavlin	10	break;
133
134			case MACHINE_EVBMIPS:
135			/* TODO: Irqs... */
136	dpavlin	14	device_add(machine, "wdc addr=0x180001f0 irq=22");/* primary */
137			device_add(machine, "wdc addr=0x18000170 irq=23");/* secondary*/
138	dpavlin	10	break;
139
140	dpavlin	14	case MACHINE_NETWINDER:
141			/* TODO: Irqs... */
142			device_add(machine, "wdc addr=0x7c0001f0 irq=46");/* primary */
143			device_add(machine, "wdc addr=0x7c000170 irq=47");/* secondary*/
144			break;
145
146	dpavlin	10	default:fatal("pci_vt82c586_ide_init(): unimplemented machine type\n");
147			exit(1);
148			}
149	dpavlin	4	}
150