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dpavlin |
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/* |
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* Copyright (C) 2004-2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_sgi_ip22.c,v 1.24 2005/02/22 05:52:58 debug Exp $ |
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* |
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* SGI IP22 stuff. |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include "cpu.h" |
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#include "devices.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "imcreg.h" |
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#define SGI_IP22_TICK_SHIFT 14 |
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/* |
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* dev_sgi_ip22_tick(): |
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*/ |
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void dev_sgi_ip22_tick(struct cpu *cpu, void *extra) |
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{ |
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struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra; |
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if (d->reg[0x38 / 4] != 0) |
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d->reg[0x38 / 4] --; |
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} |
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/* |
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* dev_sgi_ip22_imc_access(): |
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* |
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* The memory controller (?). |
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*/ |
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int dev_sgi_ip22_imc_access(struct cpu *cpu, struct memory *mem, |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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{ |
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struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra; |
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uint64_t idata = 0, odata = 0; |
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int regnr; |
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idata = memory_readmax64(cpu, data, len); |
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regnr = relative_addr / sizeof(uint32_t); |
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if (writeflag == MEM_WRITE) |
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d->imc_reg[regnr] = idata; |
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else |
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odata = d->imc_reg[regnr]; |
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switch (relative_addr) { |
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case (IMC_CPUCTRL0 - IP22_IMC_BASE): |
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if (writeflag == MEM_WRITE) { |
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/* debug("[ sgi_ip22_imc: write to " |
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"IMC_CPUCTRL0, data=0x%08x ]\n", (int)idata); */ |
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} else { |
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/* debug("[ sgi_ip22_imc: read from IMC_CPUCTRL0, " |
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"data=0x%08x ]\n", (int)odata); */ |
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} |
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break; |
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case (IMC_SYSID - IP22_IMC_BASE): |
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if (writeflag == MEM_WRITE) { |
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debug("[ sgi_ip22_imc: unimplemented write " |
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"IMC_SYSID, data=0x%08x ]\n", (int)idata); |
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} else { |
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/* Lowest 4 bits are the revision bits. */ |
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odata = 3; /* + IMC_SYSID_HAVEISA; */ |
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/* debug("[ sgi_ip22_imc: read from IMC_SYSID, " |
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"data=0x%08x ]\n", (int)odata); */ |
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} |
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break; |
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case (IMC_WDOG - IP22_IMC_BASE): |
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if (writeflag == MEM_WRITE) { |
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/* debug("[ sgi_ip22_imc: write to IMC_WDOG, " |
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"data=0x%08x ]\n", (int)idata); */ |
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} else { |
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/* debug("[ sgi_ip22_imc: read from IMC_WDOG, " |
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"data=0x%08x ]\n", (int)odata); */ |
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} |
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break; |
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case (IMC_MEMCFG0 - IP22_IMC_BASE): |
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if (writeflag == MEM_WRITE) { |
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debug("[ sgi_ip22_imc: unimplemented write " |
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"IMC_MEMCFG0, data=0x%08x ]\n", (int)idata); |
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} else { |
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odata = 0x3100 + (0x8000000 >> 22); /* ? TODO */ |
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/* debug("[ sgi_ip22_imc: read from IMC_MEMCFG0," |
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" data=0x%08x ]\n", (int)odata); */ |
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} |
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break; |
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case (IMC_MEMCFG1 - IP22_IMC_BASE): |
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if (writeflag == MEM_WRITE) { |
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debug("[ sgi_ip22_imc: unimplemented write " |
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"IMC_MEMCFG1, data=0x%08x ]\n", (int)idata); |
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} else { |
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odata = 0; |
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/* debug("[ sgi_ip22_imc: read from IMC_MEMCFG1, " |
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"data=0x%08x ]\n", (int)odata); */ |
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} |
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break; |
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case (IMC_EEPROM - IP22_IMC_BASE): |
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/* |
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* The IP22 prom tries to access this during bootup, |
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* but I have no idea how it works. |
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*/ |
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if (writeflag == MEM_WRITE) { |
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debug("[ sgi_ip22_imc: write to IMC_EEPROM, data=" |
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"0x%08x ]\n", (int)idata); |
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} else { |
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odata = random() & 0x1e; |
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debug("[ sgi_ip22_imc: read from IMC_WDOG, " |
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"data=0x%08x ]\n", (int)odata); |
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} |
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break; |
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default: |
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if (writeflag == MEM_WRITE) { |
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debug("[ sgi_ip22_imc: unimplemented write to " |
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"address 0x%x, data=0x%08x ]\n", |
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(int)relative_addr, (int)idata); |
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} else { |
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debug("[ sgi_ip22_imc: unimplemented read from " |
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"address 0x%x, data=0x%08x ]\n", |
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(int)relative_addr, (int)odata); |
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} |
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} |
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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return 1; |
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} |
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/* |
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* dev_sgi_ip22_unknown_access(): |
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* |
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* A so far unknown device, used by the IP22 prom during startup. |
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*/ |
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int dev_sgi_ip22_unknown_access(struct cpu *cpu, struct memory *mem, |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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{ |
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struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra; |
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uint64_t idata = 0, odata = 0; |
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idata = memory_readmax64(cpu, data, len); |
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switch (relative_addr) { |
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case 0x04: |
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if (writeflag == MEM_WRITE) { |
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debug("[ sgi_ip22_unknown: write to address 0x%x," |
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" data=0x%08x ]\n", (int)relative_addr, (int)idata); |
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} else { |
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odata = d->unknown_timer; |
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d->unknown_timer += 100; |
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debug("[ sgi_ip22_unknown: read from address 0x%x, " |
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"data=0x%08x ]\n", (int)relative_addr, (int)odata); |
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} |
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break; |
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default: |
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if (writeflag == MEM_WRITE) { |
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debug("[ sgi_ip22_unknown: unimplemented write to " |
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"address 0x%x, data=0x%08x ]\n", |
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(int)relative_addr, (int)idata); |
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} else { |
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debug("[ sgi_ip22_unknown: unimplemented read from " |
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"address 0x%x, data=0x%08x ]\n", |
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(int)relative_addr, (int)odata); |
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} |
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} |
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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return 1; |
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} |
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/* |
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* dev_sgi_ip22_unknown2_access(): |
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* |
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* A so far unknown device, used by the IP22 prom during startup. |
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*/ |
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int dev_sgi_ip22_unknown2_access(struct cpu *cpu, struct memory *mem, |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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{ |
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struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra; |
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uint64_t idata = 0, odata = 0; |
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int regnr; |
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idata = memory_readmax64(cpu, data, len); |
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regnr = relative_addr / sizeof(uint32_t); |
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if (writeflag == MEM_WRITE) |
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d->unknown2_reg[regnr] = idata; |
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else |
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odata = d->unknown2_reg[regnr]; |
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switch (relative_addr) { |
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default: |
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if (writeflag == MEM_WRITE) { |
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debug("[ sgi_ip22_unknown2: unimplemented write " |
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"to address 0x%x, data=0x%08x ]\n", |
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(int)relative_addr, (int)idata); |
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} else { |
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debug("[ sgi_ip22_unknown2: unimplemented read from " |
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"address 0x%x, data=0x%08x ]\n", |
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(int)relative_addr, (int)odata); |
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} |
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} |
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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return 1; |
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} |
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| 251 |
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/* |
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* dev_sgi_ip22_sysid_access(): |
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*/ |
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int dev_sgi_ip22_sysid_access(struct cpu *cpu, struct memory *mem, |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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{ |
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struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra; |
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uint64_t idata = 0, odata = 0; |
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| 261 |
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idata = memory_readmax64(cpu, data, len); |
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| 263 |
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if (writeflag == MEM_WRITE) { |
| 264 |
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debug("[ sgi_ip22_sysid: write to address 0x%x, " |
| 265 |
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"data=0x%08x ]\n", (int)relative_addr, (int)idata); |
| 266 |
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} else { |
| 267 |
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/* |
| 268 |
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* According to NetBSD's sgimips/ip22.c: |
| 269 |
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* |
| 270 |
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* printf("IOC rev %d, machine %s, board rev %d\n", |
| 271 |
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* (sysid >> 5) & 0x07, |
| 272 |
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* (sysid & 1) ? "Indigo2 (Fullhouse)" : "Indy (Guiness)", |
| 273 |
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* (sysid >> 1) & 0x0f); |
| 274 |
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*/ |
| 275 |
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| 276 |
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/* IOC rev 1, Guiness, board rev 3: */ |
| 277 |
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odata = (1 << 5) + (3 << 1) + (d->guiness_flag? 0 : 1); |
| 278 |
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| 279 |
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debug("[ sgi_ip22_sysid: read from address 0x%x, data=" |
| 280 |
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"0x%08x ]\n", (int)relative_addr, (int)odata); |
| 281 |
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} |
| 282 |
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| 283 |
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if (writeflag == MEM_READ) |
| 284 |
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memory_writemax64(cpu, data, len, odata); |
| 285 |
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| 286 |
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return 1; |
| 287 |
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} |
| 288 |
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| 289 |
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| 290 |
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/* |
| 291 |
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* dev_sgi_ip22_access(): |
| 292 |
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* |
| 293 |
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* Returns 1 if ok, 0 on error. |
| 294 |
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*/ |
| 295 |
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int dev_sgi_ip22_access(struct cpu *cpu, struct memory *mem, |
| 296 |
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uint64_t relative_addr, unsigned char *data, size_t len, |
| 297 |
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int writeflag, void *extra) |
| 298 |
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{ |
| 299 |
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struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra; |
| 300 |
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uint64_t idata = 0, odata = 0; |
| 301 |
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int regnr; |
| 302 |
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| 303 |
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idata = memory_readmax64(cpu, data, len); |
| 304 |
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regnr = relative_addr / sizeof(uint32_t); |
| 305 |
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| 306 |
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if (writeflag == MEM_WRITE) |
| 307 |
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d->reg[regnr] = idata; |
| 308 |
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else |
| 309 |
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odata = d->reg[regnr]; |
| 310 |
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|
| 311 |
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/* Read from/write to the sgi_ip22: */ |
| 312 |
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switch (relative_addr) { |
| 313 |
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case 0x00: /* local0 irq stat */ |
| 314 |
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if (writeflag == MEM_WRITE) { |
| 315 |
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debug("[ sgi_ip22: write to local0 IRQ STAT, " |
| 316 |
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"data=0x%llx ]\n", (long long)idata); |
| 317 |
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} else { |
| 318 |
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debug("[ sgi_ip22: read from local0 IRQ STAT, " |
| 319 |
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"data=0x%llx ]\n", (long long)odata); |
| 320 |
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} |
| 321 |
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break; |
| 322 |
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case 0x04: /* local0 irq mask */ |
| 323 |
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if (writeflag == MEM_WRITE) { |
| 324 |
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/* |
| 325 |
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* Ugly hack: if an interrupt is asserted, and someone |
| 326 |
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* writes to this mask register, the interrupt should |
| 327 |
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* be masked. That is, sgi_ip22_interrupt() in |
| 328 |
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* src/machine.c has to be called to deal with this. |
| 329 |
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* The ugly solution I choose here is to deassert |
| 330 |
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* some interrupt which should never be used anyway. |
| 331 |
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* (TODO: Fix this.) |
| 332 |
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*/ |
| 333 |
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cpu_interrupt_ack(cpu, 8 + 63); |
| 334 |
|
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debug("[ sgi_ip22: write to local0 IRQ MASK, " |
| 335 |
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"data=0x%llx ]\n", (long long)idata); |
| 336 |
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} else { |
| 337 |
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debug("[ sgi_ip22: read from local0 IRQ MASK, " |
| 338 |
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"data=0x%llx ]\n", (long long)odata); |
| 339 |
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} |
| 340 |
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break; |
| 341 |
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case 0x08: /* local1 irq stat */ |
| 342 |
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if (writeflag == MEM_WRITE) { |
| 343 |
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debug("[ sgi_ip22: write to local1 IRQ STAT, " |
| 344 |
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"data=0x%llx ]\n", (long long)idata); |
| 345 |
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} else { |
| 346 |
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debug("[ sgi_ip22: read from local1 IRQ STAT, " |
| 347 |
|
|
"data=0x%llx ]\n", (long long)odata); |
| 348 |
|
|
} |
| 349 |
|
|
break; |
| 350 |
|
|
case 0x0c: /* local1 irq mask */ |
| 351 |
|
|
if (writeflag == MEM_WRITE) { |
| 352 |
|
|
/* See commen above, about local0 irq mask. */ |
| 353 |
|
|
cpu_interrupt_ack(cpu, 8 + 63); |
| 354 |
|
|
debug("[ sgi_ip22: write to local1 IRQ MASK, " |
| 355 |
|
|
"data=0x%llx ]\n", (long long)idata); |
| 356 |
|
|
} else { |
| 357 |
|
|
debug("[ sgi_ip22: read from local1 IRQ MASK, " |
| 358 |
|
|
"data=0x%llx ]\n", (long long)odata); |
| 359 |
|
|
} |
| 360 |
|
|
break; |
| 361 |
|
|
case 0x10: |
| 362 |
|
|
if (writeflag == MEM_WRITE) { |
| 363 |
|
|
debug("[ sgi_ip22: write to mappable IRQ STAT, " |
| 364 |
|
|
"data=0x%llx ]\n", (long long)idata); |
| 365 |
|
|
} else { |
| 366 |
|
|
debug("[ sgi_ip22: read from mappable IRQ STAT, " |
| 367 |
|
|
"data=0x%llx ]\n", (long long)odata); |
| 368 |
|
|
} |
| 369 |
|
|
break; |
| 370 |
|
|
case 0x14: |
| 371 |
|
|
if (writeflag == MEM_WRITE) { |
| 372 |
|
|
debug("[ sgi_ip22: write to mappable local0 IRQ " |
| 373 |
|
|
"MASK, data=0x%llx ]\n", (long long)idata); |
| 374 |
|
|
} else { |
| 375 |
|
|
debug("[ sgi_ip22: read from mappable local0 IRQ " |
| 376 |
|
|
"MASK, data=0x%llx ]\n", (long long)odata); |
| 377 |
|
|
} |
| 378 |
|
|
break; |
| 379 |
|
|
case 0x18: |
| 380 |
|
|
if (writeflag == MEM_WRITE) { |
| 381 |
|
|
debug("[ sgi_ip22: write to mappable local1 IRQ " |
| 382 |
|
|
"MASK, data=0x%llx ]\n", (long long)idata); |
| 383 |
|
|
} else { |
| 384 |
|
|
debug("[ sgi_ip22: read from mappable local1 IRQ " |
| 385 |
|
|
"MASK, data=0x%llx ]\n", (long long)odata); |
| 386 |
|
|
} |
| 387 |
|
|
break; |
| 388 |
|
|
case 0x38: /* timer count */ |
| 389 |
|
|
if (writeflag == MEM_WRITE) { |
| 390 |
|
|
/* Two byte values are written to this address, |
| 391 |
|
|
sequentially... TODO */ |
| 392 |
|
|
} else { |
| 393 |
|
|
/* The timer is decreased by the tick function. */ |
| 394 |
|
|
} |
| 395 |
|
|
break; |
| 396 |
|
|
case 0x3b: /* ? */ |
| 397 |
|
|
odata = random(); |
| 398 |
|
|
break; |
| 399 |
|
|
case 0x3c: /* timer control */ |
| 400 |
|
|
break; |
| 401 |
|
|
case 0x3f: /* ? */ |
| 402 |
|
|
odata = random(); |
| 403 |
|
|
break; |
| 404 |
|
|
default: |
| 405 |
|
|
if (writeflag == MEM_WRITE) { |
| 406 |
|
|
debug("[ sgi_ip22: unimplemented write to address " |
| 407 |
|
|
"0x%x, data=0x%02x ]\n", (int)relative_addr, |
| 408 |
|
|
(int)idata); |
| 409 |
|
|
} else { |
| 410 |
|
|
debug("[ sgi_ip22: unimplemented read from address " |
| 411 |
|
|
"0x%llx ]\n", (long long)relative_addr); |
| 412 |
|
|
} |
| 413 |
|
|
} |
| 414 |
|
|
|
| 415 |
|
|
if (writeflag == MEM_READ) |
| 416 |
|
|
memory_writemax64(cpu, data, len, odata); |
| 417 |
|
|
|
| 418 |
|
|
return 1; |
| 419 |
|
|
} |
| 420 |
|
|
|
| 421 |
|
|
|
| 422 |
|
|
/* |
| 423 |
|
|
* dev_sgi_ip22_init(): |
| 424 |
|
|
*/ |
| 425 |
|
|
struct sgi_ip22_data *dev_sgi_ip22_init(struct machine *machine, |
| 426 |
|
|
struct memory *mem, uint64_t baseaddr, int guiness_flag) |
| 427 |
|
|
{ |
| 428 |
|
|
struct sgi_ip22_data *d = malloc(sizeof(struct sgi_ip22_data)); |
| 429 |
|
|
if (d == NULL) { |
| 430 |
|
|
fprintf(stderr, "out of memory\n"); |
| 431 |
|
|
exit(1); |
| 432 |
|
|
} |
| 433 |
|
|
memset(d, 0, sizeof(struct sgi_ip22_data)); |
| 434 |
|
|
d->guiness_flag = guiness_flag; |
| 435 |
|
|
|
| 436 |
|
|
memory_device_register(mem, "sgi_ip22", baseaddr, DEV_SGI_IP22_LENGTH, |
| 437 |
|
|
dev_sgi_ip22_access, (void *)d, MEM_DEFAULT, NULL); |
| 438 |
|
|
memory_device_register(mem, "sgi_ip22_sysid", 0x1fbd9858, 0x8, |
| 439 |
|
|
dev_sgi_ip22_sysid_access, (void *)d, MEM_DEFAULT, NULL); |
| 440 |
|
|
memory_device_register(mem, "sgi_ip22_imc", IP22_IMC_BASE, |
| 441 |
|
|
DEV_SGI_IP22_IMC_LENGTH, dev_sgi_ip22_imc_access, (void *)d, |
| 442 |
|
|
MEM_DEFAULT, NULL); |
| 443 |
|
|
memory_device_register(mem, "sgi_ip22_unknown", 0x1fa01000, 0x10, |
| 444 |
|
|
dev_sgi_ip22_unknown_access, (void *)d, MEM_DEFAULT, NULL); |
| 445 |
|
|
memory_device_register(mem, "sgi_ip22_unknown2", IP22_UNKNOWN2_BASE, |
| 446 |
|
|
DEV_SGI_IP22_UNKNOWN2_LENGTH, dev_sgi_ip22_unknown2_access, |
| 447 |
|
|
(void *)d, MEM_DEFAULT, NULL); |
| 448 |
|
|
|
| 449 |
|
|
machine_add_tickfunction(machine, dev_sgi_ip22_tick, d, |
| 450 |
|
|
SGI_IP22_TICK_SHIFT); |
| 451 |
|
|
|
| 452 |
|
|
return d; |
| 453 |
|
|
} |
| 454 |
|
|
|
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