src/cpus/cpu_x86_instr.c

/*
 *  Copyright (C) 2005  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_x86_instr.c,v 1.1 2005/08/29 14:36:41 debug Exp $
 *
 *  x86/amd64 instructions.
 *
 *  Individual functions should keep track of cpu->n_translated_instrs. Since
 *  x86 uses variable length instructions, cpu->cd.x86.next_ic must also be
 *  increased by the number of "instruction slots" that were executed. (I.e.
 *  if an instruction occupying 5 bytes was executed, then next_ic should be
 *  increased by 5.)
 *
 *  (n_translated_instrs is automatically increased by 1 for each function
 *  call. If no instruction was executed, then it should be decreased. If, say, 
 *  4 instructions were combined into one function and executed, then it should 
 *  be increased by 3.)
 */


/*
 *  nop:  Do nothing.
 */
X(nop)
{
        cpu->cd.x86.next_ic ++;
}


/*****************************************************************************/


X(end_of_page)
{
        /*  Update the PC:  (offset 0, but on the next page)  */
        cpu->pc &= ~(X86_IC_ENTRIES_PER_PAGE-1);
        cpu->pc += X86_IC_ENTRIES_PER_PAGE;

        /*  Find the new physical page and update the translation pointers:  */
        x86_pc_to_pointers(cpu);

        /*  end_of_page doesn't count as an executed instruction:  */
        cpu->n_translated_instrs --;
}


/*****************************************************************************/


/*
 *  x86_combine_instructions():
 *
 *  Combine two or more instructions, if possible, into a single function call.
 */
void COMBINE_INSTRUCTIONS(struct cpu *cpu, struct x86_instr_call *ic,
        uint64_t addr)
{
        int n_back;
        n_back = addr & (X86_IC_ENTRIES_PER_PAGE-1);

        if (n_back >= 1) {
                /*  TODO  */
        }

        /*  TODO: Combine forward as well  */
}


/*****************************************************************************/


/*
 *  x86_instr_to_be_translated():
 *
 *  Translate an instruction word into an x86_instr_call. ic is filled in with
 *  valid data for the translated instruction, or a "nothing" instruction if
 *  there was a translation failure. The newly translated instruction is then
 *  executed.
 */
X(to_be_translated)
{
        uint64_t addr, low_pc;
        unsigned char *page;
        int main_opcode;
        unsigned char ib[17];
        void (*samepage_function)(struct cpu *, struct x86_instr_call *);

        /*  Figure out the (virtual) address of the instruction:  */
        low_pc = ((size_t)ic - (size_t)cpu->cd.x86.cur_ic_page)
            / sizeof(struct x86_instr_call);
        addr = cpu->pc & ~(X86_IC_ENTRIES_PER_PAGE-1);
        addr += low_pc;
        cpu->pc = addr;

        if (!cpu->cd.x86.descr_cache[X86_S_CS].valid) {
                fatal("x86_cpu_run_instr(): Invalid CS descriptor?\n");
                exit(1);
        }

        cpu->cd.x86.cursegment = X86_S_CS;
        cpu->cd.x86.seg_override = 0;

        /*  Read the instruction word from memory:  */
        page = cpu->cd.x86.host_load[addr >> 12];

        if (page != NULL) {
                /*  fatal("TRANSLATION HIT!\n");  */
                ib[0] = page[addr & 0xfff];
        } else {
                /*  fatal("TRANSLATION MISS!\n");  */
                if (!cpu->memory_rw(cpu, cpu->mem, addr, &ib[0],
                    1, MEM_READ, CACHE_INSTRUCTION)) {
                        fatal("to_be_translated(): read failed: TODO\n");
                        goto bad;
                }
        }

        fatal("X86: ib[0] = 0x%02x\n", ib[0]);


#define DYNTRANS_TO_BE_TRANSLATED_HEAD
#include "cpu_dyntrans.c"
#undef  DYNTRANS_TO_BE_TRANSLATED_HEAD


        /*
         *  Translate the instruction:
         */


/*  TODO  */


        main_opcode = ib[0];

        switch (main_opcode) {

        default:goto bad;
        }


#define DYNTRANS_TO_BE_TRANSLATED_TAIL
#include "cpu_dyntrans.c" 
#undef  DYNTRANS_TO_BE_TRANSLATED_TAIL
}

1	/*
2	* Copyright (C) 2005 Anders Gavare. All rights reserved.
3	*
4	* Redistribution and use in source and binary forms, with or without
5	* modification, are permitted provided that the following conditions are met:
6	*
7	* 1. Redistributions of source code must retain the above copyright
8	* notice, this list of conditions and the following disclaimer.
9	* 2. Redistributions in binary form must reproduce the above copyright
10	* notice, this list of conditions and the following disclaimer in the
11	* documentation and/or other materials provided with the distribution.
12	* 3. The name of the author may not be used to endorse or promote products
13	* derived from this software without specific prior written permission.
14	*
15	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25	* SUCH DAMAGE.
26	*
27	*
28	* $Id: cpu_x86_instr.c,v 1.1 2005/08/29 14:36:41 debug Exp $
29	*
30	* x86/amd64 instructions.
31	*
32	* Individual functions should keep track of cpu->n_translated_instrs. Since
33	* x86 uses variable length instructions, cpu->cd.x86.next_ic must also be
34	* increased by the number of "instruction slots" that were executed. (I.e.
35	* if an instruction occupying 5 bytes was executed, then next_ic should be
36	* increased by 5.)
37	*
38	* (n_translated_instrs is automatically increased by 1 for each function
39	* call. If no instruction was executed, then it should be decreased. If, say,
40	* 4 instructions were combined into one function and executed, then it should
41	* be increased by 3.)
42	*/
43
44
45	/*
46	* nop: Do nothing.
47	*/
48	X(nop)
49	{
50	cpu->cd.x86.next_ic ++;
51	}
52
53
54	/*****************************************************************************/
55
56
57	X(end_of_page)
58	{
59	/* Update the PC: (offset 0, but on the next page) */
60	cpu->pc &= ~(X86_IC_ENTRIES_PER_PAGE-1);
61	cpu->pc += X86_IC_ENTRIES_PER_PAGE;
62
63	/* Find the new physical page and update the translation pointers: */
64	x86_pc_to_pointers(cpu);
65
66	/* end_of_page doesn't count as an executed instruction: */
67	cpu->n_translated_instrs --;
68	}
69
70
71	/*****************************************************************************/
72
73
74	/*
75	* x86_combine_instructions():
76	*
77	* Combine two or more instructions, if possible, into a single function call.
78	*/
79	void COMBINE_INSTRUCTIONS(struct cpu cpu, struct x86_instr_call ic,
80	uint64_t addr)
81	{
82	int n_back;
83	n_back = addr & (X86_IC_ENTRIES_PER_PAGE-1);
84
85	if (n_back >= 1) {
86	/* TODO */
87	}
88
89	/* TODO: Combine forward as well */
90	}
91
92
93	/*****************************************************************************/
94
95
96	/*
97	* x86_instr_to_be_translated():
98	*
99	* Translate an instruction word into an x86_instr_call. ic is filled in with
100	* valid data for the translated instruction, or a "nothing" instruction if
101	* there was a translation failure. The newly translated instruction is then
102	* executed.
103	*/
104	X(to_be_translated)
105	{
106	uint64_t addr, low_pc;
107	unsigned char *page;
108	int main_opcode;
109	unsigned char ib[17];
110	void (samepage_function)(struct cpu , struct x86_instr_call *);
111
112	/* Figure out the (virtual) address of the instruction: */
113	low_pc = ((size_t)ic - (size_t)cpu->cd.x86.cur_ic_page)
114	/ sizeof(struct x86_instr_call);
115	addr = cpu->pc & ~(X86_IC_ENTRIES_PER_PAGE-1);
116	addr += low_pc;
117	cpu->pc = addr;
118
119	if (!cpu->cd.x86.descr_cache[X86_S_CS].valid) {
120	fatal("x86_cpu_run_instr(): Invalid CS descriptor?\n");
121	exit(1);
122	}
123
124	cpu->cd.x86.cursegment = X86_S_CS;
125	cpu->cd.x86.seg_override = 0;
126
127	/* Read the instruction word from memory: */
128	page = cpu->cd.x86.host_load[addr >> 12];
129
130	if (page != NULL) {
131	/* fatal("TRANSLATION HIT!\n"); */
132	ib[0] = page[addr & 0xfff];
133	} else {
134	/* fatal("TRANSLATION MISS!\n"); */
135	if (!cpu->memory_rw(cpu, cpu->mem, addr, &ib[0],
136	1, MEM_READ, CACHE_INSTRUCTION)) {
137	fatal("to_be_translated(): read failed: TODO\n");
138	goto bad;
139	}
140	}
141
142	fatal("X86: ib[0] = 0x%02x\n", ib[0]);
143
144
145	#define DYNTRANS_TO_BE_TRANSLATED_HEAD
146	#include "cpu_dyntrans.c"
147	#undef DYNTRANS_TO_BE_TRANSLATED_HEAD
148
149
150	/*
151	* Translate the instruction:
152	*/
153
154
155	/* TODO */
156
157
158	main_opcode = ib[0];
159
160	switch (main_opcode) {
161
162	default:goto bad;
163	}
164
165
166	#define DYNTRANS_TO_BE_TRANSLATED_TAIL
167	#include "cpu_dyntrans.c"
168	#undef DYNTRANS_TO_BE_TRANSLATED_TAIL
169	}
170