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/* |
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* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: memory_mips_v2p.c,v 1.4 2005/02/18 07:11:56 debug Exp $ |
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* |
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* Included from memory.c. |
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*/ |
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|
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|
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/* |
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* translate_address(): |
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* |
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* Don't call this function is userland_emul is non-NULL, or cpu is NULL. |
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* |
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* TODO: vpn2 is a bad name for R2K/R3K, as it is the actual framenumber. |
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* |
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* Return values: |
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* 0 Failure |
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* 1 Success, the page is readable only |
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* 2 Success, the page is read/write |
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*/ |
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int TRANSLATE_ADDRESS(struct cpu *cpu, uint64_t vaddr, |
| 47 |
uint64_t *return_addr, int flags) |
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{ |
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int writeflag = flags & FLAG_WRITEFLAG? MEM_WRITE : MEM_READ; |
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int no_exceptions = flags & FLAG_NOEXCEPTIONS; |
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int instr = flags & FLAG_INSTR; |
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int ksu, use_tlb, status, i; |
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uint64_t vaddr_vpn2=0, vaddr_asid=0; |
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int exccode, tlb_refill; |
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struct mips_coproc *cp0; |
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int bintrans_cached = cpu->machine->bintrans_enable; |
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|
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#ifdef V2P_MMU3K |
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const int x_64 = 0; |
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const int n_tlbs = 64; |
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const int pmask = 0xfff; |
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#else |
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#ifdef V2P_MMU10K |
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const uint64_t vpn2_mask = ENTRYHI_VPN2_MASK_R10K; |
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#else |
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#ifdef V2P_MMU4100 |
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/* This is ugly */ |
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const uint64_t vpn2_mask = ENTRYHI_VPN2_MASK | 0x1800; |
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#else |
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const uint64_t vpn2_mask = ENTRYHI_VPN2_MASK; |
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#endif |
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#endif |
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int x_64; /* non-zero for 64-bit address space accesses */ |
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int pageshift, n_tlbs; |
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int pmask; |
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#ifdef V2P_MMU4100 |
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const int pagemask_mask = PAGEMASK_MASK_R4100; |
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const int pagemask_shift = PAGEMASK_SHIFT_R4100; |
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const int pfn_shift = 10; |
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#else |
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const int pagemask_mask = PAGEMASK_MASK; |
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const int pagemask_shift = PAGEMASK_SHIFT; |
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const int pfn_shift = 12; |
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#endif |
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#endif /* !V2P_MMU3K */ |
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|
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|
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#ifdef USE_TINY_CACHE |
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/* |
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* Check the tiny translation cache first: |
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* |
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* Only userland addresses are checked, because other addresses |
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* are probably better of being statically translated, or through |
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* the TLB. (Note: When running with 64-bit addresses, this |
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* will still produce the correct result. At worst, we check the |
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* cache in vain, but the result should still be correct.) |
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*/ |
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if (!bintrans_cached && |
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(vaddr & 0xc0000000ULL) != 0x80000000ULL) { |
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int i, wf = 1 + (writeflag == MEM_WRITE); |
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uint64_t vaddr_shift_12 = vaddr >> 12; |
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|
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if (instr) { |
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/* Code: */ |
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for (i=0; i<N_TRANSLATION_CACHE_INSTR; i++) { |
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if (cpu->cd.mips.translation_cache_instr[i].wf |
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>= wf && vaddr_shift_12 == (cpu->cd.mips. |
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translation_cache_instr[i].vaddr_pfn)) { |
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*return_addr = cpu->cd.mips. |
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translation_cache_instr[i].paddr |
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| (vaddr & 0xfff); |
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return cpu->cd.mips. |
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translation_cache_instr[i].wf; |
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} |
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} |
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} else { |
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/* Data: */ |
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for (i=0; i<N_TRANSLATION_CACHE_DATA; i++) { |
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if (cpu->cd.mips.translation_cache_data[i].wf |
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>= wf && vaddr_shift_12 == (cpu->cd.mips. |
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translation_cache_data[i].vaddr_pfn)) { |
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*return_addr = cpu->cd.mips. |
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translation_cache_data[i].paddr |
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| (vaddr & 0xfff); |
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return cpu->cd.mips. |
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translation_cache_data[i].wf; |
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} |
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} |
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} |
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} |
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#endif |
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|
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exccode = -1; |
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tlb_refill = 1; |
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|
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/* Cached values: */ |
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cp0 = cpu->cd.mips.coproc[0]; |
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status = cp0->reg[COP0_STATUS]; |
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|
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/* |
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* R4000 Address Translation: |
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* |
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* An address may be in one of the kernel segments, that |
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* are directly mapped, or the address can go through the |
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* TLBs to be turned into a physical address. |
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* |
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* KSU: EXL: ERL: X: Name: Range: |
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* ---- ---- ---- -- ----- ------ |
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* |
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* 10 0 0 0 useg 0 - 0x7fffffff (2GB) (via TLB) |
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* 10 0 0 1 xuseg 0 - 0xffffffffff (1TB) (via TLB) |
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* |
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* 01 0 0 0 suseg 0 - 0x7fffffff (2GB via TLB) |
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* 01 0 0 0 ssseg 0xc0000000 - 0xdfffffff (0.5 GB via TLB) |
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* 01 0 0 1 xsuseg 0 - 0xffffffffff (1TB) (via TLB) |
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* 01 0 0 1 xsseg 0x4000000000000000 - 0x400000ffffffffff |
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* (1TB) (via TLB) |
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* 01 0 0 1 csseg 0xffffffffc0000000 - 0xffffffffdfffffff |
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* (0.5TB) (via TLB) |
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* |
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* 00 x x 0 kuseg 0 - 0x7fffffff (2GB) (via TLB) (*) |
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* 00 x x 0 kseg0 0x80000000 - 0x9fffffff (0.5GB) |
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* unmapped, cached |
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* 00 x x 0 kseg1 0xa0000000 - 0xbfffffff (0.5GB) |
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* unmapped, uncached |
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* 00 x x 0 ksseg 0xc0000000 - 0xdfffffff (0.5GB) |
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* (via TLB) |
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* 00 x x 0 kseg3 0xe0000000 - 0xffffffff (0.5GB) |
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* (via TLB) |
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* 00 x x 1 xksuseg 0 - 0xffffffffff (1TB) (via TLB) (*) |
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* 00 x x 1 xksseg 0x4000000000000000 - 0x400000ffffffffff |
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* (1TB) (via TLB) |
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* 00 x x 1 xkphys 0x8000000000000000 - 0xbfffffffffffffff |
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* todo |
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* 00 x x 1 xkseg 0xc000000000000000 - 0xc00000ff7fffffff |
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* todo |
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* 00 x x 1 ckseg0 0xffffffff80000000 - 0xffffffff9fffffff |
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* like kseg0 |
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* 00 x x 1 ckseg1 0xffffffffa0000000 - 0xffffffffbfffffff |
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* like kseg1 |
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* 00 x x 1 cksseg 0xffffffffc0000000 - 0xffffffffdfffffff |
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* like ksseg |
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* 00 x x 1 ckseg3 0xffffffffe0000000 - 0xffffffffffffffff |
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* like kseg2 |
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* |
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* (*) = if ERL=1 then kuseg is not via TLB, but unmapped, |
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* uncached physical memory. |
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* |
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* (KSU==0 or EXL=1 or ERL=1 is enough to use k*seg*.) |
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* |
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* An invalid address causes an Address Error. |
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* |
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* See chapter 4, page 96, in the R4000 manual for more info! |
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*/ |
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|
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#ifdef V2P_MMU3K |
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if (status & MIPS1_SR_KU_CUR) |
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ksu = KSU_USER; |
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else |
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ksu = KSU_KERNEL; |
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|
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/* These are needed later: */ |
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vaddr_asid = cp0->reg[COP0_ENTRYHI] & R2K3K_ENTRYHI_ASID_MASK; |
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vaddr_vpn2 = vaddr & R2K3K_ENTRYHI_VPN_MASK; |
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#else |
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/* |
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* R4000 and others: |
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* |
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* kx,sx,ux = 0 for 32-bit addressing, |
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* 1 for 64-bit addressing. |
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*/ |
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n_tlbs = cpu->cd.mips.cpu_type.nr_of_tlb_entries; |
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|
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ksu = (status & STATUS_KSU_MASK) >> STATUS_KSU_SHIFT; |
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if (status & (STATUS_EXL | STATUS_ERL)) |
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ksu = KSU_KERNEL; |
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|
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/* Assume KSU_USER. */ |
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x_64 = status & STATUS_UX; |
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|
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if (ksu == KSU_KERNEL) |
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x_64 = status & STATUS_KX; |
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else if (ksu == KSU_SUPERVISOR) |
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x_64 = status & STATUS_SX; |
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|
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/* This suppresses a compiler warning: */ |
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pageshift = 12; |
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|
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/* |
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* Physical addressing on R10000 etc: |
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* |
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* TODO: Probably only accessible in kernel mode. |
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* |
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* 0x9000000080000000 = disable L2 cache (?) |
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* TODO: Make this correct. |
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*/ |
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if ((vaddr >> 62) == 0x2) { |
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/* |
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* On IP30, addresses such as 0x900000001f600050 are used, |
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* but also things like 0x90000000a0000000. (TODO) |
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* |
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* On IP27 (and probably others), addresses such as |
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* 0x92... and 0x96... have to do with NUMA stuff. |
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*/ |
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*return_addr = vaddr & (((uint64_t)1 << 44) - 1); |
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return 2; |
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} |
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|
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/* This is needed later: */ |
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vaddr_asid = cp0->reg[COP0_ENTRYHI] & ENTRYHI_ASID; |
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/* vpn2 depends on pagemask, which is not fixed on R4000 */ |
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#endif |
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|
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|
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if (vaddr <= 0x7fffffff) |
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use_tlb = 1; |
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else { |
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#if 1 |
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/* TODO: This should be removed, but it seems that other |
| 260 |
bugs are triggered. */ |
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/* Sign-extend vaddr, if necessary: */ |
| 262 |
if ((vaddr >> 32) == 0 && vaddr & (uint32_t)0x80000000ULL) |
| 263 |
vaddr |= 0xffffffff00000000ULL; |
| 264 |
#endif |
| 265 |
if (ksu == KSU_KERNEL) { |
| 266 |
/* kseg0, kseg1: */ |
| 267 |
if (vaddr >= (uint64_t)0xffffffff80000000ULL && |
| 268 |
vaddr <= (uint64_t)0xffffffffbfffffffULL) { |
| 269 |
*return_addr = vaddr & 0x1fffffff; |
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return 2; |
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} |
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|
| 273 |
/* TODO: supervisor stuff */ |
| 274 |
|
| 275 |
/* other segments: */ |
| 276 |
use_tlb = 1; |
| 277 |
} else |
| 278 |
use_tlb = 0; |
| 279 |
} |
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|
| 281 |
if (use_tlb) { |
| 282 |
#ifndef V2P_MMU3K |
| 283 |
int odd = 0, cached_lo1 = 0; |
| 284 |
#endif |
| 285 |
int g_bit, v_bit, d_bit; |
| 286 |
uint64_t cached_hi, cached_lo0; |
| 287 |
uint64_t entry_vpn2 = 0, entry_asid, pfn; |
| 288 |
|
| 289 |
for (i=0; i<n_tlbs; i++) { |
| 290 |
#ifdef V2P_MMU3K |
| 291 |
/* R3000 or similar: */ |
| 292 |
cached_hi = cp0->tlbs[i].hi; |
| 293 |
cached_lo0 = cp0->tlbs[i].lo0; |
| 294 |
|
| 295 |
entry_vpn2 = cached_hi & R2K3K_ENTRYHI_VPN_MASK; |
| 296 |
entry_asid = cached_hi & R2K3K_ENTRYHI_ASID_MASK; |
| 297 |
g_bit = cached_lo0 & R2K3K_ENTRYLO_G; |
| 298 |
v_bit = cached_lo0 & R2K3K_ENTRYLO_V; |
| 299 |
d_bit = cached_lo0 & R2K3K_ENTRYLO_D; |
| 300 |
#else |
| 301 |
/* R4000 or similar: */ |
| 302 |
pmask = cp0->tlbs[i].mask & pagemask_mask; |
| 303 |
cached_hi = cp0->tlbs[i].hi; |
| 304 |
cached_lo0 = cp0->tlbs[i].lo0; |
| 305 |
cached_lo1 = cp0->tlbs[i].lo1; |
| 306 |
|
| 307 |
/* Optimized for minimum page size: */ |
| 308 |
if (pmask == 0) { |
| 309 |
pageshift = pagemask_shift - 1; |
| 310 |
entry_vpn2 = (cached_hi & vpn2_mask) |
| 311 |
>> pagemask_shift; |
| 312 |
vaddr_vpn2 = (vaddr & vpn2_mask) |
| 313 |
>> pagemask_shift; |
| 314 |
pmask = (1 << (pagemask_shift-1)) - 1; |
| 315 |
odd = (vaddr >> (pagemask_shift-1)) & 1; |
| 316 |
} else { |
| 317 |
/* Non-standard page mask: */ |
| 318 |
switch (pmask | ((1 << pagemask_shift) - 1)) { |
| 319 |
case 0x00007ff: pageshift = 10; break; |
| 320 |
case 0x0001fff: pageshift = 12; break; |
| 321 |
case 0x0007fff: pageshift = 14; break; |
| 322 |
case 0x001ffff: pageshift = 16; break; |
| 323 |
case 0x007ffff: pageshift = 18; break; |
| 324 |
case 0x01fffff: pageshift = 20; break; |
| 325 |
case 0x07fffff: pageshift = 22; break; |
| 326 |
case 0x1ffffff: pageshift = 24; break; |
| 327 |
case 0x7ffffff: pageshift = 26; break; |
| 328 |
default: |
| 329 |
fatal("pmask=%08x\n", i, pmask); |
| 330 |
exit(1); |
| 331 |
} |
| 332 |
|
| 333 |
entry_vpn2 = (cached_hi & |
| 334 |
vpn2_mask) >> (pageshift + 1); |
| 335 |
vaddr_vpn2 = (vaddr & vpn2_mask) >> |
| 336 |
(pageshift + 1); |
| 337 |
pmask = (1 << pageshift) - 1; |
| 338 |
odd = (vaddr >> pageshift) & 1; |
| 339 |
} |
| 340 |
|
| 341 |
/* Assume even virtual page... */ |
| 342 |
v_bit = cached_lo0 & ENTRYLO_V; |
| 343 |
d_bit = cached_lo0 & ENTRYLO_D; |
| 344 |
|
| 345 |
#ifdef V2P_MMU8K |
| 346 |
/* |
| 347 |
* TODO: I don't really know anything about the R8000. |
| 348 |
* http://futuretech.mirror.vuurwerk.net/i2sec7.html |
| 349 |
* says that it has a three-way associative TLB with |
| 350 |
* 384 entries, 16KB page size, and some other things. |
| 351 |
* |
| 352 |
* It feels like things like the valid bit (ala R4000) |
| 353 |
* and dirty bit are not implemented the same on R8000. |
| 354 |
* |
| 355 |
* http://sgistuff.tastensuppe.de/documents/ |
| 356 |
* R8000_chipset.html |
| 357 |
* also has some info, but no details. |
| 358 |
*/ |
| 359 |
v_bit = 1; /* Big TODO */ |
| 360 |
d_bit = 1; |
| 361 |
#endif |
| 362 |
|
| 363 |
entry_asid = cached_hi & ENTRYHI_ASID; |
| 364 |
|
| 365 |
/* ... reload pfn, v_bit, d_bit if |
| 366 |
it was the odd virtual page: */ |
| 367 |
if (odd) { |
| 368 |
v_bit = cached_lo1 & ENTRYLO_V; |
| 369 |
d_bit = cached_lo1 & ENTRYLO_D; |
| 370 |
} |
| 371 |
#ifdef V2P_MMU4100 |
| 372 |
g_bit = cached_lo1 & cached_lo0 & ENTRYLO_G; |
| 373 |
#else |
| 374 |
g_bit = cached_hi & TLB_G; |
| 375 |
#endif |
| 376 |
|
| 377 |
#endif |
| 378 |
|
| 379 |
/* Is there a VPN and ASID match? */ |
| 380 |
if (entry_vpn2 == vaddr_vpn2 && |
| 381 |
(entry_asid == vaddr_asid || g_bit)) { |
| 382 |
/* debug("OK MAP 1, i=%i { vaddr=%016llx " |
| 383 |
"==> paddr %016llx v=%i d=%i " |
| 384 |
"asid=0x%02x }\n", i, (long long)vaddr, |
| 385 |
(long long) *return_addr, v_bit?1:0, |
| 386 |
d_bit?1:0, vaddr_asid); */ |
| 387 |
if (v_bit) { |
| 388 |
if (d_bit || (!d_bit && |
| 389 |
writeflag == MEM_READ)) { |
| 390 |
uint64_t paddr; |
| 391 |
/* debug("OK MAP 2!!! { w=%i " |
| 392 |
"vaddr=%016llx ==> d=%i v=" |
| 393 |
"%i paddr %016llx ", |
| 394 |
writeflag, (long long)vaddr, |
| 395 |
d_bit?1:0, v_bit?1:0, |
| 396 |
(long long) *return_addr); |
| 397 |
debug(", tlb entry %2i: ma" |
| 398 |
"sk=%016llx hi=%016llx lo0" |
| 399 |
"=%016llx lo1=%016llx\n", |
| 400 |
i, cp0->tlbs[i].mask, cp0-> |
| 401 |
tlbs[i].hi, cp0->tlbs[i]. |
| 402 |
lo0, cp0->tlbs[i].lo1); |
| 403 |
*/ |
| 404 |
#ifdef V2P_MMU3K |
| 405 |
pfn = cached_lo0 & |
| 406 |
R2K3K_ENTRYLO_PFN_MASK; |
| 407 |
paddr = pfn | (vaddr & pmask); |
| 408 |
#else |
| 409 |
pfn = ((odd? cached_lo1 : |
| 410 |
cached_lo0) |
| 411 |
& ENTRYLO_PFN_MASK) |
| 412 |
>> ENTRYLO_PFN_SHIFT; |
| 413 |
paddr = (pfn << pfn_shift) | |
| 414 |
(vaddr & pmask); |
| 415 |
#endif |
| 416 |
|
| 417 |
/* |
| 418 |
* Enter into the tiny trans- |
| 419 |
* lation cache (if enabled) |
| 420 |
* and return: |
| 421 |
*/ |
| 422 |
if (!bintrans_cached) |
| 423 |
insert_into_tiny_cache( |
| 424 |
cpu, instr, d_bit? |
| 425 |
MEM_WRITE : |
| 426 |
MEM_READ, |
| 427 |
vaddr, paddr); |
| 428 |
|
| 429 |
*return_addr = paddr; |
| 430 |
return d_bit? 2 : 1; |
| 431 |
} else { |
| 432 |
/* TLB modif. exception */ |
| 433 |
tlb_refill = 0; |
| 434 |
exccode = EXCEPTION_MOD; |
| 435 |
goto exception; |
| 436 |
} |
| 437 |
} else { |
| 438 |
/* TLB invalid exception */ |
| 439 |
tlb_refill = 0; |
| 440 |
goto exception; |
| 441 |
} |
| 442 |
} |
| 443 |
} |
| 444 |
} |
| 445 |
|
| 446 |
/* |
| 447 |
* We are here if for example userland code tried to access |
| 448 |
* kernel memory. |
| 449 |
*/ |
| 450 |
|
| 451 |
/* TLB refill */ |
| 452 |
|
| 453 |
exception: |
| 454 |
if (no_exceptions) |
| 455 |
return 0; |
| 456 |
|
| 457 |
/* TLB Load or Store exception: */ |
| 458 |
if (exccode == -1) { |
| 459 |
if (writeflag == MEM_WRITE) |
| 460 |
exccode = EXCEPTION_TLBS; |
| 461 |
else |
| 462 |
exccode = EXCEPTION_TLBL; |
| 463 |
} |
| 464 |
|
| 465 |
#ifdef V2P_MMU3K |
| 466 |
vaddr_asid >>= R2K3K_ENTRYHI_ASID_SHIFT; |
| 467 |
vaddr_vpn2 >>= 12; |
| 468 |
#endif |
| 469 |
|
| 470 |
mips_cpu_exception(cpu, exccode, tlb_refill, vaddr, |
| 471 |
0, vaddr_vpn2, vaddr_asid, x_64); |
| 472 |
|
| 473 |
/* Return failure: */ |
| 474 |
return 0; |
| 475 |
} |
| 476 |
|
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