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/* |
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* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: memory_rw.c,v 1.16 2005/04/19 01:24:35 debug Exp $ |
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* |
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* Generic memory_rw(), with special hacks for specific CPU families. |
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* |
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* Example for inclusion from memory_mips.c: |
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* |
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* MEMORY_RW should be mips_memory_rw |
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* MEM_MIPS should be defined |
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*/ |
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|
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|
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/* |
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* memory_rw(): |
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* |
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* Read or write data from/to memory. |
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* |
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* cpu the cpu doing the read/write |
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* mem the memory object to use |
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* vaddr the virtual address |
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* data a pointer to the data to be written to memory, or |
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* a placeholder for data when reading from memory |
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* len the length of the 'data' buffer |
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* writeflag set to MEM_READ or MEM_WRITE |
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* cache_flags CACHE_{NONE,DATA,INSTRUCTION} | other flags |
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* |
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* If the address indicates access to a memory mapped device, that device' |
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* read/write access function is called. |
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* |
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* If instruction latency/delay support is enabled, then |
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* cpu->instruction_delay is increased by the number of instruction to |
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* delay execution. |
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* |
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* This function should not be called with cpu == NULL. |
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* |
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* Returns one of the following: |
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* MEMORY_ACCESS_FAILED |
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* MEMORY_ACCESS_OK |
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* |
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* (MEMORY_ACCESS_FAILED is 0.) |
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*/ |
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int MEMORY_RW(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
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unsigned char *data, size_t len, int writeflag, int cache_flags) |
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{ |
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#ifndef MEM_USERLAND |
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int ok = 1; |
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#endif |
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uint64_t paddr; |
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int cache, no_exceptions, offset; |
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unsigned char *memblock; |
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#ifdef BINTRANS |
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int bintrans_cached = cpu->machine->bintrans_enable; |
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int bintrans_device_danger = 0; |
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#endif |
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no_exceptions = cache_flags & NO_EXCEPTIONS; |
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cache = cache_flags & CACHE_FLAGS_MASK; |
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|
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#ifdef MEM_PPC |
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if (cpu->cd.ppc.bits == 32) |
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vaddr &= 0xffffffff; |
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#endif |
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|
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#ifdef MEM_X86 |
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if (cpu->cd.x86.bits == 32) { |
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if ((vaddr >> 32) == 0xffffffff) |
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vaddr &= 0xffffffff; |
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|
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/* TODO: Actual address translation */ |
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if ((vaddr >> 32) == 0) { |
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vaddr &= 0x0fffffff; |
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|
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if (cpu->cd.x86.mode == 16) { |
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vaddr = (cpu->cd.x86.cursegment<<4) + |
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(vaddr & 0xffff); |
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/* TODO: A20 stuff */ |
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if ((vaddr & 0xffff) + len > 0x10000) { |
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fatal("x86 memory access crossing" |
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" segment boundary: TODO\n"); |
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cpu->running = 0; |
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return 0; |
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} |
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} |
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} |
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} |
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#endif |
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|
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#ifdef MEM_URISC |
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{ |
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uint64_t mask = (uint64_t) -1; |
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if (cpu->cd.urisc.wordlen < 64) |
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mask = ((int64_t)1 << cpu->cd.urisc.wordlen) - 1; |
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vaddr &= mask; |
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} |
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#endif |
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|
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#ifdef MEM_MIPS |
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#ifdef BINTRANS |
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if (bintrans_cached) { |
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if (cache == CACHE_INSTRUCTION) { |
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cpu->cd.mips.pc_bintrans_host_4kpage = NULL; |
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cpu->cd.mips.pc_bintrans_paddr_valid = 0; |
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} |
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} |
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#endif |
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#endif /* MEM_MIPS */ |
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|
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#ifdef MEM_USERLAND |
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paddr = vaddr & 0x7fffffff; |
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goto have_paddr; |
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#endif |
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|
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#ifndef MEM_USERLAND |
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#ifdef MEM_MIPS |
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/* |
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* For instruction fetch, are we on the same page as the last |
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* instruction we fetched? |
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* |
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* NOTE: There's no need to check this stuff here if this address |
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* is known to be in host ram, as it's done at instruction fetch |
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* time in cpu.c! Only check if _host_4k_page == NULL. |
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*/ |
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if (cache == CACHE_INSTRUCTION && |
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cpu->cd.mips.pc_last_host_4k_page == NULL && |
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(vaddr & ~0xfff) == cpu->cd.mips.pc_last_virtual_page) { |
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paddr = cpu->cd.mips.pc_last_physical_page | (vaddr & 0xfff); |
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goto have_paddr; |
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} |
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#endif /* MEM_MIPS */ |
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|
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if (cache_flags & PHYSICAL || cpu->translate_address == NULL) { |
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paddr = vaddr; |
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} else { |
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ok = cpu->translate_address(cpu, vaddr, &paddr, |
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(writeflag? FLAG_WRITEFLAG : 0) + |
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(no_exceptions? FLAG_NOEXCEPTIONS : 0) |
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+ (cache==CACHE_INSTRUCTION? FLAG_INSTR : 0)); |
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/* If the translation caused an exception, or was invalid in |
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some way, we simply return without doing the memory |
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access: */ |
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if (!ok) |
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return MEMORY_ACCESS_FAILED; |
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} |
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|
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|
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#ifdef MEM_MIPS |
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/* |
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* If correct cache emulation is enabled, and we need to simluate |
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* cache misses even from the instruction cache, we can't run directly |
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* from a host page. :-/ |
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*/ |
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#if defined(ENABLE_CACHE_EMULATION) && defined(ENABLE_INSTRUCTION_DELAYS) |
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#else |
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if (cache == CACHE_INSTRUCTION) { |
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cpu->cd.mips.pc_last_virtual_page = vaddr & ~0xfff; |
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cpu->cd.mips.pc_last_physical_page = paddr & ~0xfff; |
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cpu->cd.mips.pc_last_host_4k_page = NULL; |
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|
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/* _last_host_4k_page will be set to 1 further down, |
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if the page is actually in host ram */ |
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} |
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#endif |
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#endif /* MEM_MIPS */ |
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#endif /* ifndef MEM_USERLAND */ |
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|
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|
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#if defined(MEM_MIPS) || defined(MEM_USERLAND) |
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have_paddr: |
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#endif |
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|
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|
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#ifdef MEM_MIPS |
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/* TODO: How about bintrans vs cache emulation? */ |
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#ifdef BINTRANS |
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if (bintrans_cached) { |
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if (cache == CACHE_INSTRUCTION) { |
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cpu->cd.mips.pc_bintrans_paddr_valid = 1; |
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cpu->cd.mips.pc_bintrans_paddr = paddr; |
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} |
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} |
206 |
#endif |
207 |
#endif /* MEM_MIPS */ |
208 |
|
209 |
|
210 |
if (!(cache_flags & PHYSICAL)) |
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if (no_exceptions) |
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goto no_exception_access; |
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|
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|
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#ifndef MEM_USERLAND |
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/* |
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* Memory mapped device? |
218 |
* |
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* TODO: this is utterly slow. |
220 |
* TODO2: if paddr<base, but len enough, then we should write |
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* to a device to |
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*/ |
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if (paddr >= mem->mmap_dev_minaddr && paddr < mem->mmap_dev_maxaddr) { |
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#ifdef BINTRANS |
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uint64_t orig_paddr = paddr; |
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#endif |
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int i, start, res; |
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|
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#ifdef BINTRANS |
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/* |
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* Really really slow, but unfortunately necessary. This is |
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* to avoid the folowing scenario: |
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* |
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* a) offsets 0x000..0x123 are normal memory |
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* b) offsets 0x124..0x777 are a device |
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* |
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* 1) a read is done from offset 0x100. the page is |
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* added to the bintrans system as a "RAM" page |
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* 2) a bintranslated read is done from offset 0x200, |
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* which should access the device, but since the |
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* entire page is added, it will access non-existant |
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* RAM instead, without warning. |
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* |
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* Setting bintrans_device_danger = 1 on accesses which are |
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* on _any_ offset on pages that are device mapped avoids |
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* this problem, but it is probably not very fast. |
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*/ |
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if (bintrans_cached) { |
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for (i=0; i<mem->n_mmapped_devices; i++) |
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if (paddr >= (mem->dev_baseaddr[i] & ~0xfff) && |
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paddr <= ((mem->dev_baseaddr[i] + |
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mem->dev_length[i] - 1) | 0xfff)) { |
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bintrans_device_danger = 1; |
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break; |
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} |
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} |
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#endif |
258 |
|
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i = start = mem->last_accessed_device; |
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|
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/* Scan through all devices: */ |
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do { |
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if (paddr >= mem->dev_baseaddr[i] && |
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paddr < mem->dev_baseaddr[i] + mem->dev_length[i]) { |
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/* Found a device, let's access it: */ |
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mem->last_accessed_device = i; |
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|
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paddr -= mem->dev_baseaddr[i]; |
269 |
if (paddr + len > mem->dev_length[i]) |
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len = mem->dev_length[i] - paddr; |
271 |
|
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#ifdef BINTRANS |
273 |
if (bintrans_cached && mem->dev_flags[i] & |
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MEM_BINTRANS_OK) { |
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int wf = writeflag == MEM_WRITE? 1 : 0; |
276 |
|
277 |
if (writeflag) { |
278 |
if (paddr < mem-> |
279 |
dev_bintrans_write_low[i]) |
280 |
mem-> |
281 |
dev_bintrans_write_low |
282 |
[i] = |
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paddr & ~0xfff; |
284 |
if (paddr > mem-> |
285 |
dev_bintrans_write_high[i]) |
286 |
mem-> |
287 |
dev_bintrans_write_high |
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[i] = paddr | 0xfff; |
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} |
290 |
|
291 |
if (!(mem->dev_flags[i] & |
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MEM_BINTRANS_WRITE_OK)) |
293 |
wf = 0; |
294 |
|
295 |
update_translation_table(cpu, |
296 |
vaddr & ~0xfff, |
297 |
mem->dev_bintrans_data[i] + |
298 |
(paddr & ~0xfff), |
299 |
wf, orig_paddr & ~0xfff); |
300 |
} |
301 |
#endif |
302 |
|
303 |
res = mem->dev_f[i](cpu, mem, paddr, data, len, |
304 |
writeflag, mem->dev_extra[i]); |
305 |
|
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#ifdef ENABLE_INSTRUCTION_DELAYS |
307 |
if (res == 0) |
308 |
res = -1; |
309 |
|
310 |
cpu->cd.mips.instruction_delay += |
311 |
( (abs(res) - 1) * |
312 |
cpu->cd.mips.cpu_type.instrs_per_cycle ); |
313 |
#endif |
314 |
/* |
315 |
* If accessing the memory mapped device |
316 |
* failed, then return with a DBE exception. |
317 |
*/ |
318 |
if (res <= 0) { |
319 |
debug("%s device '%s' addr %08lx " |
320 |
"failed\n", writeflag? |
321 |
"writing to" : "reading from", |
322 |
mem->dev_name[i], (long)paddr); |
323 |
#ifdef MEM_MIPS |
324 |
mips_cpu_exception(cpu, EXCEPTION_DBE, |
325 |
0, vaddr, 0, 0, 0, 0); |
326 |
#endif |
327 |
return MEMORY_ACCESS_FAILED; |
328 |
} |
329 |
|
330 |
goto do_return_ok; |
331 |
} |
332 |
|
333 |
i ++; |
334 |
if (i == mem->n_mmapped_devices) |
335 |
i = 0; |
336 |
} while (i != start); |
337 |
} |
338 |
|
339 |
|
340 |
#ifdef MEM_MIPS |
341 |
/* |
342 |
* Data and instruction cache emulation: |
343 |
*/ |
344 |
|
345 |
switch (cpu->cd.mips.cpu_type.mmu_model) { |
346 |
case MMU3K: |
347 |
/* if not uncached addess (TODO: generalize this) */ |
348 |
if (!(cache_flags & PHYSICAL) && cache != CACHE_NONE && |
349 |
!((vaddr & 0xffffffffULL) >= 0xa0000000ULL && |
350 |
(vaddr & 0xffffffffULL) <= 0xbfffffffULL)) { |
351 |
if (memory_cache_R3000(cpu, cache, paddr, |
352 |
writeflag, len, data)) |
353 |
goto do_return_ok; |
354 |
} |
355 |
break; |
356 |
#if 0 |
357 |
/* Remove this, it doesn't work anyway */ |
358 |
case MMU10K: |
359 |
/* other cpus: */ |
360 |
/* |
361 |
* SUPER-UGLY HACK for SGI-IP32 PROM, R10000: |
362 |
* K0 bits == 0x3 means uncached... |
363 |
* |
364 |
* It seems that during bootup, the SGI-IP32 prom |
365 |
* stores a return pointers a 0x80000f10, then tests |
366 |
* memory by writing bit patterns to 0xa0000xxx, and |
367 |
* then when it's done, reads back the return pointer |
368 |
* from 0x80000f10. |
369 |
* |
370 |
* I need to find the correct way to disconnect the |
371 |
* cache from the main memory for R10000. (TODO !!!) |
372 |
*/ |
373 |
/* if ((cpu->cd.mips.coproc[0]->reg[COP0_CONFIG] & 7) == 3) { */ |
374 |
/* |
375 |
if (cache == CACHE_DATA && |
376 |
cpu->r10k_cache_disable_TODO) { |
377 |
paddr &= ((512*1024)-1); |
378 |
paddr += 512*1024; |
379 |
} |
380 |
*/ |
381 |
break; |
382 |
#endif |
383 |
default: |
384 |
/* R4000 etc */ |
385 |
/* TODO */ |
386 |
; |
387 |
} |
388 |
#endif /* MEM_MIPS */ |
389 |
|
390 |
|
391 |
/* Outside of physical RAM? */ |
392 |
if (paddr >= mem->physical_max) { |
393 |
if ((paddr & 0xffff000000ULL) == 0x1f000000) { |
394 |
/* Ok, this is PROM stuff */ |
395 |
} else if ((paddr & 0xfffff00000ULL) == 0x1ff00000) { |
396 |
/* Sprite reads from this area of memory... */ |
397 |
/* TODO: is this still correct? */ |
398 |
if (writeflag == MEM_READ) |
399 |
memset(data, 0, len); |
400 |
goto do_return_ok; |
401 |
} else { |
402 |
if (paddr >= mem->physical_max + 0 * 1024) { |
403 |
char *symbol; |
404 |
#ifdef MEM_MIPS |
405 |
uint64_t offset; |
406 |
#endif |
407 |
if (!quiet_mode) { |
408 |
fatal("[ memory_rw(): writeflag=%i ", |
409 |
writeflag); |
410 |
if (writeflag) { |
411 |
unsigned int i; |
412 |
debug("data={", writeflag); |
413 |
if (len > 16) { |
414 |
int start2 = len-16; |
415 |
for (i=0; i<16; i++) |
416 |
debug("%s%02x", |
417 |
i?",":"", |
418 |
data[i]); |
419 |
debug(" .. "); |
420 |
if (start2 < 16) |
421 |
start2 = 16; |
422 |
for (i=start2; i<len; |
423 |
i++) |
424 |
debug("%s%02x", |
425 |
i?",":"", |
426 |
data[i]); |
427 |
} else |
428 |
for (i=0; i<len; i++) |
429 |
debug("%s%02x", |
430 |
i?",":"", |
431 |
data[i]); |
432 |
debug("}"); |
433 |
} |
434 |
#ifdef MEM_MIPS |
435 |
symbol = get_symbol_name( |
436 |
&cpu->machine->symbol_context, |
437 |
cpu->cd.mips.pc_last, &offset); |
438 |
#else |
439 |
symbol = "(unimpl for non-MIPS)"; |
440 |
#endif |
441 |
|
442 |
/* TODO: fix! not mips.pc_last for for example ppc */ |
443 |
|
444 |
fatal(" paddr=%llx >= physical_max pc=" |
445 |
"0x%08llx <%s> ]\n", |
446 |
(long long)paddr, |
447 |
(long long)cpu->cd.mips.pc_last, |
448 |
symbol? symbol : "no symbol"); |
449 |
} |
450 |
|
451 |
if (cpu->machine->single_step_on_bad_addr) { |
452 |
fatal("[ unimplemented access to " |
453 |
"0x%016llx, pc = 0x%016llx ]\n", |
454 |
(long long)paddr, |
455 |
(long long)cpu->pc); |
456 |
single_step = 1; |
457 |
} |
458 |
} |
459 |
|
460 |
if (writeflag == MEM_READ) { |
461 |
/* Return all zeroes? (Or 0xff? TODO) */ |
462 |
memset(data, 0, len); |
463 |
|
464 |
#ifdef MEM_MIPS |
465 |
/* |
466 |
* For real data/instruction accesses, cause |
467 |
* an exceptions on an illegal read: |
468 |
*/ |
469 |
if (cache != CACHE_NONE && cpu->machine-> |
470 |
dbe_on_nonexistant_memaccess) { |
471 |
if (paddr >= mem->physical_max && |
472 |
paddr < mem->physical_max+1048576) |
473 |
mips_cpu_exception(cpu, |
474 |
EXCEPTION_DBE, 0, vaddr, 0, |
475 |
0, 0, 0); |
476 |
} |
477 |
#endif /* MEM_MIPS */ |
478 |
} |
479 |
|
480 |
/* Hm? Shouldn't there be a DBE exception for |
481 |
invalid writes as well? TODO */ |
482 |
|
483 |
goto do_return_ok; |
484 |
} |
485 |
} |
486 |
|
487 |
#endif /* ifndef MEM_USERLAND */ |
488 |
|
489 |
|
490 |
no_exception_access: |
491 |
|
492 |
/* |
493 |
* Uncached access: |
494 |
*/ |
495 |
memblock = memory_paddr_to_hostaddr(mem, paddr, writeflag); |
496 |
if (memblock == NULL) { |
497 |
if (writeflag == MEM_READ) |
498 |
memset(data, 0, len); |
499 |
goto do_return_ok; |
500 |
} |
501 |
|
502 |
offset = paddr & ((1 << BITS_PER_MEMBLOCK) - 1); |
503 |
|
504 |
#ifdef BINTRANS |
505 |
if (bintrans_cached && !bintrans_device_danger) |
506 |
update_translation_table(cpu, vaddr & ~0xfff, |
507 |
memblock + (offset & ~0xfff), |
508 |
#if 0 |
509 |
cache == CACHE_INSTRUCTION? |
510 |
(writeflag == MEM_WRITE? 1 : 0) |
511 |
: ok - 1, |
512 |
#else |
513 |
writeflag == MEM_WRITE? 1 : 0, |
514 |
#endif |
515 |
paddr & ~0xfff); |
516 |
#endif |
517 |
|
518 |
if (writeflag == MEM_WRITE) { |
519 |
if (len == sizeof(uint32_t) && (offset & 3)==0) |
520 |
*(uint32_t *)(memblock + offset) = *(uint32_t *)data; |
521 |
else if (len == sizeof(uint8_t)) |
522 |
*(uint8_t *)(memblock + offset) = *(uint8_t *)data; |
523 |
else |
524 |
memcpy(memblock + offset, data, len); |
525 |
} else { |
526 |
if (len == sizeof(uint32_t) && (offset & 3)==0) |
527 |
*(uint32_t *)data = *(uint32_t *)(memblock + offset); |
528 |
else if (len == sizeof(uint8_t)) |
529 |
*(uint8_t *)data = *(uint8_t *)(memblock + offset); |
530 |
else |
531 |
memcpy(data, memblock + offset, len); |
532 |
|
533 |
if (cache == CACHE_INSTRUCTION) { |
534 |
cpu->cd.mips.pc_last_host_4k_page = memblock |
535 |
+ (offset & ~0xfff); |
536 |
#ifdef BINTRANS |
537 |
if (bintrans_cached) { |
538 |
cpu->cd.mips.pc_bintrans_host_4kpage = |
539 |
cpu->cd.mips.pc_last_host_4k_page; |
540 |
} |
541 |
#endif |
542 |
} |
543 |
} |
544 |
|
545 |
|
546 |
do_return_ok: |
547 |
return MEMORY_ACCESS_OK; |
548 |
} |
549 |
|