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/* |
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* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: memory_mips.c,v 1.5 2005/02/18 07:04:10 debug Exp $ |
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* |
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* MIPS-specific memory routines. Included from cpu_mips.c. |
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*/ |
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|
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#include <sys/types.h> |
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#include <sys/mman.h> |
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|
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|
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/* |
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* insert_into_tiny_cache(): |
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* |
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* If the tiny cache is enabled (USE_TINY_CACHE), then this routine inserts |
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* a vaddr to paddr translation first in the instruction (or data) tiny |
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* translation cache. |
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*/ |
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static void insert_into_tiny_cache(struct cpu *cpu, int instr, int writeflag, |
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uint64_t vaddr, uint64_t paddr) |
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{ |
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#ifdef USE_TINY_CACHE |
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int wf = 1 + (writeflag == MEM_WRITE); |
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|
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if (cpu->machine->bintrans_enable) |
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return; |
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|
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paddr &= ~0xfff; |
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vaddr >>= 12; |
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|
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if (instr) { |
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/* Code: */ |
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memmove(&cpu->cd.mips.translation_cache_instr[1], |
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&cpu->cd.mips.translation_cache_instr[0], |
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sizeof(struct translation_cache_entry) * |
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(N_TRANSLATION_CACHE_INSTR - 1)); |
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|
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cpu->cd.mips.translation_cache_instr[0].wf = wf; |
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cpu->cd.mips.translation_cache_instr[0].vaddr_pfn = vaddr; |
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cpu->cd.mips.translation_cache_instr[0].paddr = paddr; |
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} else { |
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/* Data: */ |
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memmove(&cpu->cd.mips.translation_cache_data[1], |
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&cpu->cd.mips.translation_cache_data[0], |
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sizeof(struct translation_cache_entry) * |
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(N_TRANSLATION_CACHE_DATA - 1)); |
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|
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cpu->cd.mips.translation_cache_data[0].wf = wf; |
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cpu->cd.mips.translation_cache_data[0].vaddr_pfn = vaddr; |
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cpu->cd.mips.translation_cache_data[0].paddr = paddr; |
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} |
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#endif |
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} |
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|
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|
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/* |
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* memory_cache_R3000(): |
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* |
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* R2000/R3000 specific cache handling. |
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* |
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* Return value is 1 if a jump to do_return_ok is supposed to happen directly |
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* after this routine is finished, 0 otherwise. |
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*/ |
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int memory_cache_R3000(struct cpu *cpu, int cache, uint64_t paddr, |
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int writeflag, size_t len, unsigned char *data) |
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{ |
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#ifdef ENABLE_CACHE_EMULATION |
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struct r3000_cache_line *rp; |
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int cache_line; |
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uint32_t tag_mask; |
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unsigned char *memblock; |
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struct memory *mem = cpu->mem; |
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int offset; |
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#endif |
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unsigned int i; |
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int cache_isolated = 0, addr, hit, which_cache = cache; |
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|
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|
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if (len > 4 || cache == CACHE_NONE) |
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return 0; |
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|
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|
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#ifdef ENABLE_CACHE_EMULATION |
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if (cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & MIPS1_SWAP_CACHES) |
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which_cache ^= 1; |
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|
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tag_mask = 0xffffffff & ~cpu->cd.mips.cache_mask[which_cache]; |
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cache_line = (paddr & cpu->cd.mips.cache_mask[which_cache]) |
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/ cpu->cd.mips.cache_linesize[which_cache]; |
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rp = (struct r3000_cache_line *) cpu->cd.mips.cache_tags[which_cache]; |
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|
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/* Is this a cache hit or miss? */ |
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hit = (rp[cache_line].tag_valid & R3000_TAG_VALID) && |
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(rp[cache_line].tag_paddr == (paddr & tag_mask)); |
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|
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#ifdef ENABLE_INSTRUCTION_DELAYS |
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if (!hit) |
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cpu->cd.mips.instruction_delay += |
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cpu->cd.mips.cpu_type.instrs_per_cycle |
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* cpu->cd.mips.cache_miss_penalty[which_cache]; |
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#endif |
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|
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/* |
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* The cache miss bit is only set on cache reads, and only to the |
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* data cache. (?) |
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* |
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* (TODO: is this correct? I don't remember where I got this from.) |
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*/ |
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if (cache == CACHE_DATA && writeflag==MEM_READ) { |
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cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &= ~MIPS1_CACHE_MISS; |
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if (!hit) |
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cpu->cd.mips.coproc[0]->reg[COP0_STATUS] |= |
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MIPS1_CACHE_MISS; |
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} |
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|
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/* |
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* Is the Data cache isolated? Then don't access main memory: |
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*/ |
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if (cache == CACHE_DATA && |
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cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & MIPS1_ISOL_CACHES) |
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cache_isolated = 1; |
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|
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addr = paddr & cpu->cd.mips.cache_mask[which_cache]; |
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|
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/* |
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* If there was a miss and the cache is not isolated, then flush |
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* the old cacheline back to main memory, and read in the new |
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* cacheline. |
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* |
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* Then access the cache. |
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*/ |
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/* |
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fatal("L1 CACHE isolated=%i hit=%i write=%i cache=%i cacheline=%i" |
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" paddr=%08x => addr in" |
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" cache = 0x%lx\n", cache_isolated, hit, writeflag, |
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which_cache, cache_line, (int)paddr, |
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addr); |
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*/ |
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if (!hit && !cache_isolated) { |
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unsigned char *dst, *src; |
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uint64_t old_cached_paddr = rp[cache_line].tag_paddr |
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+ cache_line * cpu->cd.mips.cache_linesize[which_cache]; |
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|
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/* Flush the old cacheline to main memory: */ |
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if ((rp[cache_line].tag_valid & R3000_TAG_VALID) && |
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(rp[cache_line].tag_valid & R3000_TAG_DIRTY)) { |
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/* fatal(" FLUSHING old tag=0%08x " |
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"old_cached_paddr=0x%08x\n", |
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rp[cache_line].tag_paddr, |
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old_cached_paddr); |
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*/ |
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memblock = memory_paddr_to_hostaddr( |
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mem, old_cached_paddr, MEM_WRITE); |
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offset = old_cached_paddr |
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& ((1 << BITS_PER_MEMBLOCK) - 1) |
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& ~cpu->cd.mips.cache_mask[which_cache]; |
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|
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src = cpu->cd.mips.cache[which_cache]; |
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dst = memblock + (offset & |
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~cpu->cd.mips.cache_mask[which_cache]); |
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|
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src += cache_line * |
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cpu->cd.mips.cache_linesize[which_cache]; |
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dst += cache_line * |
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cpu->cd.mips.cache_linesize[which_cache]; |
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|
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if (memblock == NULL) { |
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fatal("BUG in memory.c! Hm.\n"); |
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} else { |
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memcpy(dst, src, |
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cpu->cd.mips.cache_linesize[which_cache]); |
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} |
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/* offset is the offset within |
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* the memblock: |
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* printf("read: offset = 0x%x\n", offset); |
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*/ |
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} |
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|
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/* Copy from main memory into the cache: */ |
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memblock = memory_paddr_to_hostaddr(mem, paddr, writeflag); |
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offset = paddr & ((1 << BITS_PER_MEMBLOCK) - 1) |
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& ~cpu->cd.mips.cache_mask[which_cache]; |
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/* offset is offset within the memblock: |
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* printf("write: offset = 0x%x\n", offset); |
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*/ |
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|
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/* fatal(" FETCHING new paddr=0%08x\n", paddr); |
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*/ |
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dst = cpu->cd.mips.cache[which_cache]; |
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|
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if (memblock == NULL) { |
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if (writeflag == MEM_READ) |
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memset(dst, 0, |
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cpu->cd.mips.cache_linesize[which_cache]); |
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} else { |
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src = memblock + (offset & |
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~cpu->cd.mips.cache_mask[which_cache]); |
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|
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src += cache_line * |
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cpu->cd.mips.cache_linesize[which_cache]; |
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dst += cache_line * |
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cpu->cd.mips.cache_linesize[which_cache]; |
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memcpy(dst, src, |
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cpu->cd.mips.cache_linesize[which_cache]); |
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} |
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|
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rp[cache_line].tag_paddr = paddr & tag_mask; |
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rp[cache_line].tag_valid = R3000_TAG_VALID; |
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} |
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|
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if (cache_isolated && writeflag == MEM_WRITE) { |
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rp[cache_line].tag_valid = 0; |
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} |
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|
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if (writeflag==MEM_READ) { |
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for (i=0; i<len; i++) |
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data[i] = cpu->cd.mips.cache[which_cache][(addr+i) & |
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cpu->cd.mips.cache_mask[which_cache]]; |
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} else { |
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for (i=0; i<len; i++) { |
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if (cpu->cd.mips.cache[which_cache][(addr+i) & |
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cpu->cd.mips.cache_mask[which_cache]] != data[i]) { |
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rp[cache_line].tag_valid |= R3000_TAG_DIRTY; |
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} |
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cpu->cd.mips.cache[which_cache][(addr+i) & |
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cpu->cd.mips.cache_mask[which_cache]] = data[i]; |
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} |
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} |
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|
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/* Run instructions from the right host page: */ |
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if (cache == CACHE_INSTRUCTION) { |
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memblock = memory_paddr_to_hostaddr(mem, paddr, writeflag); |
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if (memblock != NULL) { |
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cpu->cd.mips.pc_last_host_4k_page = memblock + |
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(paddr & ((1 << BITS_PER_MEMBLOCK) - 1) & ~0xfff); |
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} |
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} |
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|
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/* Write-through! (Write to main memory as well.) */ |
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if (writeflag == MEM_READ || cache_isolated) |
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return 1; |
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|
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#else |
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|
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/* |
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* R2000/R3000 without correct cache emulation: |
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* |
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* TODO: This is just enough to trick NetBSD/pmax and Ultrix into |
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* being able to detect the cache sizes and think that the caches |
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* are actually working, but they are not. |
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*/ |
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|
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if (cache != CACHE_DATA) |
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return 0; |
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|
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/* Is this a cache hit or miss? */ |
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hit = (cpu->cd.mips.cache_last_paddr[which_cache] |
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& ~cpu->cd.mips.cache_mask[which_cache]) |
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== (paddr & ~(cpu->cd.mips.cache_mask[which_cache])); |
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|
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#ifdef ENABLE_INSTRUCTION_DELAYS |
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if (!hit) |
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cpu->cd.mips.instruction_delay += |
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cpu->cd.mips.cpu_type.instrs_per_cycle |
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* cpu->cd.mips.cache_miss_penalty[which_cache]; |
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#endif |
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|
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/* |
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* The cache miss bit is only set on cache reads, and only to the |
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* data cache. (?) |
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* |
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* (TODO: is this correct? I don't remember where I got this from.) |
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*/ |
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if (cache == CACHE_DATA && writeflag==MEM_READ) { |
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cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &= ~MIPS1_CACHE_MISS; |
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if (!hit) |
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cpu->cd.mips.coproc[0]->reg[COP0_STATUS] |= |
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MIPS1_CACHE_MISS; |
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} |
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|
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/* |
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* Is the Data cache isolated? Then don't access main memory: |
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*/ |
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if (cache == CACHE_DATA && |
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cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & MIPS1_ISOL_CACHES) |
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cache_isolated = 1; |
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|
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addr = paddr & cpu->cd.mips.cache_mask[which_cache]; |
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|
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/* Data cache isolated? Then don't access main memory: */ |
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if (cache_isolated) { |
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/* debug("ISOLATED write=%i cache=%i vaddr=%016llx " |
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"paddr=%016llx => addr in cache = 0x%lx\n", |
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writeflag, cache, (long long)vaddr, |
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(long long)paddr, addr); */ |
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|
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if (writeflag==MEM_READ) { |
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for (i=0; i<len; i++) |
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data[i] = cpu->cd.mips.cache[cache][(addr+i) & |
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cpu->cd.mips.cache_mask[cache]]; |
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} else { |
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for (i=0; i<len; i++) |
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cpu->cd.mips.cache[cache][(addr+i) & |
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cpu->cd.mips.cache_mask[cache]] = data[i]; |
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} |
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return 1; |
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} else { |
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/* Reload caches if necessary: */ |
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|
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/* No! Not when not emulating caches fully. (TODO?) */ |
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cpu->cd.mips.cache_last_paddr[cache] = paddr; |
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} |
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#endif |
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|
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return 0; |
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} |
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|
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|
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#define TRANSLATE_ADDRESS translate_address_mmu3k |
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#define V2P_MMU3K |
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#include "memory_mips_v2p.c" |
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#undef TRANSLATE_ADDRESS |
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#undef V2P_MMU3K |
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|
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#define TRANSLATE_ADDRESS translate_address_mmu8k |
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#define V2P_MMU8K |
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#include "memory_mips_v2p.c" |
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#undef TRANSLATE_ADDRESS |
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#undef V2P_MMU8K |
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|
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#define TRANSLATE_ADDRESS translate_address_mmu10k |
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#define V2P_MMU10K |
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#include "memory_mips_v2p.c" |
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#undef TRANSLATE_ADDRESS |
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#undef V2P_MMU10K |
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|
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/* Almost generic :-) */ |
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#define TRANSLATE_ADDRESS translate_address_mmu4100 |
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#define V2P_MMU4100 |
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#include "memory_mips_v2p.c" |
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#undef TRANSLATE_ADDRESS |
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#undef V2P_MMU4100 |
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|
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#define TRANSLATE_ADDRESS translate_address_generic |
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#include "memory_mips_v2p.c" |
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|
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|
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#define MEMORY_RW mips_memory_rw |
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#define MEM_MIPS |
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#include "memory_rw.c" |
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#undef MEM_MIPS |
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#undef MEMORY_RW |
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