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#ifndef CPU_X86_H |
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#define CPU_X86_H |
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|
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/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_x86.h,v 1.31 2005/05/29 19:21:05 debug Exp $ |
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*/ |
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|
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#include "misc.h" |
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|
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|
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struct cpu_family; |
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|
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#define N_X86_REGS 16 |
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|
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#define x86_reg_names { \ |
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"ax", "cx", "dx", "bx", "sp", "bp", "si", "di", \ |
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"08", "09", "10", "11", "12", "13", "14", "15" } |
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#define x86_reg_names_bytes { \ |
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"al", "cl", "dl", "bl", "ah", "ch", "dh", "bh" } |
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|
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#define X86_R_AX 0 |
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#define X86_R_CX 1 |
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#define X86_R_DX 2 |
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#define X86_R_BX 3 |
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#define X86_R_SP 4 |
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#define X86_R_BP 5 |
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#define X86_R_SI 6 |
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#define X86_R_DI 7 |
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|
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#define N_X86_SEGS 8 |
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/* (All of these 8 are not actually used.) */ |
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|
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#define X86_S_ES 0 |
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#define X86_S_CS 1 |
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#define X86_S_SS 2 |
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#define X86_S_DS 3 |
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#define X86_S_FS 4 |
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#define X86_S_GS 5 |
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|
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#define x86_seg_names { "es", "cs", "ss", "ds", "fs", "gs", "segr6", "segr7" } |
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|
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#define N_X86_CREGS 8 |
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|
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#define N_X86_DREGS 8 |
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|
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#define x86_cond_names { "o", "b", "z", "be", "s", "p", "l", "le" } |
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#define N_X86_CONDS 8 |
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|
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#define X86_MODEL_8086 1 |
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#define X86_MODEL_80286 2 |
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#define X86_MODEL_80386 3 |
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#define X86_MODEL_80486 4 |
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#define X86_MODEL_PENTIUM 5 |
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#define X86_MODEL_AMD64 6 |
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|
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struct x86_model { |
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int model_number; |
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char *name; |
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}; |
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|
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#define x86_models { \ |
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{ X86_MODEL_8086, "8086" }, \ |
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{ X86_MODEL_80286, "80286" }, \ |
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{ X86_MODEL_80386, "80386" }, \ |
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{ X86_MODEL_80486, "80486" }, \ |
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{ X86_MODEL_PENTIUM, "PENTIUM" }, \ |
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{ X86_MODEL_AMD64, "AMD64" }, \ |
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{ 0, NULL } \ |
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} |
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|
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|
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struct descriptor_cache { |
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int valid; |
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int default_op_size; |
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int access_rights; |
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int descr_type; |
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int readable; |
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int writable; |
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int granularity; |
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uint64_t base; |
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uint64_t limit; |
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}; |
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|
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|
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struct x86_cpu { |
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struct x86_model model; |
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|
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int halted; |
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int interrupt_asserted; |
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|
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int cursegment; /* NOTE: 0..N_X86_SEGS-1 */ |
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int seg_override; /* 0 or 1 */ |
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|
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uint64_t tsc; /* time stamp counter */ |
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|
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uint64_t gdtr; /* global descriptor table */ |
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uint32_t gdtr_limit; |
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uint64_t idtr; /* interrupt descriptor table */ |
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uint32_t idtr_limit; |
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|
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uint16_t tr; /* task register */ |
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uint64_t tr_base; |
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uint32_t tr_limit; |
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uint16_t ldtr; /* local descriptor table register */ |
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uint64_t ldtr_base; |
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uint32_t ldtr_limit; |
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|
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uint64_t rflags; |
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uint64_t cr[N_X86_CREGS]; /* control registers */ |
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uint64_t dr[N_X86_DREGS]; /* debug registers */ |
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|
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uint16_t s[N_X86_SEGS]; /* segment selectors */ |
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struct descriptor_cache descr_cache[N_X86_SEGS]; |
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|
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uint64_t r[N_X86_REGS]; /* GPRs */ |
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|
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/* FPU: */ |
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uint16_t fpu_sw; /* status word */ |
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uint16_t fpu_cw; /* control word */ |
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|
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/* MSRs: */ |
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uint64_t efer; |
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}; |
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|
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|
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#define X86_FLAGS_CF (1) /* Carry Flag */ |
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#define X86_FLAGS_PF (4) /* Parity Flag */ |
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#define X86_FLAGS_AF (16) /* Adjust/AuxilaryCarry Flag */ |
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#define X86_FLAGS_ZF (64) /* Zero Flag */ |
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#define X86_FLAGS_SF (128) /* Sign Flag */ |
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#define X86_FLAGS_TF (256) /* Trap Flag */ |
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#define X86_FLAGS_IF (512) /* Interrupt Enable Flag */ |
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#define X86_FLAGS_DF (1024) /* Direction Flag */ |
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#define X86_FLAGS_OF (2048) /* Overflow Flag */ |
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/* Bits 12 and 13 are I/O Privilege Level */ |
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#define X86_FLAGS_NT (1<<14) /* Nested Task Flag */ |
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#define X86_FLAGS_RF (1<<16) /* Resume Flag */ |
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#define X86_FLAGS_VM (1<<17) /* VM86 Flag */ |
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#define X86_FLAGS_AC (1<<18) /* Alignment Check */ |
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#define X86_FLAGS_VIF (1<<19) /* ? */ |
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#define X86_FLAGS_VIP (1<<20) /* ? */ |
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#define X86_FLAGS_ID (1<<21) /* CPUID present */ |
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|
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#define X86_CR0_PE 0x00000001 /* Protection Enable */ |
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#define X86_CR0_MP 0x00000002 |
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#define X86_CR0_EM 0x00000004 |
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#define X86_CR0_TS 0x00000008 |
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#define X86_CR0_ET 0x00000010 |
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#define X86_CR0_NE 0x00000020 |
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#define X86_CR0_WP 0x00010000 |
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#define X86_CR0_AM 0x00040000 |
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#define X86_CR0_NW 0x20000000 |
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#define X86_CR0_CD 0x40000000 |
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#define X86_CR0_PG 0x80000000 /* Paging Enable */ |
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|
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#define X86_CR4_OSXMEX 0x00000400 |
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#define X86_CR4_OSFXSR 0x00000200 |
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#define X86_CR4_PCE 0x00000100 |
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#define X86_CR4_PGE 0x00000080 |
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#define X86_CR4_MCE 0x00000040 |
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#define X86_CR4_PAE 0x00000020 |
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#define X86_CR4_PSE 0x00000010 |
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#define X86_CR4_DE 0x00000008 |
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#define X86_CR4_TSD 0x00000004 /* Time Stamp Disable */ |
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#define X86_CR4_PVI 0x00000002 |
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#define X86_CR4_VME 0x00000001 |
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|
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/* EFER bits: */ |
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#define X86_EFER_FFXSR 0x00004000 |
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#define X86_EFER_LMSLE 0x00002000 |
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#define X86_EFER_NXE 0x00000800 |
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#define X86_EFER_LMA 0x00000400 |
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#define X86_EFER_LME 0x00000100 /* Long Mode (64-bit) */ |
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#define X86_EFER_SCE 0x00000001 |
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|
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/* CPUID feature bits: */ |
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#define X86_CPUID_ECX_ETPRD 0x00004000 |
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#define X86_CPUID_ECX_CX16 0x00002000 /* cmpxchg16b */ |
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#define X86_CPUID_ECX_CID 0x00000400 |
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#define X86_CPUID_ECX_TM2 0x00000100 |
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#define X86_CPUID_ECX_EST 0x00000080 |
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#define X86_CPUID_ECX_DSCPL 0x00000010 |
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#define X86_CPUID_ECX_MON 0x00000004 |
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#define X86_CPUID_ECX_SSE3 0x00000001 |
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#define X86_CPUID_EDX_PBE 0x80000000 /* pending break event */ |
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#define X86_CPUID_EDX_IA64 0x40000000 |
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#define X86_CPUID_EDX_TM1 0x20000000 /* thermal interrupt */ |
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#define X86_CPUID_EDX_HTT 0x10000000 /* hyper threading */ |
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#define X86_CPUID_EDX_SS 0x08000000 /* self-snoop */ |
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#define X86_CPUID_EDX_SSE2 0x04000000 |
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#define X86_CPUID_EDX_SSE 0x02000000 |
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#define X86_CPUID_EDX_FXSR 0x01000000 |
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#define X86_CPUID_EDX_MMX 0x00800000 |
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#define X86_CPUID_EDX_ACPI 0x00400000 |
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#define X86_CPUID_EDX_DTES 0x00200000 |
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#define X86_CPUID_EDX_CLFL 0x00080000 |
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#define X86_CPUID_EDX_PSN 0x00040000 |
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#define X86_CPUID_EDX_PSE36 0x00020000 |
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#define X86_CPUID_EDX_PAT 0x00010000 |
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#define X86_CPUID_EDX_CMOV 0x00008000 |
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#define X86_CPUID_EDX_MCA 0x00004000 |
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#define X86_CPUID_EDX_PGE 0x00002000 /* global bit in PDE/PTE */ |
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#define X86_CPUID_EDX_MTRR 0x00001000 |
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#define X86_CPUID_EDX_SEP 0x00000800 /* sysenter/sysexit */ |
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#define X86_CPUID_EDX_APIC 0x00000200 |
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#define X86_CPUID_EDX_CX8 0x00000100 /* cmpxchg8b */ |
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#define X86_CPUID_EDX_MCE 0x00000080 |
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#define X86_CPUID_EDX_PAE 0x00000040 |
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#define X86_CPUID_EDX_MSR 0x00000020 |
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#define X86_CPUID_EDX_TSC 0x00000010 |
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#define X86_CPUID_EDX_PSE 0x00000008 |
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#define X86_CPUID_EDX_DE 0x00000004 |
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#define X86_CPUID_EDX_VME 0x00000002 |
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#define X86_CPUID_EDX_FPU 0x00000001 |
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|
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/* Extended CPUID flags: */ |
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#define X86_CPUID_EXT_ECX_CR8D 0x00000010 |
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#define X86_CPUID_EXT_ECX_CMP 0x00000002 |
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#define X86_CPUID_EXT_ECX_AHF64 0x00000001 |
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#define X86_CPUID_EXT_EDX_LM 0x20000000 /* AMD64 Long Mode */ |
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#define X86_CPUID_EXT_EDX_FFXSR 0x02000000 |
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/* TODO: Many bits are duplicated in the Extended CPUID bits! */ |
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|
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#define X86_IO_BASE 0x1000000000ULL |
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|
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/* Privilege level in the lowest 2 bits of a selector: */ |
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#define X86_PL_MASK 0x0003 |
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#define X86_RING0 0 |
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#define X86_RING1 1 |
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#define X86_RING2 2 |
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#define X86_RING3 3 |
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|
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#define DESCR_TYPE_CODE 1 |
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#define DESCR_TYPE_DATA 2 |
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|
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|
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#define PROTECTED_MODE (cpu->cd.x86.cr[0] & X86_CR0_PE) |
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#define REAL_MODE (!PROTECTED_MODE) |
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|
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/* cpu_x86.c: */ |
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void reload_segment_descriptor(struct cpu *cpu, int segnr, int selector, |
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uint64_t *curpcp); |
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int x86_interrupt(struct cpu *cpu, int nr, int errcode); |
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int x86_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
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unsigned char *data, size_t len, int writeflag, int cache_flags); |
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int x86_cpu_family_init(struct cpu_family *); |
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|
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|
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#endif /* CPU_X86_H */ |
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