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dpavlin |
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/* |
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* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_mips16.c,v 1.2 2005/02/21 07:18:11 debug Exp $ |
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* |
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* MIPS16 encoding support, 16-bit to 32-bit instruction translation. |
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* |
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* Included from cpu_mips.c. |
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*/ |
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#ifndef ENABLE_MIPS16 |
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/* Dummy functions if MIPS16 support is not to be included: */ |
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int mips16_to_32(struct cpu *cpu, unsigned char *instr16, |
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unsigned char *instr) |
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{ |
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fatal("mips16_to_32(): internal error! this function shouldn't " |
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"be called if ENABLE_MIPS16 isn't defined!\n"); |
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return 0; |
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} |
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#else |
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/* MIPS16 register numbers: */ |
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static int mips16_reg8_to_reg32[8] = { |
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MIPS_GPR_S0, MIPS_GPR_S1, MIPS_GPR_V0, MIPS_GPR_V1, |
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MIPS_GPR_A0, MIPS_GPR_A1, MIPS_GPR_A2, MIPS_GPR_A3 |
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}; |
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static int mips16_sp = MIPS_GPR_SP; |
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/* static int mips16_t = MIPS_GPR_T8; */ |
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/* |
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* mips16_to_32(): |
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* |
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* Translate a 16-bit MIPS16 instruction word into a normal 32-bit instruction |
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* word. instr16[1..0] ==> instr[3..0]. |
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* |
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* Returns 1 if there is a resulting 32-bit instruction, 0 if this is an |
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* "extend". |
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*/ |
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int mips16_to_32(struct cpu *cpu, unsigned char *instr16, unsigned char *instr) |
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{ |
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int rs, rd, imm, wlen; |
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int x = (instr16[1] << 8) + instr16[0]; |
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int y = 0x3e << 26; /* This should be something 'illegal', |
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so that execution stops */ |
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/* Translate 16-bit x into 32-bit y: */ |
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/* extend: */ |
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if ((x & 0xf800) == 0xf000) { |
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/* TODO: what happens if an extend is interrupted? */ |
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cpu->cd.mips.mips16_extend = x; /* save x until later */ |
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return 0; |
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} |
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/* nop: */ |
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if ((x & 0xffff) == 0x6500) { |
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y = 0x00000000; /* nop */ |
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goto mips16_ret; |
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} |
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/* move y,X: 0x67 + 3 bits rd + 5 bits rs */ |
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if ((x & 0xff00) == 0x6700) { |
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rd = (x >> 5) & 0x07; |
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rs = (x >> 0) & 0x1f; |
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/* addiu mips16_reg8_to_reg32[rd], reg32[rs], 0 */ |
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y = (HI6_ADDIU << 26) + (rs << 21) + |
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(mips16_reg8_to_reg32[rd] << 16); |
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goto mips16_ret; |
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} |
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/* ld y,D(x) { ld "y,D(x)", 0x3800, 0xf800, WR_y|RD_x, I3 } */ |
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if ((x & 0xf800) == 0x3800) { |
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wlen = 8; /* for ld */ |
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rd = (x >> 5) & 0x07; |
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rs = (x >> 8) & 0x07; |
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if (cpu->cd.mips.mips16_extend) |
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imm = (cpu->cd.mips.mips16_extend & 0x7ff) + |
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((x & 0x1f) << 11); |
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else { |
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imm = (x & 0x1f) * wlen; |
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if (imm >= 0x10) |
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imm |= 0xffe0; /* sign-extend */ |
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} |
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y = (HI6_LD << 26) + (mips16_reg8_to_reg32[rd] << 16) + |
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(rs << 21) + imm; |
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goto mips16_ret; |
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} |
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/* sd y,D(S) 0xf900, 0xff00, RD_y|RD_PC, I3 */ |
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if ((x & 0xff00) == 0xf900) { |
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wlen = 8; /* for sd */ |
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rd = (x >> 5) & 0x07; |
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rs = (x >> 8) & 0x07; |
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/* TODO */ |
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if (cpu->cd.mips.mips16_extend) { |
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imm = (cpu->cd.mips.mips16_extend & 0x7ff) + |
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((x & 0x1f) << 11); |
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} else { |
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imm = (x & 0x1f) * wlen; |
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if (imm >= 0x10) |
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imm |= 0xffe0; /* sign-extend */ |
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} |
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y = (HI6_SD << 26) + (mips16_reg8_to_reg32[rd] << 16) + |
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(rs << 21) + imm; |
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goto mips16_ret; |
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} |
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/* daddiu "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 */ |
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if ((x & 0xff00) == 0xfb00) { |
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/* TODO: this is wrong */ |
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if (cpu->cd.mips.mips16_extend) { |
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imm = ((cpu->cd.mips.mips16_extend & 0x7ff) << 5) + |
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(x & 0xff); |
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} else { |
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imm = (x & 0xff) << 3; |
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if (imm & (1 << 10)) |
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imm |= 0xf800; /* sign-extend */ |
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} |
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y = (HI6_DADDIU << 26) + (mips16_sp << 21) + (mips16_sp << 16) |
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+ (imm & 0xffff); |
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goto mips16_ret; |
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} |
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/* fatal("WARNING: unimplemented MIPS16 instruction 0x%04x\n", x); */ |
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mips16_ret: |
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instr[3] = y >> 24; instr[2] = y >> 16; |
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instr[1] = y >> 8; instr[0] = y; |
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return 1; |
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} |
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#endif /* ENABLE_MIPS16 */ |