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/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_urisc.c,v 1.6 2005/04/04 20:08:58 debug Exp $ |
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* |
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* URISC CPU emulation. See http://en.wikipedia.org/wiki/URISC for more |
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* information about the "instruction set". |
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* |
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* |
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* NOTE: |
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* |
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* The PC should always be in sync with the memory word at address 0. |
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* |
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* Optional: The accumulator register should always be in sync with the |
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* memory word following the word at address 0. |
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* |
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* This implementation of URISC emulation supports any wordlen 8*n, |
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* where 1 <= n <= 8. (I think.) |
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* |
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* |
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* TODO: |
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* |
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* o) Little-endian support? |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "misc.h" |
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|
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|
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#ifndef ENABLE_URISC |
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|
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|
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#include "cpu_urisc.h" |
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|
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|
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/* |
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* urisc_cpu_family_init(): |
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* |
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* Bogus, when ENABLE_URISC isn't defined. |
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*/ |
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int urisc_cpu_family_init(struct cpu_family *fp) |
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{ |
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return 0; |
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} |
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|
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|
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#else /* ENABLE_URISC */ |
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|
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|
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#include "cpu.h" |
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#include "cpu_urisc.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "symbol.h" |
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|
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|
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extern volatile int single_step; |
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extern int old_show_trace_tree; |
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extern int old_instruction_trace; |
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extern int old_quiet_mode; |
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extern int quiet_mode; |
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|
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|
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/* |
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* urisc_cpu_new(): |
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* |
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* Create a new URISC cpu object. |
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*/ |
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struct cpu *urisc_cpu_new(struct memory *mem, struct machine *machine, |
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int cpu_id, char *cpu_type_name) |
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{ |
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struct cpu *cpu; |
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|
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if (cpu_type_name == NULL || strcmp(cpu_type_name, "URISC") != 0) |
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return NULL; |
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|
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cpu = malloc(sizeof(struct cpu)); |
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if (cpu == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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|
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memset(cpu, 0, sizeof(struct cpu)); |
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cpu->memory_rw = urisc_memory_rw; |
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cpu->name = cpu_type_name; |
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cpu->mem = mem; |
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cpu->machine = machine; |
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cpu->cpu_id = cpu_id; |
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cpu->byte_order = EMUL_BIG_ENDIAN; |
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|
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cpu->cd.urisc.wordlen = 32; |
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cpu->cd.urisc.acc_in_mem = 0; |
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cpu->cd.urisc.halt_on_zero = 1; |
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|
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/* Only show name for CPU nr 0 (in SMP machines): */ |
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if (cpu_id == 0) { |
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debug("%s", cpu->name); |
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debug(" (%i-bit, ", cpu->cd.urisc.wordlen); |
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debug("%s-endian", cpu->byte_order == EMUL_BIG_ENDIAN? |
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"big" : "little"); |
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if (cpu->cd.urisc.acc_in_mem) |
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debug(", memory-mapped accumulator"); |
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debug(")"); |
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} |
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|
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return cpu; |
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} |
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|
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|
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/* |
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* urisc_cpu_dumpinfo(): |
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*/ |
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void urisc_cpu_dumpinfo(struct cpu *cpu) |
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{ |
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debug(" (%i-bit, ", cpu->cd.urisc.wordlen); |
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debug("%s-endian", cpu->byte_order == EMUL_BIG_ENDIAN? |
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"big" : "little"); |
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if (cpu->cd.urisc.acc_in_mem) |
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debug(", memory-mapped accumulator"); |
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debug(")\n"); |
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} |
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|
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|
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/* |
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* urisc_cpu_list_available_types(): |
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* |
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* Print a list of available URISC CPU types. |
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*/ |
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void urisc_cpu_list_available_types(void) |
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{ |
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/* TODO */ |
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|
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debug("URISC\n"); |
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} |
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|
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|
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/* |
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* urisc_cpu_register_dump(): |
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* |
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* Dump cpu registers in a relatively readable format. |
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* |
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* gprs: set to non-zero to dump GPRs and some special-purpose registers. |
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* coprocs: set bit 0..3 to dump registers in coproc 0..3. |
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*/ |
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void urisc_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs) |
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{ |
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char *symbol; |
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uint64_t offset; |
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int x = cpu->cpu_id; |
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char tmps[100]; |
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|
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
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cpu->pc, &offset); |
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sprintf(tmps, "cpu%%i: pc = 0x%%0%illx", (cpu->cd.urisc.wordlen/4)); |
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debug(tmps, x, (long long)cpu->pc); |
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debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
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sprintf(tmps, "cpu%%i: acc = 0x%%0%illx\n", (cpu->cd.urisc.wordlen/4)); |
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debug(tmps, x, (long long)cpu->cd.urisc.acc); |
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} |
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|
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|
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/* |
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* urisc_cpu_disassemble_instr(): |
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* |
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* Convert an instruction word into human readable format, for instruction |
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* tracing. |
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* |
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* If running is 1, cpu->pc should be the address of the instruction. |
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* |
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* If running is 0, things that depend on the runtime environment (eg. |
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* register contents) will not be shown, and addr will be used instead of |
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* cpu->pc for relative addresses. |
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*/ |
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int urisc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
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int running, uint64_t dumpaddr, int bintrans) |
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{ |
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uint64_t offset; |
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char *symbol; |
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int i, nbytes = cpu->cd.urisc.wordlen / 8; |
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char tmps[50]; |
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|
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if (running) |
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dumpaddr = cpu->pc; |
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|
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
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dumpaddr, &offset); |
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if (symbol != NULL && offset==0) |
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debug("<%s>\n", symbol); |
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|
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if (cpu->machine->ncpus > 1 && running) |
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debug("cpu%i: ", cpu->cpu_id); |
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sprintf(tmps, "0x%%0%illx: 0x", nbytes * 2); |
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debug(tmps, (long long)dumpaddr); |
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|
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/* TODO: Little-endian? */ |
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|
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for (i=0; i<nbytes; i++) |
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debug("%02x", instr[i]); |
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|
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if (!running) |
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debug("\n"); |
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|
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return nbytes; |
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} |
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|
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|
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/* |
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* urisc_cpu_register_match(): |
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*/ |
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void urisc_cpu_register_match(struct machine *m, char *name, |
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int writeflag, uint64_t *valuep, int *match_register) |
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{ |
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int i, cpunr = 0; |
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int nbytes = m->cpus[cpunr]->cd.urisc.wordlen / 8; |
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|
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/* CPU number: */ |
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/* TODO */ |
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|
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/* Register name: */ |
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if (strcasecmp(name, "pc") == 0) { |
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if (writeflag) { |
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unsigned char buf[8]; |
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m->cpus[cpunr]->pc = *valuep; |
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|
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for (i=0; i<nbytes; i++) |
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buf[nbytes-1-i] = *valuep >> (8*i); |
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|
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m->cpus[cpunr]->memory_rw(m->cpus[cpunr], |
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m->cpus[cpunr]->mem, 0, buf, |
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m->cpus[cpunr]->cd.urisc.wordlen / 8, MEM_WRITE, |
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CACHE_NONE | NO_EXCEPTIONS); |
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} else |
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*valuep = m->cpus[cpunr]->pc; |
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*match_register = 1; |
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} |
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|
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if (strcasecmp(name, "acc") == 0) { |
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if (writeflag) { |
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unsigned char buf[8]; |
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m->cpus[cpunr]->cd.urisc.acc = *valuep; |
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|
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if (m->cpus[cpunr]->cd.urisc.acc_in_mem) { |
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for (i=0; i<nbytes; i++) |
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buf[nbytes-1-i] = *valuep >> (8*i); |
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|
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m->cpus[cpunr]->memory_rw(m->cpus[cpunr], |
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m->cpus[cpunr]->mem, |
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m->cpus[cpunr]->cd.urisc.wordlen / 8, |
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buf, m->cpus[cpunr]->cd.urisc.wordlen / 8, |
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MEM_WRITE, CACHE_NONE | NO_EXCEPTIONS); |
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} |
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} else |
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*valuep = m->cpus[cpunr]->cd.urisc.acc; |
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*match_register = 1; |
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} |
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} |
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|
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|
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/* |
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* urisc_cpu_run_instr(): |
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* |
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* Execute one instruction on a specific CPU. |
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* |
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* Return value is the number of instructions executed during this call, |
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* 0 if no instruction was executed. |
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*/ |
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int urisc_cpu_run_instr(struct emul *emul, struct cpu *cpu) |
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{ |
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unsigned char buf[8]; |
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unsigned char instr[8]; |
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uint64_t addr, data, mask = (uint64_t) -1; |
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int skip = 0, i, nbytes = cpu->cd.urisc.wordlen / 8; |
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char tmps[100]; |
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|
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if (cpu->cd.urisc.wordlen < 64) |
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mask = ((int64_t)1 << cpu->cd.urisc.wordlen) - 1; |
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|
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/* Read PC from memory, just to be sure: */ |
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cpu->memory_rw(cpu, cpu->mem, 0, buf, nbytes, MEM_READ, CACHE_DATA); |
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cpu->pc = 0; |
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for (i=0; i<nbytes; i++) { |
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cpu->pc <<= 8; |
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cpu->pc += buf[i]; |
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} |
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|
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addr = cpu->pc; |
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|
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if (cpu->cd.urisc.halt_on_zero && cpu->pc <= 4) { |
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cpu->running = 0; |
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return 0; |
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} |
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|
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/* Advance the program counter: */ |
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cpu->pc += nbytes; |
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cpu->pc &= mask; |
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for (i=0; i<nbytes; i++) |
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buf[nbytes-1-i] = cpu->pc >> (8*i); |
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cpu->memory_rw(cpu, cpu->mem, 0, buf, nbytes, MEM_WRITE, CACHE_DATA); |
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|
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/* Read an instruction: */ |
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cpu->memory_rw(cpu, cpu->mem, addr, instr, nbytes, MEM_READ, |
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CACHE_INSTRUCTION); |
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|
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if (cpu->machine->instruction_trace) { |
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cpu->pc -= nbytes; |
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urisc_cpu_disassemble_instr(cpu, instr, 1, 0, 0); |
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cpu->pc += nbytes; |
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} |
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|
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addr = 0; |
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for (i=0; i<nbytes; i++) { |
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addr <<= 8; |
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addr += instr[i]; |
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} |
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|
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/* Read data from memory: */ |
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cpu->memory_rw(cpu, cpu->mem, addr, buf, cpu->cd.urisc.wordlen/8, |
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MEM_READ, CACHE_DATA); |
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data = 0; |
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for (i=0; i<nbytes; i++) { |
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data <<= 8; |
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data += buf[i]; |
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} |
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|
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if (cpu->machine->instruction_trace) { |
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sprintf(tmps, "\t[mem=0x%%0%illx", nbytes * 2); |
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debug(tmps, (long long)data); |
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sprintf(tmps, "; acc: 0x%%0%illx", nbytes * 2); |
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debug(tmps, (long long)cpu->cd.urisc.acc); |
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} |
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|
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skip = (uint64_t)data < (uint64_t)cpu->cd.urisc.acc; |
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|
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data -= cpu->cd.urisc.acc; |
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data &= mask; |
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|
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cpu->cd.urisc.acc = data; |
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|
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if (cpu->machine->instruction_trace) { |
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sprintf(tmps, " ==> 0x%%0%illx", nbytes * 2); |
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debug(tmps, (long long)cpu->cd.urisc.acc); |
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if (skip) |
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debug(", SKIP"); |
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debug("]\n"); |
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} |
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|
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/* Write back result to both memory and the accumulator: */ |
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for (i=0; i<nbytes; i++) |
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buf[nbytes-1-i] = cpu->cd.urisc.acc >> (8*i); |
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cpu->memory_rw(cpu, cpu->mem, addr, buf, nbytes, MEM_WRITE, CACHE_DATA); |
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if (cpu->cd.urisc.acc_in_mem) |
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cpu->memory_rw(cpu, cpu->mem, nbytes, buf, |
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nbytes, MEM_WRITE, CACHE_DATA); |
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|
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/* Skip on borrow: */ |
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if (skip) { |
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/* Read PC from memory: */ |
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cpu->memory_rw(cpu, cpu->mem, 0, buf, nbytes, |
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MEM_READ, CACHE_DATA); |
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cpu->pc = 0; |
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for (i=0; i<nbytes; i++) { |
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cpu->pc <<= 8; |
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cpu->pc += buf[i]; |
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} |
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|
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/* Advance the program counter: */ |
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cpu->pc += nbytes; |
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cpu->pc &= mask; |
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|
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for (i=0; i<nbytes; i++) |
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buf[nbytes-1-i] = cpu->pc >> (8*i); |
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cpu->memory_rw(cpu, cpu->mem, 0, buf, nbytes, MEM_WRITE, |
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CACHE_DATA); |
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} |
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|
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return 1; |
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} |
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|
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|
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#define CPU_RUN urisc_cpu_run |
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#define CPU_RINSTR urisc_cpu_run_instr |
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#define CPU_RUN_URISC |
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#include "cpu_run.c" |
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#undef CPU_RINSTR |
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#undef CPU_RUN_URISC |
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#undef CPU_RUN |
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|
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|
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#define MEMORY_RW urisc_memory_rw |
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#define MEM_URISC |
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#include "memory_rw.c" |
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#undef MEM_URISC |
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#undef MEMORY_RW |
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|
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|
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/* |
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* urisc_cpu_family_init(): |
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* |
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* Fill in the cpu_family struct for URISC. |
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*/ |
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int urisc_cpu_family_init(struct cpu_family *fp) |
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{ |
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fp->name = "URISC"; |
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fp->cpu_new = urisc_cpu_new; |
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fp->list_available_types = urisc_cpu_list_available_types; |
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fp->register_match = urisc_cpu_register_match; |
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fp->disassemble_instr = urisc_cpu_disassemble_instr; |
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fp->register_dump = urisc_cpu_register_dump; |
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fp->run = urisc_cpu_run; |
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fp->dumpinfo = urisc_cpu_dumpinfo; |
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return 1; |
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} |
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|
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#endif /* ENABLE_URISC */ |
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