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dpavlin |
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/* gxemul: $Id: wdcreg.h,v 1.2 2005/03/05 12:34:03 debug Exp $ */ |
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/* $NetBSD: wdcreg.h,v 1.25 2002/03/31 19:47:39 bouyer Exp $ */ |
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#ifndef WDCREG_H |
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#define WDCREG_H |
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/*- |
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* Copyright (c) 1991 The Regents of the University of California. |
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* All rights reserved. |
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* |
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* This code is derived from software contributed to Berkeley by |
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* William Jolitz. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed by the University of |
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* California, Berkeley and its contributors. |
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* 4. Neither the name of the University nor the names of its contributors |
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* may be used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* @(#)wdreg.h 7.1 (Berkeley) 5/9/91 |
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*/ |
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/* |
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* Disk Controller register definitions. |
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*/ |
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/* offsets of registers in the 'regular' register region */ |
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#define wd_data 0 /* data register (R/W - 16 bits) */ |
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#define wd_error 1 /* error register (R) */ |
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#define wd_precomp 1 /* write precompensation (W) */ |
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#define wd_features 1 /* features (W), same as wd_precomp */ |
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#define wd_seccnt 2 /* sector count (R/W) */ |
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#define wd_ireason 2 /* interrupt reason (R/W) (for atapi) */ |
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#define wd_sector 3 /* first sector number (R/W) */ |
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#define wd_cyl_lo 4 /* cylinder address, low byte (R/W) */ |
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#define wd_cyl_hi 5 /* cylinder address, high byte (R/W) */ |
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#define wd_sdh 6 /* sector size/drive/head (R/W) */ |
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#define wd_command 7 /* command register (W) */ |
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#define wd_status 7 /* immediate status (R) */ |
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#define wd_lba_lo 3 /* lba address, low byte (RW) */ |
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#define wd_lba_mi 4 /* lba address, middle byte (RW) */ |
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#define wd_lba_hi 5 /* lba address, high byte (RW) */ |
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/* offsets of registers in the auxiliary register region */ |
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#define wd_aux_altsts 0 /* alternate fixed disk status (R) */ |
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#define wd_aux_ctlr 0 /* fixed disk controller control (W) */ |
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#define WDCTL_4BIT 0x08 /* use four head bits (wd1003) */ |
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#define WDCTL_RST 0x04 /* reset the controller */ |
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#define WDCTL_IDS 0x02 /* disable controller interrupts */ |
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#if 0 /* NOT MAPPED; fd uses this register on PCs */ |
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#define wd_digin 1 /* disk controller input (R) */ |
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#endif |
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/* |
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* Status bits. |
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*/ |
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#define WDCS_BSY 0x80 /* busy */ |
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#define WDCS_DRDY 0x40 /* drive ready */ |
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#define WDCS_DWF 0x20 /* drive write fault */ |
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#define WDCS_DSC 0x10 /* drive seek complete */ |
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#define WDCS_DRQ 0x08 /* data request */ |
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#define WDCS_CORR 0x04 /* corrected data */ |
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#define WDCS_IDX 0x02 /* index */ |
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#define WDCS_ERR 0x01 /* error */ |
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#define WDCS_BITS \ |
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"\020\010bsy\007drdy\006dwf\005dsc\004drq\003corr\002idx\001err" |
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/* |
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* Error bits. |
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*/ |
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#define WDCE_BBK 0x80 /* bad block detected */ |
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#define WDCE_CRC 0x80 /* CRC error (Ultra-DMA only) */ |
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#define WDCE_UNC 0x40 /* uncorrectable data error */ |
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#define WDCE_MC 0x20 /* media changed */ |
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#define WDCE_IDNF 0x10 /* id not found */ |
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#define WDCE_MCR 0x08 /* media change requested */ |
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#define WDCE_ABRT 0x04 /* aborted command */ |
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#define WDCE_TK0NF 0x02 /* track 0 not found */ |
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#define WDCE_AMNF 0x01 /* address mark not found */ |
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/* |
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* Commands for Disk Controller. |
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*/ |
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#define WDCC_NOP 0x00 /* Always fail with "aborted command" */ |
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#define WDCC_RECAL 0x10 /* disk restore code -- resets cntlr */ |
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#define WDCC_READ 0x20 /* disk read code */ |
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#define WDCC_WRITE 0x30 /* disk write code */ |
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#define WDCC__LONG 0x02 /* modifier -- access ecc bytes */ |
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#define WDCC__NORETRY 0x01 /* modifier -- no retrys */ |
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#define WDCC_FORMAT 0x50 /* disk format code */ |
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#define WDCC_DIAGNOSE 0x90 /* controller diagnostic */ |
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#define WDCC_IDP 0x91 /* initialize drive parameters */ |
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#define WDCC_SMART 0xb0 /* Self Mon, Analysis, Reporting Tech */ |
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#define WDCC_READMULTI 0xc4 /* read multiple */ |
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#define WDCC_WRITEMULTI 0xc5 /* write multiple */ |
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#define WDCC_SETMULTI 0xc6 /* set multiple mode */ |
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#define WDCC_READDMA 0xc8 /* read with DMA */ |
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#define WDCC_WRITEDMA 0xca /* write with DMA */ |
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#define WDCC_ACKMC 0xdb /* acknowledge media change */ |
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#define WDCC_LOCK 0xde /* lock drawer */ |
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#define WDCC_UNLOCK 0xdf /* unlock drawer */ |
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#define WDCC_FLUSHCACHE 0xe7 /* Flush cache */ |
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#define WDCC_IDENTIFY 0xec /* read parameters from controller */ |
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#define SET_FEATURES 0xef /* set features */ |
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#define WDCC_IDLE 0xe3 /* set idle timer & enter idle mode */ |
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#define WDCC_IDLE_IMMED 0xe1 /* enter idle mode */ |
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#define WDCC_SLEEP 0xe6 /* enter sleep mode */ |
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#define WDCC_STANDBY 0xe2 /* set standby timer & enter standby */ |
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#define WDCC_STANDBY_IMMED 0xe0 /* enter standby mode */ |
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#define WDCC_CHECK_PWR 0xe5 /* check power mode */ |
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/* |
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* Big Drive support |
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*/ |
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#define WDCC_READ_EXT 0x24 /* read 48-bit addressing */ |
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#define WDCC_WRITE_EXT 0x34 /* write 48-bit addressing */ |
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#define WDCC_READMULTI_EXT 0x29 /* read multiple 48-bit addressing */ |
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#define WDCC_WRITEMULTI_EXT 0x39 /* write multiple 48-bit addressing */ |
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#define WDCC_READDMA_EXT 0x25 /* read 48-bit addressing with DMA */ |
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#define WDCC_WRITEDMA_EXT 0x35 /* write 48-bit addressing with DMA */ |
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/* Subcommands for SET_FEATURES (features register) */ |
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#define WDSF_EN_WR_CACHE 0x02 |
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#define WDSF_SET_MODE 0x03 |
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#define WDSF_REASSIGN_EN 0x04 |
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#define WDSF_RETRY_DS 0x33 |
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#define WDSF_SET_CACHE_SGMT 0x54 |
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#define WDSF_READAHEAD_DS 0x55 |
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#define WDSF_POD_DS 0x66 |
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#define WDSF_ECC_DS 0x77 |
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#define WDSF_WRITE_CACHE_DS 0x82 |
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#define WDSF_REASSIGN_DS 0x84 |
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#define WDSF_ECC_EN 0x88 |
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#define WDSF_RETRY_EN 0x99 |
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#define WDSF_SET_CURRENT 0x9a |
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#define WDSF_READAHEAD_EN 0xaa |
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#define WDSF_PREFETCH_SET 0xab |
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#define WDSF_POD_EN 0xcc |
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/* Subcommands for SMART (features register) */ |
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#define WDSM_RD_DATA 0xd0 |
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#define WDSM_ATTR_AUTOSAVE_EN 0xd2 |
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#define WDSM_SAVE_ATTR 0xd3 |
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#define WDSM_EXEC_OFFL_IMM 0xd4 |
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#define WDSM_ENABLE_OPS 0xd8 |
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#define WDSM_DISABLE_OPS 0xd9 |
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#define WDSM_STATUS 0xda |
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#define WDSMART_CYL_LO 0x4f |
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#define WDSMART_CYL_HI 0xc2 |
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/* parameters uploaded to device/heads register */ |
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#define WDSD_IBM 0xa0 /* forced to 512 byte sector, ecc */ |
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#define WDSD_CHS 0x00 /* cylinder/head/sector addressing */ |
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#define WDSD_LBA 0x40 /* logical block addressing */ |
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/* Commands for ATAPI devices */ |
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#define ATAPI_CHECK_POWER_MODE 0xe5 |
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#define ATAPI_EXEC_DRIVE_DIAGS 0x90 |
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#define ATAPI_IDLE_IMMEDIATE 0xe1 |
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#define ATAPI_NOP 0x00 |
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#define ATAPI_PKT_CMD 0xa0 |
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#define ATAPI_IDENTIFY_DEVICE 0xa1 |
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#define ATAPI_SOFT_RESET 0x08 |
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#define ATAPI_SLEEP 0xe6 |
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#define ATAPI_STANDBY_IMMEDIATE 0xe0 |
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/* Bytes used by ATAPI_PACKET_COMMAND ( feature register) */ |
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#define ATAPI_PKT_CMD_FTRE_DMA 0x01 |
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#define ATAPI_PKT_CMD_FTRE_OVL 0x02 |
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/* ireason */ |
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#define WDCI_CMD 0x01 /* command(1) or data(0) */ |
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#define WDCI_IN 0x02 /* transfer to(1) or from(0) the host */ |
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#define WDCI_RELEASE 0x04 /* bus released until completion */ |
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#define PHASE_CMDOUT (WDCS_DRQ | WDCI_CMD) |
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#define PHASE_DATAIN (WDCS_DRQ | WDCI_IN) |
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#define PHASE_DATAOUT (WDCS_DRQ) |
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#define PHASE_COMPLETED (WDCI_IN | WDCI_CMD) |
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#define PHASE_ABORTED (0) |
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#endif /* WDCREG_H */ |
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