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dpavlin |
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/* gxemul: $Id: pcireg.h,v 1.4 2005/03/05 12:34:03 debug Exp $ */ |
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/* $NetBSD: pcireg.h,v 1.37 2002/03/22 20:03:20 drochner Exp $ */ |
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#ifndef _DEV_PCI_PCIREG_H_ |
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#define _DEV_PCI_PCIREG_H_ |
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#ifdef __attribute__ |
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#undef __attribute__ |
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#endif |
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#ifdef __noreturn__ |
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#undef __noreturn__ |
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#endif |
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#define __attribute__(x) /* */ |
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#define __noreturn__ /* */ |
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/* |
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* Copyright (c) 1995, 1996, 1999, 2000 |
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* Christopher G. Demetriou. All rights reserved. |
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* Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed by Charles M. Hannum. |
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* 4. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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/* |
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* Standardized PCI configuration information |
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* |
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* XXX This is not complete. |
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*/ |
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/* |
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* Device identification register; contains a vendor ID and a device ID. |
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*/ |
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#define PCI_ID_REG 0x00 |
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typedef u_int16_t pci_vendor_id_t; |
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typedef u_int16_t pci_product_id_t; |
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#define PCI_VENDOR_SHIFT 0 |
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#define PCI_VENDOR_MASK 0xffff |
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#define PCI_VENDOR(id) \ |
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(((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) |
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#define PCI_PRODUCT_SHIFT 16 |
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#define PCI_PRODUCT_MASK 0xffff |
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#define PCI_PRODUCT(id) \ |
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(((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) |
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#define PCI_ID_CODE(vid,pid) \ |
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((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \ |
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(((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT)) \ |
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/* |
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* Command and status register. |
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*/ |
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#define PCI_COMMAND_STATUS_REG 0x04 |
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#define PCI_COMMAND_SHIFT 0 |
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#define PCI_COMMAND_MASK 0xffff |
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#define PCI_STATUS_SHIFT 16 |
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#define PCI_STATUS_MASK 0xffff |
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#define PCI_COMMAND_STATUS_CODE(cmd,stat) \ |
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((((cmd) & PCI_COMMAND_MASK) >> PCI_COMMAND_SHIFT) | \ |
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(((stat) & PCI_STATUS_MASK) >> PCI_STATUS_SHIFT)) \ |
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#define PCI_COMMAND_IO_ENABLE 0x00000001 |
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#define PCI_COMMAND_MEM_ENABLE 0x00000002 |
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#define PCI_COMMAND_MASTER_ENABLE 0x00000004 |
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#define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 |
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#define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 |
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#define PCI_COMMAND_PALETTE_ENABLE 0x00000020 |
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#define PCI_COMMAND_PARITY_ENABLE 0x00000040 |
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#define PCI_COMMAND_STEPPING_ENABLE 0x00000080 |
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#define PCI_COMMAND_SERR_ENABLE 0x00000100 |
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#define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 |
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#define PCI_STATUS_CAPLIST_SUPPORT 0x00100000 |
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#define PCI_STATUS_66MHZ_SUPPORT 0x00200000 |
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#define PCI_STATUS_UDF_SUPPORT 0x00400000 |
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#define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000 |
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#define PCI_STATUS_PARITY_ERROR 0x01000000 |
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#define PCI_STATUS_DEVSEL_FAST 0x00000000 |
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#define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 |
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#define PCI_STATUS_DEVSEL_SLOW 0x04000000 |
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#define PCI_STATUS_DEVSEL_MASK 0x06000000 |
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#define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 |
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#define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 |
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#define PCI_STATUS_MASTER_ABORT 0x20000000 |
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#define PCI_STATUS_SPECIAL_ERROR 0x40000000 |
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#define PCI_STATUS_PARITY_DETECT 0x80000000 |
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/* |
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* PCI Class and Revision Register; defines type and revision of device. |
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*/ |
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#define PCI_CLASS_REG 0x08 |
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typedef u_int8_t pci_class_t; |
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typedef u_int8_t pci_subclass_t; |
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typedef u_int8_t pci_interface_t; |
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typedef u_int8_t pci_revision_t; |
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#define PCI_CLASS_SHIFT 24 |
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#define PCI_CLASS_MASK 0xff |
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#define PCI_CLASS(cr) \ |
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(((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) |
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#define PCI_SUBCLASS_SHIFT 16 |
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#define PCI_SUBCLASS_MASK 0xff |
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#define PCI_SUBCLASS(cr) \ |
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(((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) |
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#define PCI_INTERFACE_SHIFT 8 |
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#define PCI_INTERFACE_MASK 0xff |
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#define PCI_INTERFACE(cr) \ |
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(((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) |
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#define PCI_REVISION_SHIFT 0 |
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#define PCI_REVISION_MASK 0xff |
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#define PCI_REVISION(cr) \ |
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(((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) |
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#define PCI_CLASS_CODE(mainclass, subclass, interface) \ |
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((((mainclass) & PCI_CLASS_MASK) << PCI_CLASS_SHIFT) | \ |
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(((subclass) & PCI_SUBCLASS_MASK) << PCI_SUBCLASS_SHIFT) | \ |
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(((interface) & PCI_INTERFACE_MASK) << PCI_INTERFACE_SHIFT)) |
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/* base classes */ |
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#define PCI_CLASS_PREHISTORIC 0x00 |
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#define PCI_CLASS_MASS_STORAGE 0x01 |
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#define PCI_CLASS_NETWORK 0x02 |
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#define PCI_CLASS_DISPLAY 0x03 |
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#define PCI_CLASS_MULTIMEDIA 0x04 |
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#define PCI_CLASS_MEMORY 0x05 |
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#define PCI_CLASS_BRIDGE 0x06 |
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#define PCI_CLASS_COMMUNICATIONS 0x07 |
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#define PCI_CLASS_SYSTEM 0x08 |
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#define PCI_CLASS_INPUT 0x09 |
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#define PCI_CLASS_DOCK 0x0a |
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#define PCI_CLASS_PROCESSOR 0x0b |
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#define PCI_CLASS_SERIALBUS 0x0c |
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#define PCI_CLASS_WIRELESS 0x0d |
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#define PCI_CLASS_I2O 0x0e |
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#define PCI_CLASS_SATCOM 0x0f |
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#define PCI_CLASS_CRYPTO 0x10 |
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#define PCI_CLASS_DASP 0x11 |
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#define PCI_CLASS_UNDEFINED 0xff |
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/* 0x00 prehistoric subclasses */ |
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#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 |
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#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 |
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/* 0x01 mass storage subclasses */ |
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#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 |
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#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 |
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#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 |
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#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 |
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#define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 |
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#define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05 |
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#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 |
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/* 0x02 network subclasses */ |
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#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 |
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#define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 |
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#define PCI_SUBCLASS_NETWORK_FDDI 0x02 |
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#define PCI_SUBCLASS_NETWORK_ATM 0x03 |
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#define PCI_SUBCLASS_NETWORK_ISDN 0x04 |
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#define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 |
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#define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 |
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#define PCI_SUBCLASS_NETWORK_MISC 0x80 |
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/* 0x03 display subclasses */ |
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#define PCI_SUBCLASS_DISPLAY_VGA 0x00 |
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#define PCI_SUBCLASS_DISPLAY_XGA 0x01 |
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#define PCI_SUBCLASS_DISPLAY_3D 0x02 |
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#define PCI_SUBCLASS_DISPLAY_MISC 0x80 |
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/* 0x04 multimedia subclasses */ |
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#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 |
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#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 |
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#define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 |
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#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 |
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/* 0x05 memory subclasses */ |
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#define PCI_SUBCLASS_MEMORY_RAM 0x00 |
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#define PCI_SUBCLASS_MEMORY_FLASH 0x01 |
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#define PCI_SUBCLASS_MEMORY_MISC 0x80 |
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/* 0x06 bridge subclasses */ |
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#define PCI_SUBCLASS_BRIDGE_HOST 0x00 |
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#define PCI_SUBCLASS_BRIDGE_ISA 0x01 |
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#define PCI_SUBCLASS_BRIDGE_EISA 0x02 |
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#define PCI_SUBCLASS_BRIDGE_MC 0x03 /* XXX _MCA? */ |
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#define PCI_SUBCLASS_BRIDGE_PCI 0x04 |
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#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 |
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#define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 |
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#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 |
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#define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 |
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#define PCI_SUBCLASS_BRIDGE_STPCI 0x09 |
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#define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a |
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#define PCI_SUBCLASS_BRIDGE_MISC 0x80 |
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/* 0x07 communications subclasses */ |
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#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 |
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#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 |
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#define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 |
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#define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 |
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#define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04 |
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#define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05 |
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#define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 |
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/* 0x08 system subclasses */ |
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#define PCI_SUBCLASS_SYSTEM_PIC 0x00 |
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#define PCI_SUBCLASS_SYSTEM_DMA 0x01 |
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#define PCI_SUBCLASS_SYSTEM_TIMER 0x02 |
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#define PCI_SUBCLASS_SYSTEM_RTC 0x03 |
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#define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04 |
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#define PCI_SUBCLASS_SYSTEM_MISC 0x80 |
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/* 0x09 input subclasses */ |
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#define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 |
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#define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 |
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#define PCI_SUBCLASS_INPUT_MOUSE 0x02 |
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#define PCI_SUBCLASS_INPUT_SCANNER 0x03 |
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#define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 |
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#define PCI_SUBCLASS_INPUT_MISC 0x80 |
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/* 0x0a dock subclasses */ |
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#define PCI_SUBCLASS_DOCK_GENERIC 0x00 |
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#define PCI_SUBCLASS_DOCK_MISC 0x80 |
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/* 0x0b processor subclasses */ |
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#define PCI_SUBCLASS_PROCESSOR_386 0x00 |
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#define PCI_SUBCLASS_PROCESSOR_486 0x01 |
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#define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 |
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#define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 |
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#define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 |
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#define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 |
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#define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 |
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/* 0x0c serial bus subclasses */ |
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#define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 |
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#define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 |
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#define PCI_SUBCLASS_SERIALBUS_SSA 0x02 |
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#define PCI_SUBCLASS_SERIALBUS_USB 0x03 |
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#define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 /* XXX _FIBRECHANNEL */ |
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#define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 |
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#define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 |
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#define PCI_SUBCLASS_SERIALBUS_IPMI 0x07 |
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#define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 |
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#define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 |
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/* 0x0d wireless subclasses */ |
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#define PCI_SUBCLASS_WIRELESS_IRDA 0x00 |
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#define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 |
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#define PCI_SUBCLASS_WIRELESS_RF 0x10 |
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#define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11 |
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#define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12 |
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#define PCI_SUBCLASS_WIRELESS_MISC 0x80 |
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/* 0x0e I2O (Intelligent I/O) subclasses */ |
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#define PCI_SUBCLASS_I2O_STANDARD 0x00 |
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/* 0x0f satellite communication subclasses */ |
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/* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */ |
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#define PCI_SUBCLASS_SATCOM_TV 0x01 |
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#define PCI_SUBCLASS_SATCOM_AUDIO 0x02 |
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#define PCI_SUBCLASS_SATCOM_VOICE 0x03 |
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#define PCI_SUBCLASS_SATCOM_DATA 0x04 |
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/* 0x10 encryption/decryption subclasses */ |
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#define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00 |
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#define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 |
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#define PCI_SUBCLASS_CRYPTO_MISC 0x80 |
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/* 0x11 data acquisition and signal processing subclasses */ |
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#define PCI_SUBCLASS_DASP_DPIO 0x00 |
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#define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 |
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#define PCI_SUBCLASS_DASP_SYNC 0x10 |
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#define PCI_SUBCLASS_DASP_MGMT 0x20 |
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#define PCI_SUBCLASS_DASP_MISC 0x80 |
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/* |
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* PCI BIST/Header Type/Latency Timer/Cache Line Size Register. |
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*/ |
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#define PCI_BHLC_REG 0x0c |
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#define PCI_BIST_SHIFT 24 |
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#define PCI_BIST_MASK 0xff |
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#define PCI_BIST(bhlcr) \ |
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(((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) |
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#define PCI_HDRTYPE_SHIFT 16 |
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#define PCI_HDRTYPE_MASK 0xff |
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#define PCI_HDRTYPE(bhlcr) \ |
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(((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) |
| 320 |
|
|
|
| 321 |
|
|
#define PCI_HDRTYPE_TYPE(bhlcr) \ |
| 322 |
|
|
(PCI_HDRTYPE(bhlcr) & 0x7f) |
| 323 |
|
|
#define PCI_HDRTYPE_MULTIFN(bhlcr) \ |
| 324 |
|
|
((PCI_HDRTYPE(bhlcr) & 0x80) != 0) |
| 325 |
|
|
|
| 326 |
|
|
#define PCI_LATTIMER_SHIFT 8 |
| 327 |
|
|
#define PCI_LATTIMER_MASK 0xff |
| 328 |
|
|
#define PCI_LATTIMER(bhlcr) \ |
| 329 |
|
|
(((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) |
| 330 |
|
|
|
| 331 |
|
|
#define PCI_CACHELINE_SHIFT 0 |
| 332 |
|
|
#define PCI_CACHELINE_MASK 0xff |
| 333 |
|
|
#define PCI_CACHELINE(bhlcr) \ |
| 334 |
|
|
(((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) |
| 335 |
|
|
|
| 336 |
|
|
#define PCI_BHLC_CODE(bist,type,multi,latency,cacheline) \ |
| 337 |
|
|
((((bist) & PCI_BIST_MASK) << PCI_BIST_SHIFT) | \ |
| 338 |
|
|
(((type) & PCI_HDRTYPE_MASK) << PCI_HDRTYPE_SHIFT) | \ |
| 339 |
|
|
(((multi)?0x80:0) << PCI_HDRTYPE_SHIFT) | \ |
| 340 |
|
|
(((latency) & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT) | \ |
| 341 |
|
|
(((cacheline) & PCI_CACHELINE_MASK) << PCI_CACHELINE_SHIFT)) |
| 342 |
|
|
|
| 343 |
|
|
/* |
| 344 |
|
|
* Mapping registers |
| 345 |
|
|
*/ |
| 346 |
|
|
#define PCI_MAPREG_START 0x10 |
| 347 |
|
|
#define PCI_MAPREG_END 0x28 |
| 348 |
|
|
#define PCI_MAPREG_ROM 0x30 |
| 349 |
|
|
#define PCI_MAPREG_PPB_END 0x18 |
| 350 |
|
|
#define PCI_MAPREG_PCB_END 0x14 |
| 351 |
|
|
|
| 352 |
|
|
#define PCI_MAPREG_TYPE(mr) \ |
| 353 |
|
|
((mr) & PCI_MAPREG_TYPE_MASK) |
| 354 |
|
|
#define PCI_MAPREG_TYPE_MASK 0x00000001 |
| 355 |
|
|
|
| 356 |
|
|
#define PCI_MAPREG_TYPE_MEM 0x00000000 |
| 357 |
|
|
#define PCI_MAPREG_TYPE_IO 0x00000001 |
| 358 |
|
|
#define PCI_MAPREG_ROM_ENABLE 0x00000001 |
| 359 |
|
|
|
| 360 |
|
|
#define PCI_MAPREG_MEM_TYPE(mr) \ |
| 361 |
|
|
((mr) & PCI_MAPREG_MEM_TYPE_MASK) |
| 362 |
|
|
#define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 |
| 363 |
|
|
|
| 364 |
|
|
#define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 |
| 365 |
|
|
#define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 |
| 366 |
|
|
#define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 |
| 367 |
|
|
|
| 368 |
|
|
#define PCI_MAPREG_MEM_PREFETCHABLE(mr) \ |
| 369 |
|
|
(((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0) |
| 370 |
|
|
#define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 |
| 371 |
|
|
|
| 372 |
|
|
#define PCI_MAPREG_MEM_ADDR(mr) \ |
| 373 |
|
|
((mr) & PCI_MAPREG_MEM_ADDR_MASK) |
| 374 |
|
|
#define PCI_MAPREG_MEM_SIZE(mr) \ |
| 375 |
|
|
(PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) |
| 376 |
|
|
#define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 |
| 377 |
|
|
|
| 378 |
|
|
#define PCI_MAPREG_MEM64_ADDR(mr) \ |
| 379 |
|
|
((mr) & PCI_MAPREG_MEM64_ADDR_MASK) |
| 380 |
|
|
#define PCI_MAPREG_MEM64_SIZE(mr) \ |
| 381 |
|
|
(PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) |
| 382 |
|
|
#define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL |
| 383 |
|
|
|
| 384 |
|
|
#define PCI_MAPREG_IO_ADDR(mr) \ |
| 385 |
|
|
((mr) & PCI_MAPREG_IO_ADDR_MASK) |
| 386 |
|
|
#define PCI_MAPREG_IO_SIZE(mr) \ |
| 387 |
|
|
(PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) |
| 388 |
|
|
#define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc |
| 389 |
|
|
|
| 390 |
|
|
#define PCI_MAPREG_SIZE_TO_MASK(size) \ |
| 391 |
|
|
(-(size)) |
| 392 |
|
|
|
| 393 |
|
|
#define PCI_MAPREG_NUM(offset) \ |
| 394 |
|
|
(((unsigned)(offset)-PCI_MAPREG_START)/4) |
| 395 |
|
|
|
| 396 |
|
|
|
| 397 |
|
|
/* |
| 398 |
|
|
* Cardbus CIS pointer (PCI rev. 2.1) |
| 399 |
|
|
*/ |
| 400 |
|
|
#define PCI_CARDBUS_CIS_REG 0x28 |
| 401 |
|
|
|
| 402 |
|
|
/* |
| 403 |
|
|
* Subsystem identification register; contains a vendor ID and a device ID. |
| 404 |
|
|
* Types/macros for PCI_ID_REG apply. |
| 405 |
|
|
* (PCI rev. 2.1) |
| 406 |
|
|
*/ |
| 407 |
|
|
#define PCI_SUBSYS_ID_REG 0x2c |
| 408 |
|
|
|
| 409 |
|
|
/* |
| 410 |
|
|
* capabilities link list (PCI rev. 2.2) |
| 411 |
|
|
*/ |
| 412 |
|
|
#define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */ |
| 413 |
|
|
#define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */ |
| 414 |
|
|
#define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) |
| 415 |
|
|
#define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) |
| 416 |
|
|
#define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) |
| 417 |
|
|
|
| 418 |
|
|
#define PCI_CAP_RESERVED0 0x00 |
| 419 |
|
|
#define PCI_CAP_PWRMGMT 0x01 |
| 420 |
|
|
#define PCI_CAP_AGP 0x02 |
| 421 |
|
|
#define PCI_CAP_VPD 0x03 |
| 422 |
|
|
#define PCI_CAP_SLOTID 0x04 |
| 423 |
|
|
#define PCI_CAP_MBI 0x05 |
| 424 |
|
|
#define PCI_CAP_CPCI_HOTSWAP 0x06 |
| 425 |
|
|
#define PCI_CAP_PCIX 0x07 |
| 426 |
|
|
#define PCI_CAP_LDT 0x08 |
| 427 |
|
|
#define PCI_CAP_VENDSPEC 0x09 |
| 428 |
|
|
#define PCI_CAP_DEBUGPORT 0x0a |
| 429 |
|
|
#define PCI_CAP_CPCI_RSRCCTL 0x0b |
| 430 |
|
|
#define PCI_CAP_HOTPLUG 0x0c |
| 431 |
|
|
|
| 432 |
|
|
/* |
| 433 |
|
|
* Power Management Control Status Register; access via capability pointer. |
| 434 |
|
|
*/ |
| 435 |
|
|
|
| 436 |
|
|
#define PCI_PMCSR_STATE_MASK 0x03 |
| 437 |
|
|
#define PCI_PMCSR_STATE_D0 0x00 |
| 438 |
|
|
#define PCI_PMCSR_STATE_D1 0x01 |
| 439 |
|
|
#define PCI_PMCSR_STATE_D2 0x02 |
| 440 |
|
|
#define PCI_PMCSR_STATE_D3 0x03 |
| 441 |
|
|
|
| 442 |
|
|
/* |
| 443 |
|
|
* Interrupt Configuration Register; contains interrupt pin and line. |
| 444 |
|
|
*/ |
| 445 |
|
|
#define PCI_INTERRUPT_REG 0x3c |
| 446 |
|
|
|
| 447 |
|
|
typedef u_int8_t pci_intr_latency_t; |
| 448 |
|
|
typedef u_int8_t pci_intr_grant_t; |
| 449 |
|
|
typedef u_int8_t pci_intr_pin_t; |
| 450 |
|
|
typedef u_int8_t pci_intr_line_t; |
| 451 |
|
|
|
| 452 |
|
|
#define PCI_MAX_LAT_SHIFT 24 |
| 453 |
|
|
#define PCI_MAX_LAT_MASK 0xff |
| 454 |
|
|
#define PCI_MAX_LAT(icr) \ |
| 455 |
|
|
(((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK) |
| 456 |
|
|
|
| 457 |
|
|
#define PCI_MIN_GNT_SHIFT 16 |
| 458 |
|
|
#define PCI_MIN_GNT_MASK 0xff |
| 459 |
|
|
#define PCI_MIN_GNT(icr) \ |
| 460 |
|
|
(((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK) |
| 461 |
|
|
|
| 462 |
|
|
#define PCI_INTERRUPT_GRANT_SHIFT 24 |
| 463 |
|
|
#define PCI_INTERRUPT_GRANT_MASK 0xff |
| 464 |
|
|
#define PCI_INTERRUPT_GRANT(icr) \ |
| 465 |
|
|
(((icr) >> PCI_INTERRUPT_GRANT_SHIFT) & PCI_INTERRUPT_GRANT_MASK) |
| 466 |
|
|
|
| 467 |
|
|
#define PCI_INTERRUPT_LATENCY_SHIFT 16 |
| 468 |
|
|
#define PCI_INTERRUPT_LATENCY_MASK 0xff |
| 469 |
|
|
#define PCI_INTERRUPT_LATENCY(icr) \ |
| 470 |
|
|
(((icr) >> PCI_INTERRUPT_LATENCY_SHIFT) & PCI_INTERRUPT_LATENCY_MASK) |
| 471 |
|
|
|
| 472 |
|
|
#define PCI_INTERRUPT_PIN_SHIFT 8 |
| 473 |
|
|
#define PCI_INTERRUPT_PIN_MASK 0xff |
| 474 |
|
|
#define PCI_INTERRUPT_PIN(icr) \ |
| 475 |
|
|
(((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) |
| 476 |
|
|
|
| 477 |
|
|
#define PCI_INTERRUPT_LINE_SHIFT 0 |
| 478 |
|
|
#define PCI_INTERRUPT_LINE_MASK 0xff |
| 479 |
|
|
#define PCI_INTERRUPT_LINE(icr) \ |
| 480 |
|
|
(((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) |
| 481 |
|
|
|
| 482 |
|
|
#define PCI_INTERRUPT_CODE(lat,gnt,pin,line) \ |
| 483 |
|
|
((((lat)&PCI_INTERRUPT_LATENCY_MASK)<<PCI_INTERRUPT_LATENCY_SHIFT)| \ |
| 484 |
|
|
(((gnt)&PCI_INTERRUPT_GRANT_MASK) <<PCI_INTERRUPT_GRANT_SHIFT) | \ |
| 485 |
|
|
(((pin)&PCI_INTERRUPT_PIN_MASK) <<PCI_INTERRUPT_PIN_SHIFT) | \ |
| 486 |
|
|
(((line)&PCI_INTERRUPT_LINE_MASK) <<PCI_INTERRUPT_LINE_SHIFT)) |
| 487 |
|
|
|
| 488 |
|
|
#define PCI_INTERRUPT_PIN_NONE 0x00 |
| 489 |
|
|
#define PCI_INTERRUPT_PIN_A 0x01 |
| 490 |
|
|
#define PCI_INTERRUPT_PIN_B 0x02 |
| 491 |
|
|
#define PCI_INTERRUPT_PIN_C 0x03 |
| 492 |
|
|
#define PCI_INTERRUPT_PIN_D 0x04 |
| 493 |
|
|
#define PCI_INTERRUPT_PIN_MAX 0x04 |
| 494 |
|
|
|
| 495 |
|
|
/* Header Type 1 (Bridge) configuration registers */ |
| 496 |
|
|
#define PCI_BRIDGE_BUS_REG 0x18 |
| 497 |
|
|
#define PCI_BRIDGE_BUS_PRIMARY_SHIFT 0 |
| 498 |
|
|
#define PCI_BRIDGE_BUS_SECONDARY_SHIFT 8 |
| 499 |
|
|
#define PCI_BRIDGE_BUS_SUBORDINATE_SHIFT 16 |
| 500 |
|
|
|
| 501 |
|
|
#define PCI_BRIDGE_STATIO_REG 0x1C |
| 502 |
|
|
#define PCI_BRIDGE_STATIO_IOBASE_SHIFT 0 |
| 503 |
|
|
#define PCI_BRIDGE_STATIO_IOLIMIT_SHIFT 8 |
| 504 |
|
|
#define PCI_BRIDGE_STATIO_STATUS_SHIFT 16 |
| 505 |
|
|
#define PCI_BRIDGE_STATIO_IOBASE_MASK 0xf0 |
| 506 |
|
|
#define PCI_BRIDGE_STATIO_IOLIMIT_MASK 0xf0 |
| 507 |
|
|
#define PCI_BRIDGE_STATIO_STATUS_MASK 0xffff |
| 508 |
|
|
#define PCI_BRIDGE_IO_32BITS(reg) (((reg) & 0xf) == 1) |
| 509 |
|
|
|
| 510 |
|
|
#define PCI_BRIDGE_MEMORY_REG 0x20 |
| 511 |
|
|
#define PCI_BRIDGE_MEMORY_BASE_SHIFT 4 |
| 512 |
|
|
#define PCI_BRIDGE_MEMORY_LIMIT_SHIFT 20 |
| 513 |
|
|
#define PCI_BRIDGE_MEMORY_BASE_MASK 0xffff |
| 514 |
|
|
#define PCI_BRIDGE_MEMORY_LIMIT_MASK 0xffff |
| 515 |
|
|
|
| 516 |
|
|
#define PCI_BRIDGE_PREFETCHMEM_REG 0x24 |
| 517 |
|
|
#define PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT 4 |
| 518 |
|
|
#define PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT 20 |
| 519 |
|
|
#define PCI_BRIDGE_PREFETCHMEM_BASE_MASK 0xffff |
| 520 |
|
|
#define PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK 0xffff |
| 521 |
|
|
#define PCI_BRIDGE_PREFETCHMEM_64BITS(reg) ((reg) & 0xf) |
| 522 |
|
|
|
| 523 |
|
|
#define PCI_BRIDGE_PREFETCHBASE32_REG 0x28 |
| 524 |
|
|
#define PCI_BRIDGE_PREFETCHLIMIT32_REG 0x2C |
| 525 |
|
|
|
| 526 |
|
|
#define PCI_BRIDGE_IOHIGH_REG 0x30 |
| 527 |
|
|
#define PCI_BRIDGE_IOHIGH_BASE_SHIFT 0 |
| 528 |
|
|
#define PCI_BRIDGE_IOHIGH_LIMIT_SHIFT 16 |
| 529 |
|
|
#define PCI_BRIDGE_IOHIGH_BASE_MASK 0xffff |
| 530 |
|
|
#define PCI_BRIDGE_IOHIGH_LIMIT_MASK 0xffff |
| 531 |
|
|
|
| 532 |
|
|
#define PCI_BRIDGE_CONTROL_REG 0x3C |
| 533 |
|
|
#define PCI_BRIDGE_CONTROL_SHIFT 16 |
| 534 |
|
|
#define PCI_BRIDGE_CONTROL_MASK 0xffff |
| 535 |
|
|
#define PCI_BRIDGE_CONTROL_PERE (1 << 0) |
| 536 |
|
|
#define PCI_BRIDGE_CONTROL_SERR (1 << 1) |
| 537 |
|
|
#define PCI_BRIDGE_CONTROL_ISA (1 << 2) |
| 538 |
|
|
#define PCI_BRIDGE_CONTROL_VGA (1 << 3) |
| 539 |
|
|
/* Reserved (1 << 4) */ |
| 540 |
|
|
#define PCI_BRIDGE_CONTROL_MABRT (1 << 5) |
| 541 |
|
|
#define PCI_BRIDGE_CONTROL_SECBR (1 << 6) |
| 542 |
|
|
#define PCI_BRIDGE_CONTROL_SECFASTB2B (1 << 7) |
| 543 |
|
|
#define PCI_BRIDGE_CONTROL_PRI_DISC_TIMER (1 << 8) |
| 544 |
|
|
#define PCI_BRIDGE_CONTROL_SEC_DISC_TIMER (1 << 9) |
| 545 |
|
|
#define PCI_BRIDGE_CONTROL_DISC_TIMER_STAT (1 << 10) |
| 546 |
|
|
#define PCI_BRIDGE_CONTROL_DISC_TIMER_SERR (1 << 11) |
| 547 |
|
|
/* Reserved (1 << 12) - (1 << 15) */ |
| 548 |
|
|
|
| 549 |
|
|
/* |
| 550 |
|
|
* Vital Product Data resource tags. |
| 551 |
|
|
*/ |
| 552 |
|
|
struct pci_vpd_smallres { |
| 553 |
|
|
uint8_t vpdres_byte0; /* length of data + tag */ |
| 554 |
|
|
/* Actual data. */ |
| 555 |
|
|
} __attribute__((__packed__)); |
| 556 |
|
|
|
| 557 |
|
|
struct pci_vpd_largeres { |
| 558 |
|
|
uint8_t vpdres_byte0; |
| 559 |
|
|
uint8_t vpdres_len_lsb; /* length of data only */ |
| 560 |
|
|
uint8_t vpdres_len_msb; |
| 561 |
|
|
/* Actual data. */ |
| 562 |
|
|
} __attribute__((__packed__)); |
| 563 |
|
|
|
| 564 |
|
|
#define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) |
| 565 |
|
|
|
| 566 |
|
|
#define PCI_VPDRES_SMALL_LENGTH(x) ((x) & 0x7) |
| 567 |
|
|
#define PCI_VPDRES_SMALL_NAME(x) (((x) >> 3) & 0xf) |
| 568 |
|
|
|
| 569 |
|
|
#define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) |
| 570 |
|
|
|
| 571 |
|
|
#define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID 0x3 /* small */ |
| 572 |
|
|
#define PCI_VPDRES_TYPE_VENDOR_DEFINED 0xe /* small */ |
| 573 |
|
|
#define PCI_VPDRES_TYPE_END_TAG 0xf /* small */ |
| 574 |
|
|
|
| 575 |
|
|
#define PCI_VPDRES_TYPE_IDENTIFIER_STRING 0x02 /* large */ |
| 576 |
|
|
#define PCI_VPDRES_TYPE_VPD 0x10 /* large */ |
| 577 |
|
|
|
| 578 |
|
|
struct pci_vpd { |
| 579 |
|
|
uint8_t vpd_key0; |
| 580 |
|
|
uint8_t vpd_key1; |
| 581 |
|
|
uint8_t vpd_len; /* length of data only */ |
| 582 |
|
|
/* Actual data. */ |
| 583 |
|
|
} __attribute__((__packed__)); |
| 584 |
|
|
|
| 585 |
|
|
/* |
| 586 |
|
|
* Recommended VPD fields: |
| 587 |
|
|
* |
| 588 |
|
|
* PN Part number of assembly |
| 589 |
|
|
* FN FRU part number |
| 590 |
|
|
* EC EC level of assembly |
| 591 |
|
|
* MN Manufacture ID |
| 592 |
|
|
* SN Serial Number |
| 593 |
|
|
* |
| 594 |
|
|
* Conditionally recommended VPD fields: |
| 595 |
|
|
* |
| 596 |
|
|
* LI Load ID |
| 597 |
|
|
* RL ROM Level |
| 598 |
|
|
* RM Alterable ROM Level |
| 599 |
|
|
* NA Network Address |
| 600 |
|
|
* DD Device Driver Level |
| 601 |
|
|
* DG Diagnostic Level |
| 602 |
|
|
* LL Loadable Microcode Level |
| 603 |
|
|
* VI Vendor ID/Device ID |
| 604 |
|
|
* FU Function Number |
| 605 |
|
|
* SI Subsystem Vendor ID/Subsystem ID |
| 606 |
|
|
* |
| 607 |
|
|
* Additional VPD fields: |
| 608 |
|
|
* |
| 609 |
|
|
* Z0-ZZ User/Product Specific |
| 610 |
|
|
*/ |
| 611 |
|
|
|
| 612 |
|
|
#endif /* _DEV_PCI_PCIREG_H_ */ |
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