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dpavlin |
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/* gxemul: $Id: if_mecreg.h,v 1.2 2005/03/05 12:34:02 debug Exp $ */ |
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/* $NetBSD: if_mecreg.h,v 1.2 2004/07/11 03:13:04 tsutsui Exp $ */ |
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#ifndef IF_MECREG_H |
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#define IF_MECREG_H |
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/* |
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* Copyright (c) 2001 Christopher Sekiya |
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* Copyright (c) 2000 Soren S. Jorvang |
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* All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed for the |
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* NetBSD Project. See http://www.NetBSD.org/ for |
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* information about NetBSD. |
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* 4. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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/* |
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* MACE MAC110 ethernet register definitions |
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*/ |
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#define MEC_MAC_CONTROL 0x00 |
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#define MEC_MAC_CORE_RESET 0x0000000000000001 /* reset signal */ |
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#define MEC_MAC_FULL_DUPLEX 0x0000000000000002 /* 1 to enable */ |
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#define MEC_MAC_INT_LOOPBACK 0x0000000000000004 /* 0 = normal op */ |
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#define MEC_MAC_SPEED_SELECT 0x0000000000000008 /* 0/1 10/100 */ |
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#define MEC_MAC_MII_SELECT 0x0000000000000010 /* MII/SIA */ |
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#define MEC_MAC_FILTER_MASK 0x0000000000000060 |
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#define MEC_MAC_FILTER_STATION 0x0000000000000000 |
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#define MEC_MAC_FILTER_MATCHMULTI 0x0000000000000020 |
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#define MEC_MAC_FILTER_ALLMULTI 0x0000000000000040 |
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#define MEC_MAC_FILTER_PROMISC 0x0000000000000060 |
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#define MEC_MAC_LINK_FAILURE 0x0000000000000080 |
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#define MEC_MAC_IPGT 0x0000000000007f00 /* interpacket gap */ |
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#define MEC_MAC_IPGT_SHIFT 8 |
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#define MEC_MAC_IPGR1 0x00000000003f8000 |
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#define MEC_MAC_IPGR1_SHIFT 15 |
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#define MEC_MAC_IPGR2 0x000000001fc00000 |
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#define MEC_MAC_IPGR2_SHIFT 22 |
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#define MEC_MAC_REVISION 0x00000000e0000000 |
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#define MEC_MAC_REVISION_SHIFT 29 |
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#define MEC_MAC_IPG_DEFAULT \ |
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(21 << MEC_MAC_IPGT_SHIFT) | \ |
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(17 << MEC_MAC_IPGR1_SHIFT) | \ |
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(11 << MEC_MAC_IPGR2_SHIFT) |
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#define MEC_INT_STATUS 0x08 |
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#define MEC_INT_STATUS_MASK 0x00000000000000ff |
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#define MEC_INT_TX_EMPTY 0x0000000000000001 |
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#define MEC_INT_TX_PACKET_SENT 0x0000000000000002 |
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#define MEC_INT_TX_LINK_FAIL 0x0000000000000004 |
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#define MEC_INT_TX_MEM_ERROR 0x0000000000000008 |
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#define MEC_INT_TX_ABORT 0x0000000000000010 |
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#define MEC_INT_RX_THRESHOLD 0x0000000000000020 |
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#define MEC_INT_RX_FIFO_UNDERFLOW 0x0000000000000040 |
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#define MEC_INT_RX_DMA_UNDERFLOW 0x0000000000000080 |
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#define MEC_INT_RX_MCL_FIFO_ALIAS 0x0000000000001f00 |
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#define MEC_INT_TX_RING_BUFFER_ALIAS 0x0000000001ff0000 |
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#define MEC_INT_RX_SEQUENCE_NUMBER 0x000000003e000000 |
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#define MEC_INT_MCAST_HASH_OUTPUT 0x0000000040000000 |
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#define MEC_DMA_CONTROL 0x10 |
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#define MEC_DMA_TX_INT_ENABLE 0x0000000000000001 |
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#define MEC_DMA_TX_DMA_ENABLE 0x0000000000000002 |
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#define MEC_DMA_TX_RING_SIZE_MASK 0x000000000000000c |
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#define MEC_DMA_RX_INT_THRESHOLD 0x00000000000001f0 |
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#define MEC_DMA_RX_INT_THRESH_SHIFT 4 |
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#define MEC_DMA_RX_INT_ENABLE 0x0000000000000200 |
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#define MEC_DMA_RX_RUNT 0x0000000000000400 |
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#define MEC_DMA_RX_PACKET_GATHER 0x0000000000000800 |
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#define MEC_DMA_RX_DMA_OFFSET 0x0000000000007000 |
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#define MEC_DMA_RX_DMA_OFFSET_SHIFT 12 |
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#define MEC_DMA_RX_DMA_ENABLE 0x0000000000008000 |
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#define MEC_TIMER 0x18 |
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#define MEC_TX_ALIAS 0x20 |
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#define MEC_TX_ALIAS_INT_ENABLE 0x0000000000000001 |
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#define MEC_RX_ALIAS 0x28 |
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#define MEC_RX_ALIAS_INT_ENABLE 0x0000000000000200 |
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#define MEC_RX_ALIAS_INT_THRESHOLD 0x00000000000001f0 |
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#define MEC_TX_RING_PTR 0x30 |
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#define MEC_TX_RING_WRITE_PTR 0x00000000000001ff |
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#define MEC_TX_RING_READ_PTR 0x0000000001ff0000 |
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#define MEC_TX_RING_PTR_ALIAS 0x38 |
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#define MEC_RX_FIFO 0x40 |
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#define MEC_RX_FIFO_ELEMENT_COUNT 0x000000000000001f |
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#define MEC_RX_FIFO_READ_PTR 0x0000000000000f00 |
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#define MEC_RX_FIFO_GEN_NUMBER 0x0000000000001000 |
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#define MEC_RX_FIFO_WRITE_PTR 0x00000000000f0000 |
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#define MEC_RX_FIFO_GEN_NUMBER_2 0x0000000000100000 |
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#define MEC_RX_FIFO_ALIAS1 0x48 |
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#define MEC_RX_FIFO_ALIAS2 0x50 |
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#define MEC_TX_VECTOR 0x58 |
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#define MEC_IRQ_VECTOR 0x58 |
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#define MEC_PHY_DATA_PAD 0x60 /* XXX ? */ |
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#define MEC_PHY_DATA 0x64 |
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#define MEC_PHY_DATA_BUSY 0x00010000 |
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#define MEC_PHY_DATA_VALUE 0x0000ffff |
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#define MEC_PHY_ADDRESS_PAD 0x68 /* XXX ? */ |
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#define MEC_PHY_ADDRESS 0x6c |
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#define MEC_PHY_ADDR_REGISTER 0x0000001f |
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#define MEC_PHY_ADDR_DEVICE 0x000003e0 |
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#define MEC_PHY_ADDR_DEVSHIFT 5 |
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#define MEC_PHY_READ_INITIATE 0x70 |
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#define MEC_PHY_BACKOFF 0x78 |
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#define MEC_STATION 0xa0 |
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#define MEC_STATION_ALT 0xa8 |
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#define MEC_STATION_MASK 0x0000ffffffffffffULL |
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#define MEC_MULTICAST 0xb0 |
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#define MEC_TX_RING_BASE 0xb8 |
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#define MEC_TX_PKT1_CMD_1 0xc0 |
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#define MEC_TX_PKT1_BUFFER_1 0xc8 |
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#define MEC_TX_PKT1_BUFFER_2 0xd0 |
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#define MEC_TX_PKT1_BUFFER_3 0xd8 |
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#define MEC_TX_PKT2_CMD_1 0xe0 |
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#define MEC_TX_PKT2_BUFFER_1 0xe8 |
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#define MEC_TX_PKT2_BUFFER_2 0xf0 |
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#define MEC_TX_PKT2_BUFFER_3 0xf8 |
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#define MEC_MCL_RX_FIFO 0x100 |
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#endif /* IF_MECREG_H */ |
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