0.3.1/include/cpu_ppc.h

#ifndef CPU_PPC_H
#define CPU_PPC_H

/*
 *  Copyright (C) 2005  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_ppc.h,v 1.22 2005/03/08 22:58:58 debug Exp $
 */

#include "misc.h"


struct cpu_family;

#define MODE_PPC                0
#define MODE_POWER              1

/*  PPC CPU types:  */
struct ppc_cpu_type_def { 
        char            *name;
        int             bits;
        int             flags;
        int             icache_shift;
        int             iway;
        int             dcache_shift;
        int             dway;
        int             l2cache_shift;
        int             l2way;
        int             altivec;

        /*  TODO: POWER vs PowerPC?  */
};

/*  Flags:  */
#define PPC_NOFP                1
/*  TODO: Most of these just bogus  */

#define PPC_CPU_TYPE_DEFS       {                               \
        { "PPC405GP", 32, PPC_NOFP, 15, 2, 15, 2, 20, 1, 0 },   \
        { "PPC603e", 32, 0, 14, 4, 14, 4, 0, 0, 0 },            \
        { "MPC7400", 32, 0, 15, 2, 15, 2, 19, 1, 1 },           \
        { "PPC750", 32, 0, 15, 2, 15, 2, 20, 1, 0 },            \
        { "G4e", 32, 0, 15, 8, 15, 8, 18, 8, 1 },               \
        { "PPC970", 64, 0, 16, 1, 15, 2, 19, 1, 1 },            \
        { NULL, 0, 0, 0,0, 0,0, 0,0, 0 }                        \
        };

#define PPC_NGPRS               32
#define PPC_NFPRS               32

struct ppc_cpu {
        struct ppc_cpu_type_def cpu_type;

        int             trace_tree_depth;

        uint64_t        of_emul_addr;
        uint64_t        pc_last;

        int             mode;           /*  MODE_PPC or MODE_POWER  */
        int             bits;           /*  32 or 64  */

        uint32_t        cr;             /*  Condition Register  */
        uint32_t        fpscr;          /*  FP Status and Control Register  */
        uint64_t        lr;             /*  Link Register  */
        uint64_t        ctr;            /*  Count Register  */
        uint64_t        gpr[PPC_NGPRS]; /*  General Purpose Registers  */
        uint64_t        xer;            /*  FP Exception Register  */
        uint64_t        fpr[PPC_NFPRS]; /*  Floating-Point Registers  */

        uint32_t        tbl;            /*  Time Base Lower  */
        uint32_t        tbu;            /*  Time Base Upper  */
        uint32_t        dec;            /*  Decrementer  */
        uint32_t        hdec;           /*  Hypervisor Decrementer  */
        uint64_t        ssr0;           /*  Machine status save/restore
                                            register 0  */
        uint64_t        ssr1;           /*  Machine status save/restore
                                            register 1  */
        uint64_t        msr;            /*  Machine state register  */
        uint64_t        sprg0;          /*  Special Purpose Register G0  */
        uint64_t        sprg1;          /*  Special Purpose Register G1  */
        uint64_t        sprg2;          /*  Special Purpose Register G2  */
        uint64_t        sprg3;          /*  Special Purpose Register G3  */
        uint32_t        pvr;            /*  Processor Version Register  */
        uint32_t        pir;            /*  Processor ID  */
};


/*  Machine status word bits: (according to Book 3)  */
#define PPC_MSR_SF      (1ULL << 63)    /*  Sixty-Four-Bit Mode  */
/*  bits 62..61 are reserved  */
#define PPC_MSR_HV      (1ULL << 60)    /*  Hypervisor  */
/*  bits 59..17  are reserved  */
#define PPC_MSR_ILE     (1 << 16)       /*  Interrupt Little-Endian Mode  */
#define PPC_MSR_EE      (1 << 15)       /*  External Interrupt Enable  */
#define PPC_MSR_PR      (1 << 14)       /*  Problem State  */
#define PPC_MSR_FP      (1 << 13)       /*  Floating-Point Available  */
#define PPC_MSR_ME      (1 << 12)       /*  Machine Check Interrupt Enable  */
#define PPC_MSR_FE0     (1 << 11)       /*  Floating-Point Exception Mode 0  */
#define PPC_MSR_SE      (1 << 10)       /*  Single-Step Trace Enable  */
#define PPC_MSR_BE      (1 << 9)        /*  Branch Trace Enable  */
#define PPC_MSR_FE1     (1 << 8)        /*  Floating-Point Exception Mode 1  */
#define PPC_MSR_IR      (1 << 5)        /*  Instruction Relocate  */
#define PPC_MSR_DR      (1 << 4)        /*  Data Relocate  */
#define PPC_MSR_PMM     (1 << 2)        /*  Performance Monitor Mark  */
#define PPC_MSR_RI      (1 << 1)        /*  Recoverable Interrupt  */
#define PPC_MSR_LE      (1)             /*  Little-Endian Mode  */

/*  XER bits:  */
#define PPC_XER_SO      (1 << 31)       /*  Summary Overflow  */
#define PPC_XER_OV      (1 << 30)       /*  Overflow  */
#define PPC_XER_CA      (1 << 29)       /*  Carry  */


/*  cpu_ppc.c:  */
struct cpu *ppc_cpu_new(struct memory *mem, struct machine *machine,
        int cpu_id, char *cpu_type_name);
void ppc_cpu_show_full_statistics(struct machine *m);
void ppc_cpu_register_match(struct machine *m, char *name, 
        int writeflag, uint64_t *valuep, int *match_register);
void ppc_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs);
int ppc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,
        int running, uint64_t addr, int bintrans);
int ppc_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr);
int ppc_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr);
int ppc_cpu_run(struct emul *emul, struct machine *machine);
void ppc_cpu_dumpinfo(struct cpu *cpu);
void ppc_cpu_list_available_types(void);
int ppc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
        unsigned char *data, size_t len, int writeflag, int cache_flags);
int ppc_cpu_family_init(struct cpu_family *);


#endif  /*  CPU_PPC_H  */
1	#ifndef CPU_PPC_H
2	#define CPU_PPC_H
3
4	/*
5	* Copyright (C) 2005 Anders Gavare. All rights reserved.
6	*
7	* Redistribution and use in source and binary forms, with or without
8	* modification, are permitted provided that the following conditions are met:
9	*
10	* 1. Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.
12	* 2. Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	* 3. The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.
17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28	* SUCH DAMAGE.
29	*
30	*
31	* $Id: cpu_ppc.h,v 1.22 2005/03/08 22:58:58 debug Exp $
32	*/
33
34	#include "misc.h"
35
36
37	struct cpu_family;
38
39	#define MODE_PPC 0
40	#define MODE_POWER 1
41
42	/* PPC CPU types: */
43	struct ppc_cpu_type_def {
44	char *name;
45	int bits;
46	int flags;
47	int icache_shift;
48	int iway;
49	int dcache_shift;
50	int dway;
51	int l2cache_shift;
52	int l2way;
53	int altivec;
54
55	/* TODO: POWER vs PowerPC? */
56	};
57
58	/* Flags: */
59	#define PPC_NOFP 1
60	/* TODO: Most of these just bogus */
61
62	#define PPC_CPU_TYPE_DEFS { \
63	{ "PPC405GP", 32, PPC_NOFP, 15, 2, 15, 2, 20, 1, 0 }, \
64	{ "PPC603e", 32, 0, 14, 4, 14, 4, 0, 0, 0 }, \
65	{ "MPC7400", 32, 0, 15, 2, 15, 2, 19, 1, 1 }, \
66	{ "PPC750", 32, 0, 15, 2, 15, 2, 20, 1, 0 }, \
67	{ "G4e", 32, 0, 15, 8, 15, 8, 18, 8, 1 }, \
68	{ "PPC970", 64, 0, 16, 1, 15, 2, 19, 1, 1 }, \
69	{ NULL, 0, 0, 0,0, 0,0, 0,0, 0 } \
70	};
71
72	#define PPC_NGPRS 32
73	#define PPC_NFPRS 32
74
75	struct ppc_cpu {
76	struct ppc_cpu_type_def cpu_type;
77
78	int trace_tree_depth;
79
80	uint64_t of_emul_addr;
81	uint64_t pc_last;
82
83	int mode; /* MODE_PPC or MODE_POWER */
84	int bits; /* 32 or 64 */
85
86	uint32_t cr; /* Condition Register */
87	uint32_t fpscr; /* FP Status and Control Register */
88	uint64_t lr; /* Link Register */
89	uint64_t ctr; /* Count Register */
90	uint64_t gpr[PPC_NGPRS]; /* General Purpose Registers */
91	uint64_t xer; /* FP Exception Register */
92	uint64_t fpr[PPC_NFPRS]; /* Floating-Point Registers */
93
94	uint32_t tbl; /* Time Base Lower */
95	uint32_t tbu; /* Time Base Upper */
96	uint32_t dec; /* Decrementer */
97	uint32_t hdec; /* Hypervisor Decrementer */
98	uint64_t ssr0; /* Machine status save/restore
99	register 0 */
100	uint64_t ssr1; /* Machine status save/restore
101	register 1 */
102	uint64_t msr; /* Machine state register */
103	uint64_t sprg0; /* Special Purpose Register G0 */
104	uint64_t sprg1; /* Special Purpose Register G1 */
105	uint64_t sprg2; /* Special Purpose Register G2 */
106	uint64_t sprg3; /* Special Purpose Register G3 */
107	uint32_t pvr; /* Processor Version Register */
108	uint32_t pir; /* Processor ID */
109	};
110
111
112	/* Machine status word bits: (according to Book 3) */
113	#define PPC_MSR_SF (1ULL << 63) /* Sixty-Four-Bit Mode */
114	/* bits 62..61 are reserved */
115	#define PPC_MSR_HV (1ULL << 60) /* Hypervisor */
116	/* bits 59..17 are reserved */
117	#define PPC_MSR_ILE (1 << 16) /* Interrupt Little-Endian Mode */
118	#define PPC_MSR_EE (1 << 15) /* External Interrupt Enable */
119	#define PPC_MSR_PR (1 << 14) /* Problem State */
120	#define PPC_MSR_FP (1 << 13) /* Floating-Point Available */
121	#define PPC_MSR_ME (1 << 12) /* Machine Check Interrupt Enable */
122	#define PPC_MSR_FE0 (1 << 11) /* Floating-Point Exception Mode 0 */
123	#define PPC_MSR_SE (1 << 10) /* Single-Step Trace Enable */
124	#define PPC_MSR_BE (1 << 9) /* Branch Trace Enable */
125	#define PPC_MSR_FE1 (1 << 8) /* Floating-Point Exception Mode 1 */
126	#define PPC_MSR_IR (1 << 5) /* Instruction Relocate */
127	#define PPC_MSR_DR (1 << 4) /* Data Relocate */
128	#define PPC_MSR_PMM (1 << 2) /* Performance Monitor Mark */
129	#define PPC_MSR_RI (1 << 1) /* Recoverable Interrupt */
130	#define PPC_MSR_LE (1) /* Little-Endian Mode */
131
132	/* XER bits: */
133	#define PPC_XER_SO (1 << 31) /* Summary Overflow */
134	#define PPC_XER_OV (1 << 30) /* Overflow */
135	#define PPC_XER_CA (1 << 29) /* Carry */
136
137
138	/* cpu_ppc.c: */
139	struct cpu ppc_cpu_new(struct memory mem, struct machine *machine,
140	int cpu_id, char *cpu_type_name);
141	void ppc_cpu_show_full_statistics(struct machine *m);
142	void ppc_cpu_register_match(struct machine m, char name,
143	int writeflag, uint64_t valuep, int match_register);
144	void ppc_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs);
145	int ppc_cpu_disassemble_instr(struct cpu cpu, unsigned char instr,
146	int running, uint64_t addr, int bintrans);
147	int ppc_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr);
148	int ppc_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr);
149	int ppc_cpu_run(struct emul emul, struct machine machine);
150	void ppc_cpu_dumpinfo(struct cpu *cpu);
151	void ppc_cpu_list_available_types(void);
152	int ppc_memory_rw(struct cpu cpu, struct memory mem, uint64_t vaddr,
153	unsigned char *data, size_t len, int writeflag, int cache_flags);
154	int ppc_cpu_family_init(struct cpu_family *);
155
156
157	#endif /* CPU_PPC_H */