0.3.1/devices/dev_kn01.c

/*
 *  Copyright (C) 2003-2005  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *   
 *
 *  $Id: dev_kn01.c,v 1.6 2005/02/11 09:53:48 debug Exp $
 *  
 *  KN01 stuff ("PMAX", DECstation type 1); CSR (System Control Register)
 *  and VDAC.
 *
 *  TODO: The CSR isn't really complete.
 *
 *  One of the few usable bits in the csr would be KN01_CSR_MONO.
 *  If that bit is set, the framebuffer is treated as a monochrome
 *  one.
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "cpu.h"
#include "devices.h"
#include "memory.h"
#include "misc.h"

#include "dec_kn01.h"


struct kn01_csr_data {
        int             color_fb;
        int             csr;
};


struct vdac_data {
        unsigned char   vdac_reg[DEV_VDAC_LENGTH];

        int             color_fb_flag;

        unsigned char   cur_read_addr;
        unsigned char   cur_write_addr;

        int             sub_color;      /*  subcolor. 0, 1, or 2  */
        unsigned char   cur_rgb[3];

        unsigned char   *rgb_palette;           /*  ptr to 256 * 3 (r,g,b)  */

        unsigned char   cur_read_addr_overlay;
        unsigned char   cur_write_addr_overlay;

        int             sub_color_overlay;      /*  subcolor: 0, 1, or 2  */
        unsigned char   cur_rgb_overlay[3];

        unsigned char   rgb_palette_overlay[16 * 3];    /*  16 * 3 (r,g,b)  */
};


/*
 *  dev_kn01_csr_access():
 */
int dev_kn01_csr_access(struct cpu *cpu, struct memory *mem,
        uint64_t relative_addr, unsigned char *data, size_t len,
        int writeflag, void *extra)
{
        struct kn01_csr_data *k = extra;
        int csr;

        if (writeflag == MEM_WRITE) {
                /*  TODO  */
                return 1;
        }

        /*  Read:  */
        if (len != 2 || relative_addr != 0) {
                fatal("[ kn01_csr: trying to read something which is not "
                    "the first half-word of the csr ]");
        }

        csr = k->csr;

        if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
                data[0] = csr & 0xff;
                data[1] = (csr >> 8) & 0xff;
        } else {
                data[1] = csr & 0xff;
                data[0] = (csr >> 8) & 0xff;
        }

        return 1;
}


/*
 *  dev_vdac_access():
 */
int dev_vdac_access(struct cpu *cpu, struct memory *mem,
        uint64_t relative_addr, unsigned char *data, size_t len,
        int writeflag, void *extra)
{
        struct vdac_data *d = (struct vdac_data *) extra;

        /*  Read from/write to the vdac:  */
        switch (relative_addr) {
        case DEV_VDAC_MAPWA:
                if (writeflag == MEM_WRITE) {
                        d->cur_write_addr = data[0];
                        d->sub_color = 0;
                } else {
                        debug("[ vdac: read from MAPWA ]\n");
                        data[0] = d->vdac_reg[relative_addr];
                }
                break;
        case DEV_VDAC_MAP:
                if (writeflag == MEM_WRITE) {
                        d->cur_rgb[d->sub_color] = data[0];
                        d->sub_color++;

                        if (d->sub_color > 2) {
                                /*  (Only update for color, not mono mode)  */
                                if (d->color_fb_flag)
                                        memcpy(d->rgb_palette +
                                            3*d->cur_write_addr, d->cur_rgb, 3);

                                d->sub_color = 0;
                                d->cur_write_addr ++;
                        }
                } else {
                        if (d->sub_color == 0) {
                                memcpy(d->cur_rgb, d->rgb_palette +
                                    3 * d->cur_read_addr, 3);
                        }
                        data[0] = d->cur_rgb[d->sub_color];
                        d->sub_color++;
                        if (d->sub_color > 2) {
                                d->sub_color = 0;
                                d->cur_read_addr ++;
                        }
                }
                break;
        case DEV_VDAC_MAPRA:
                if (writeflag == MEM_WRITE) {
                        d->cur_read_addr = data[0];
                        d->sub_color = 0;
                } else {
                        debug("[ vdac: read from MAPRA ]\n");
                        data[0] = d->vdac_reg[relative_addr];
                }
                break;
        case DEV_VDAC_OVERWA:
                if (writeflag == MEM_WRITE) {
                        d->cur_write_addr_overlay = data[0];
                        d->sub_color_overlay = 0;
                } else {
                        debug("[ vdac: read from OVERWA ]\n");
                        data[0] = d->vdac_reg[relative_addr];
                }
                break;
        case DEV_VDAC_OVER:
                if (writeflag == MEM_WRITE) {
                        d->cur_rgb_overlay[d->sub_color_overlay] = data[0];
                        d->sub_color_overlay++;

                        if (d->sub_color_overlay > 2) {
                                /*  (Only update for color, not mono mode)  */
                                if (d->color_fb_flag)
                                        memcpy(d->rgb_palette_overlay +
                                            3 * d->cur_write_addr_overlay,
                                            d->cur_rgb_overlay, 3);

                                d->sub_color_overlay = 0;
                                d->cur_write_addr_overlay ++;
                                if (d->cur_write_addr_overlay > 15)
                                        d->cur_write_addr_overlay = 0;
                        }
                } else {
                        if (d->sub_color_overlay == 0) {
                                memcpy(d->cur_rgb_overlay,
                                    d->rgb_palette_overlay +
                                    3 * d->cur_read_addr_overlay, 3);
                        }
                        data[0] = d->cur_rgb_overlay[d->sub_color_overlay];
                        d->sub_color_overlay++;
                        if (d->sub_color_overlay > 2) {
                                d->sub_color_overlay = 0;
                                d->cur_read_addr_overlay ++;
                                if (d->cur_read_addr_overlay > 15)
                                        d->cur_read_addr_overlay = 0;
                        }
                }
                break;
        case DEV_VDAC_OVERRA:
                if (writeflag == MEM_WRITE) {
                        d->cur_read_addr_overlay = data[0];
                        d->sub_color_overlay = 0;
                } else {
                        debug("[ vdac: read from OVERRA ]\n");
                        data[0] = d->vdac_reg[relative_addr];
                }
                break;
        default:
                if (writeflag == MEM_WRITE) {
                        debug("[ vdac: unimplemented write to address 0x%x,"
                            " data=0x%02x ]\n", (int)relative_addr, data[0]);
                        d->vdac_reg[relative_addr] = data[0];
                } else {
                        debug("[ vdac: unimplemented read from address 0x%x"
                            " ]\n", (int)relative_addr);
                        data[0] = d->vdac_reg[relative_addr];
                }
        }

        /*  Pretend it was ok:  */
        return 1;
}


/*
 *  dev_vdac_init():
 */
void dev_vdac_init(struct memory *mem, uint64_t baseaddr,
        unsigned char *rgb_palette, int color_fb_flag)
{
        struct vdac_data *d = malloc(sizeof(struct vdac_data));
        if (d == NULL) {
                fprintf(stderr, "out of memory\n");
                exit(1);
        }
        memset(d, 0, sizeof(struct vdac_data));
        d->rgb_palette   = rgb_palette;
        d->color_fb_flag = color_fb_flag;

        memory_device_register(mem, "vdac", baseaddr, DEV_VDAC_LENGTH,
            dev_vdac_access, (void *)d, MEM_DEFAULT, NULL);
}


/*
 *  dev_kn01_csr_init():
 */
void dev_kn01_csr_init(struct memory *mem, uint64_t baseaddr, int color_fb)
{
        struct kn01_csr_data *k = malloc(sizeof(struct kn01_csr_data));
        if (k == NULL) {
                fprintf(stderr, "out of memory\n");
                exit(1);
        }

        memset(k, 0, sizeof(struct kn01_csr_data));
        k->color_fb = color_fb;

        k->csr = 0;
        k->csr |= (color_fb? 0 : KN01_CSR_MONO);

        memory_device_register(mem, "kn01_csr", baseaddr,
            DEV_KN01_CSR_LENGTH, dev_kn01_csr_access, k, MEM_DEFAULT, NULL);
}

1	dpavlin	2	/*
2			* Copyright (C) 2003-2005 Anders Gavare. All rights reserved.
3			*
4			* Redistribution and use in source and binary forms, with or without
5			* modification, are permitted provided that the following conditions are met:
6			*
7			* 1. Redistributions of source code must retain the above copyright
8			* notice, this list of conditions and the following disclaimer.
9			* 2. Redistributions in binary form must reproduce the above copyright
10			* notice, this list of conditions and the following disclaimer in the
11			* documentation and/or other materials provided with the distribution.
12			* 3. The name of the author may not be used to endorse or promote products
13			* derived from this software without specific prior written permission.
14			*
15			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25			* SUCH DAMAGE.
26			*
27			*
28			* $Id: dev_kn01.c,v 1.6 2005/02/11 09:53:48 debug Exp $
29			*
30			* KN01 stuff ("PMAX", DECstation type 1); CSR (System Control Register)
31			* and VDAC.
32			*
33			* TODO: The CSR isn't really complete.
34			*
35			* One of the few usable bits in the csr would be KN01_CSR_MONO.
36			* If that bit is set, the framebuffer is treated as a monochrome
37			* one.
38			*/
39
40			#include <stdio.h>
41			#include <stdlib.h>
42			#include <string.h>
43
44			#include "cpu.h"
45			#include "devices.h"
46			#include "memory.h"
47			#include "misc.h"
48
49			#include "dec_kn01.h"
50
51
52			struct kn01_csr_data {
53			int color_fb;
54			int csr;
55			};
56
57
58			struct vdac_data {
59			unsigned char vdac_reg[DEV_VDAC_LENGTH];
60
61			int color_fb_flag;
62
63			unsigned char cur_read_addr;
64			unsigned char cur_write_addr;
65
66			int sub_color; /* subcolor. 0, 1, or 2 */
67			unsigned char cur_rgb[3];
68
69			unsigned char rgb_palette; / ptr to 256 * 3 (r,g,b) */
70
71			unsigned char cur_read_addr_overlay;
72			unsigned char cur_write_addr_overlay;
73
74			int sub_color_overlay; /* subcolor: 0, 1, or 2 */
75			unsigned char cur_rgb_overlay[3];
76
77			unsigned char rgb_palette_overlay[16 * 3]; /* 16 * 3 (r,g,b) */
78			};
79
80
81			/*
82			* dev_kn01_csr_access():
83			*/
84			int dev_kn01_csr_access(struct cpu cpu, struct memory mem,
85			uint64_t relative_addr, unsigned char *data, size_t len,
86			int writeflag, void *extra)
87			{
88			struct kn01_csr_data *k = extra;
89			int csr;
90
91			if (writeflag == MEM_WRITE) {
92			/* TODO */
93			return 1;
94			}
95
96			/* Read: */
97			if (len != 2 \|\| relative_addr != 0) {
98			fatal("[ kn01_csr: trying to read something which is not "
99			"the first half-word of the csr ]");
100			}
101
102			csr = k->csr;
103
104			if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
105			data[0] = csr & 0xff;
106			data[1] = (csr >> 8) & 0xff;
107			} else {
108			data[1] = csr & 0xff;
109			data[0] = (csr >> 8) & 0xff;
110			}
111
112			return 1;
113			}
114
115
116			/*
117			* dev_vdac_access():
118			*/
119			int dev_vdac_access(struct cpu cpu, struct memory mem,
120			uint64_t relative_addr, unsigned char *data, size_t len,
121			int writeflag, void *extra)
122			{
123			struct vdac_data d = (struct vdac_data ) extra;
124
125			/* Read from/write to the vdac: */
126			switch (relative_addr) {
127			case DEV_VDAC_MAPWA:
128			if (writeflag == MEM_WRITE) {
129			d->cur_write_addr = data[0];
130			d->sub_color = 0;
131			} else {
132			debug("[ vdac: read from MAPWA ]\n");
133			data[0] = d->vdac_reg[relative_addr];
134			}
135			break;
136			case DEV_VDAC_MAP:
137			if (writeflag == MEM_WRITE) {
138			d->cur_rgb[d->sub_color] = data[0];
139			d->sub_color++;
140
141			if (d->sub_color > 2) {
142			/* (Only update for color, not mono mode) */
143			if (d->color_fb_flag)
144			memcpy(d->rgb_palette +
145			3*d->cur_write_addr, d->cur_rgb, 3);
146
147			d->sub_color = 0;
148			d->cur_write_addr ++;
149			}
150			} else {
151			if (d->sub_color == 0) {
152			memcpy(d->cur_rgb, d->rgb_palette +
153			3 * d->cur_read_addr, 3);
154			}
155			data[0] = d->cur_rgb[d->sub_color];
156			d->sub_color++;
157			if (d->sub_color > 2) {
158			d->sub_color = 0;
159			d->cur_read_addr ++;
160			}
161			}
162			break;
163			case DEV_VDAC_MAPRA:
164			if (writeflag == MEM_WRITE) {
165			d->cur_read_addr = data[0];
166			d->sub_color = 0;
167			} else {
168			debug("[ vdac: read from MAPRA ]\n");
169			data[0] = d->vdac_reg[relative_addr];
170			}
171			break;
172			case DEV_VDAC_OVERWA:
173			if (writeflag == MEM_WRITE) {
174			d->cur_write_addr_overlay = data[0];
175			d->sub_color_overlay = 0;
176			} else {
177			debug("[ vdac: read from OVERWA ]\n");
178			data[0] = d->vdac_reg[relative_addr];
179			}
180			break;
181			case DEV_VDAC_OVER:
182			if (writeflag == MEM_WRITE) {
183			d->cur_rgb_overlay[d->sub_color_overlay] = data[0];
184			d->sub_color_overlay++;
185
186			if (d->sub_color_overlay > 2) {
187			/* (Only update for color, not mono mode) */
188			if (d->color_fb_flag)
189			memcpy(d->rgb_palette_overlay +
190			3 * d->cur_write_addr_overlay,
191			d->cur_rgb_overlay, 3);
192
193			d->sub_color_overlay = 0;
194			d->cur_write_addr_overlay ++;
195			if (d->cur_write_addr_overlay > 15)
196			d->cur_write_addr_overlay = 0;
197			}
198			} else {
199			if (d->sub_color_overlay == 0) {
200			memcpy(d->cur_rgb_overlay,
201			d->rgb_palette_overlay +
202			3 * d->cur_read_addr_overlay, 3);
203			}
204			data[0] = d->cur_rgb_overlay[d->sub_color_overlay];
205			d->sub_color_overlay++;
206			if (d->sub_color_overlay > 2) {
207			d->sub_color_overlay = 0;
208			d->cur_read_addr_overlay ++;
209			if (d->cur_read_addr_overlay > 15)
210			d->cur_read_addr_overlay = 0;
211			}
212			}
213			break;
214			case DEV_VDAC_OVERRA:
215			if (writeflag == MEM_WRITE) {
216			d->cur_read_addr_overlay = data[0];
217			d->sub_color_overlay = 0;
218			} else {
219			debug("[ vdac: read from OVERRA ]\n");
220			data[0] = d->vdac_reg[relative_addr];
221			}
222			break;
223			default:
224			if (writeflag == MEM_WRITE) {
225			debug("[ vdac: unimplemented write to address 0x%x,"
226			" data=0x%02x ]\n", (int)relative_addr, data[0]);
227			d->vdac_reg[relative_addr] = data[0];
228			} else {
229			debug("[ vdac: unimplemented read from address 0x%x"
230			" ]\n", (int)relative_addr);
231			data[0] = d->vdac_reg[relative_addr];
232			}
233			}
234
235			/* Pretend it was ok: */
236			return 1;
237			}
238
239
240			/*
241			* dev_vdac_init():
242			*/
243			void dev_vdac_init(struct memory *mem, uint64_t baseaddr,
244			unsigned char *rgb_palette, int color_fb_flag)
245			{
246			struct vdac_data *d = malloc(sizeof(struct vdac_data));
247			if (d == NULL) {
248			fprintf(stderr, "out of memory\n");
249			exit(1);
250			}
251			memset(d, 0, sizeof(struct vdac_data));
252			d->rgb_palette = rgb_palette;
253			d->color_fb_flag = color_fb_flag;
254
255			memory_device_register(mem, "vdac", baseaddr, DEV_VDAC_LENGTH,
256			dev_vdac_access, (void *)d, MEM_DEFAULT, NULL);
257			}
258
259
260			/*
261			* dev_kn01_csr_init():
262			*/
263			void dev_kn01_csr_init(struct memory *mem, uint64_t baseaddr, int color_fb)
264			{
265			struct kn01_csr_data *k = malloc(sizeof(struct kn01_csr_data));
266			if (k == NULL) {
267			fprintf(stderr, "out of memory\n");
268			exit(1);
269			}
270
271			memset(k, 0, sizeof(struct kn01_csr_data));
272			k->color_fb = color_fb;
273
274			k->csr = 0;
275			k->csr \|= (color_fb? 0 : KN01_CSR_MONO);
276
277			memory_device_register(mem, "kn01_csr", baseaddr,
278			DEV_KN01_CSR_LENGTH, dev_kn01_csr_access, k, MEM_DEFAULT, NULL);
279			}
280