/[gxemul]/trunk/src/tools/generate_alpha_misc.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Contents of /trunk/src/tools/generate_alpha_misc.c

Parent Directory Parent Directory | Revision Log Revision Log


Revision 12 - (show annotations)
Mon Oct 8 16:18:38 2007 UTC (13 years, 1 month ago) by dpavlin
File MIME type: text/plain
File size: 11405 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.905 2005/08/16 09:16:24 debug Exp $
20050628	Continuing the work on the ARM translation engine. end_of_page
		works. Experimenting with load/store translation caches
		(virtual -> physical -> host).
20050629	More ARM stuff (memory access translation cache, mostly). This
		might break a lot of stuff elsewhere, probably some MIPS-
		related translation things.
20050630	Many load/stores are now automatically generated and included
		into cpu_arm_instr.c; 1024 functions in total (!).
		Fixes based on feedback from Alec Voropay: only print 8 hex
		digits instead of 16 in some cases when emulating 32-bit
		machines; similar 8 vs 16 digit fix for breakpoint addresses;
		4Kc has 16 TLB entries, not 48; the MIPS config select1
		register is now printed with "reg ,0".
		Also changing many other occurances of 16 vs 8 digit output.
		Adding cache associativity fields to mips_cpu_types.h; updating
		some other cache fields; making the output of
		mips_cpu_dumpinfo() look nicer.
		Generalizing the bintrans stuff for device accesses to also
		work with the new translation system. (This might also break
		some MIPS things.)
		Adding multi-load/store instructions to the ARM disassembler
		and the translator, and some optimizations of various kinds.
20050701	Adding a simple dev_disk (it can read/write sectors from
		disk images).
20050712	Adding dev_ether (a simple ethernet send/receive device).
		Debugger command "ninstrs" for toggling show_nr_of_instructions
		during runtime.
		Removing the framebuffer logo.
20050713	Continuing on dev_ether.
		Adding a dummy cpu_alpha (again).
20050714	More work on cpu_alpha.
20050715	More work on cpu_alpha. Many instructions work, enough to run
		a simple framebuffer fill test (similar to the ARM test).
20050716	More Alpha stuff.
20050717	Minor updates (Alpha stuff).
20050718	Minor updates (Alpha stuff).
20050719	Generalizing some Alpha instructions.
20050720	More Alpha-related updates.
20050721	Continuing on cpu_alpha. Importing rpb.h from NetBSD/alpha.
20050722	Alpha-related updates: userland stuff (Hello World using
		write() compiled statically for FreeBSD/Alpha runs fine), and
		more instructions are now implemented.
20050723	Fixing ldq_u and stq_u.
		Adding more instructions (conditional moves, masks, extracts,
		shifts).
20050724	More FreeBSD/Alpha userland stuff, and adding some more
		instructions (inserts).
20050725	Continuing on the Alpha stuff. (Adding dummy ldt/stt.)
		Adding a -A command line option to turn off alignment checks
		in some cases (for translated code).
		Trying to remove the old bintrans code which updated the pc
		and nr_of_executed_instructions for every instruction.
20050726	Making another attempt att removing the pc/nr of instructions
		code. This time it worked, huge performance increase for
		artificial test code, but performance loss for real-world
		code :-( so I'm scrapping that code for now.
		Tiny performance increase on Alpha (by using ret instead of
		jmp, to play nice with the Alpha's branch prediction) for the
		old MIPS bintrans backend.
20050727	Various minor fixes and cleanups.
20050728	Switching from a 2-level virtual to host/physical translation
		system for ARM emulation, to a 1-level translation.
		Trying to switch from 2-level to 1-level for the MIPS bintrans
		system as well (Alpha only, so far), but there is at least one
		problem: caches and/or how they work with device mappings.
20050730	Doing the 2-level to 1-level conversion for the i386 backend.
		The cache/device bug is still there for R2K/3K :(
		Various other minor updates (Malta etc).
		The mc146818 clock now updates the UIP bit in a way which works
		better with Linux for at least sgimips and Malta emulation.
		Beginning the work on refactoring the dyntrans system.
20050731	Continuing the dyntrans refactoring.
		Fixing a small but serious host alignment bug in memory_rw.
		Adding support for big-endian load/stores to the i386 bintrans
		backend.
		Another minor i386 bintrans backend update: stores from the
		zero register are now one (or two) loads shorter.
		The slt and sltu instructions were incorrectly implemented for
		the i386 backend; only using them for 32-bit mode for now.
20050801	Continuing the dyntrans refactoring.
		Cleanup of the ns16550 serial controller (removing unnecessary
		code).
		Bugfix (memory corruption bug) in dev_gt, and a patch/hack from
		Alec Voropay for Linux/Malta.
20050802	More cleanup/refactoring of the dyntrans subsystem: adding
		phys_page pointers to the lookup tables, for quick jumps
		between translated pages.
		Better fix for the ns16550 device (but still no real FIFO
		functionality).
		Converting cpu_ppc to the new dyntrans system. This means that
		I will have to start from scratch with implementing each
		instruction, and figure out how to implement dual 64/32-bit
		modes etc.
		Removing the URISC CPU family, because it was useless.
20050803	When selecting a machine type, the main type can now be omitted
		if the subtype name is unique. (I.e. -E can be omitted.)
		Fixing a dyntrans/device update bug. (Writes to offset 0 of
		a device could sometimes go unnoticed.)
		Adding an experimental "instruction combination" hack for
		ARM for memset-like byte fill loops.
20050804	Minor progress on cpu_alpha and related things.
		Finally fixing the MIPS dmult/dmultu bugs.
		Fixing some minor TODOs.
20050805	Generalizing the 8259 PIC. It now also works with Cobalt
		and evbmips emulation, in addition to the x86 hack.
		Finally converting the ns16550 device to use devinit.
		Continuing the work on the dyntrans system. Thinking about
		how to add breakpoints.
20050806	More dyntrans updates. Breakpoints seem to work now.
20050807	Minor updates: cpu_alpha and related things; removing
		dev_malta (as it isn't used any more).
		Dyntrans: working on general "show trace tree" support.
		The trace tree stuff now works with both the old MIPS code and
		with newer dyntrans modes. :)
		Continuing on Alpha-related stuff (trying to get *BSD to boot
		a bit further, adding more instructions, etc).
20050808	Adding a dummy IA64 cpu family, and continuing the refactoring
		of the dyntrans system.
		Removing the regression test stuff, because it was more or
		less useless.
		Adding loadlinked/storeconditional type instructions to the
		Alpha emulation. (Needed for Linux/alpha. Not very well tested
		yet.)
20050809	The function call trace tree now prints a per-function nr of
		arguments. (Semi-meaningless, since that data isn't read yet
		from the ELFs; some hardcoded symbols such as memcpy() and
		strlen() work fine, though.)
		More dyntrans refactoring; taking out more of the things that
		are common to all cpu families.
20050810	Working on adding support for "dual mode" for PPC dyntrans
		(i.e. both 64-bit and 32-bit modes).
		(Re)adding some simple PPC instructions.
20050811	Adding a dummy M68K cpu family. The dyntrans system isn't ready
		for variable-length ISAs yet, so it's completely bogus so far.
		Re-adding more PPC instructions.
		Adding a hack to src/file.c which allows OpenBSD/mac68k a.out
		kernels to be loaded.
		Beginning to add PPC loads/stores. So far they only work in
		32-bit mode.
20050812	The configure file option "add_remote" now accepts symbolic
		host names, in addition to numeric IPv4 addresses.
		Re-adding more PPC instructions.
20050814	Continuing to port back more PPC instructions.
		Found and fixed the cache/device write-update bug for 32-bit
		MIPS bintrans. :-)
		Triggered a really weird and annoying bug in Compaq's C
		compiler; ccc sometimes outputs code which loads from an
		address _before_ checking whether the pointer was NULL or not.
		(I'm not sure how to handle this problem.)
20050815	Removing all of the old x86 instruction execution code; adding
		a new (dummy) dyntrans module for x86.
		Taking the first steps to extend the dyntrans system to support
		variable-length instructions.
		Slowly preparing for the next release.
20050816	Adding a dummy SPARC cpu module.
		Minor updates (documentation etc) for the release.

==============  RELEASE 0.3.5  ==============


1 /*
2 * Copyright (C) 2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: generate_alpha_misc.c,v 1.14 2005/08/08 20:19:45 debug Exp $
29 */
30
31 #include <stdio.h>
32 #include <string.h>
33
34
35 char *sizechar[4] = { "b", "w", "l", "q" };
36
37 #define N_CMPS 5
38 char *cmps[N_CMPS] = { "ult", "eq", "ule", "lt", "le" /*bge*/ };
39 #define N_CMOV 8
40 char *cmov[N_CMOV] = { "lbs", "lbc", "eq", "ne", "lt", "ge", "le", "gt" };
41
42
43 int main(int argc, char *argv[])
44 {
45 int load, size, zero, aligncheck, n, msk, llsc;
46 int ra, rc, lo, scale, imm, not, op, quad;
47
48 printf("\n/* AUTOMATICALLY GENERATED! Do not edit. */\n\n");
49
50 n = 0;
51 /* add and sub: */
52 for (imm = 0; imm <= 1; imm ++)
53 for (quad = 0; quad <= 1; quad ++)
54 for (scale = 0; scale <= 8; scale += 4)
55 for (op = 0; op <= 1; op ++) {
56 printf("#define ALU_N alpha_instr_");
57 if (scale)
58 printf("s%i", scale);
59 printf("%s%s", op? "sub" : "add", quad? "q" : "l");
60 if (imm)
61 printf("_imm");
62 printf("\n");
63
64 if (imm)
65 printf("#define ALU_IMM\n");
66 if (!quad)
67 printf("#define ALU_LONG\n");
68 if (op)
69 printf("#define ALU_SUB\n");
70 else
71 printf("#define ALU_ADD\n");
72 if (scale)
73 printf("#define ALU_S%i\n", scale);
74
75 printf("#include \"cpu_alpha_instr_alu.c\"\n");
76
77 if (imm)
78 printf("#undef ALU_IMM\n");
79 if (!quad)
80 printf("#undef ALU_LONG\n");
81 if (op)
82 printf("#undef ALU_SUB\n");
83 else
84 printf("#undef ALU_ADD\n");
85 if (scale)
86 printf("#undef ALU_S%i\n", scale);
87
88 printf("#undef ALU_N\n");
89 }
90
91 /* and, or, xor, zap, sll, srl, sra: */
92 for (imm = 0; imm <= 1; imm ++)
93 for (not = 0; not <= 1; not ++)
94 for (op = 0; op < 7; op ++) {
95 if (op >= 4 && not)
96 continue;
97 printf("#define ALU_N alpha_instr_");
98 switch (op) {
99 case 0: printf("and"); break;
100 case 1: printf("or"); break;
101 case 2: printf("xor"); break;
102 case 3: printf("zap"); break;
103 case 4: printf("sll"); break;
104 case 5: printf("srl"); break;
105 case 6: printf("sra"); break;
106 }
107 if (not)
108 printf("not");
109 if (imm)
110 printf("_imm");
111 printf("\n");
112 if (imm)
113 printf("#define ALU_IMM\n");
114 switch (op) {
115 case 0: printf("#define ALU_AND\n"); break;
116 case 1: printf("#define ALU_OR\n"); break;
117 case 2: printf("#define ALU_XOR\n"); break;
118 case 3: printf("#define ALU_ZAP\n"); break;
119 case 4: printf("#define ALU_SLL\n"); break;
120 case 5: printf("#define ALU_SRL\n"); break;
121 case 6: printf("#define ALU_SRA\n"); break;
122 }
123 if (not)
124 printf("#define ALU_NOT\n");
125 printf("#include \"cpu_alpha_instr_alu.c\"\n");
126
127 if (imm)
128 printf("#undef ALU_IMM\n");
129 if (not)
130 printf("#undef ALU_NOT\n");
131 switch (op) {
132 case 0: printf("#undef ALU_AND\n"); break;
133 case 1: printf("#undef ALU_OR\n"); break;
134 case 2: printf("#undef ALU_XOR\n"); break;
135 case 3: printf("#undef ALU_ZAP\n"); break;
136 case 4: printf("#undef ALU_SLL\n"); break;
137 case 5: printf("#undef ALU_SRL\n"); break;
138 case 6: printf("#undef ALU_SRA\n"); break;
139 }
140
141 printf("#undef ALU_N\n");
142 }
143
144 printf("#define ALU_CMP\n");
145 for (imm = 0; imm <= 1; imm ++)
146 for (op = 0; op < N_CMPS; op ++) {
147 printf("#define ALU_N alpha_instr_cmp%s", cmps[op]);
148 if (imm)
149 printf("_imm");
150 printf("\n");
151
152 if (imm)
153 printf("#define ALU_IMM\n");
154
155 if (cmps[op][0] == 'u')
156 printf("#define ALU_UNSIGNED\n");
157 if (strcmp(cmps[op]+strlen(cmps[op])-2,"lt") == 0)
158 printf("#define ALU_CMP_LT\n");
159 if (strcmp(cmps[op]+strlen(cmps[op])-2,"le") == 0)
160 printf("#define ALU_CMP_LE\n");
161 if (strcmp(cmps[op]+strlen(cmps[op])-2,"eq") == 0)
162 printf("#define ALU_CMP_EQ\n");
163
164 printf("#include \"cpu_alpha_instr_alu.c\"\n");
165
166 if (cmps[op][0] == 'u')
167 printf("#undef ALU_UNSIGNED\n");
168 if (strcmp(cmps[op]+strlen(cmps[op])-2,"lt") == 0)
169 printf("#undef ALU_CMP_LT\n");
170 if (strcmp(cmps[op]+strlen(cmps[op])-2,"le") == 0)
171 printf("#undef ALU_CMP_LE\n");
172 if (strcmp(cmps[op]+strlen(cmps[op])-2,"eq") == 0)
173 printf("#undef ALU_CMP_EQ\n");
174 if (imm)
175 printf("#undef ALU_IMM\n");
176 printf("#undef ALU_N\n");
177 }
178 printf("#undef ALU_CMP\n");
179
180 printf("#define ALU_CMOV\n");
181 for (imm = 0; imm <= 1; imm ++)
182 for (op = 0; op < N_CMOV; op ++) {
183 printf("#define ALU_N alpha_instr_cmov%s", cmov[op]);
184 if (imm)
185 printf("_imm");
186 printf("\n");
187 if (imm)
188 printf("#define ALU_IMM\n");
189 printf("#define ALU_CMOV_%s\n", cmov[op]);
190 printf("#include \"cpu_alpha_instr_alu.c\"\n");
191 printf("#undef ALU_CMOV_%s\n", cmov[op]);
192 if (imm)
193 printf("#undef ALU_IMM\n");
194 printf("#undef ALU_N\n");
195 }
196 printf("#undef ALU_CMOV\n");
197
198 for (imm = 0; imm <= 1; imm ++)
199 for (lo = 0; lo <= 1; lo ++)
200 for (msk = 0; msk <= 2; msk ++)
201 for (size=0; size<4; size++) {
202 if (size==0 && lo==0)
203 continue;
204 switch (msk) {
205 case 0: printf("#define ALU_MSK\n"); break;
206 case 1: printf("#define ALU_EXT\n"); break;
207 case 2: printf("#define ALU_INS\n"); break;
208 }
209 switch (msk) {
210 case 0: printf("#define ALU_N alpha_instr_msk"); break;
211 case 1: printf("#define ALU_N alpha_instr_ext"); break;
212 case 2: printf("#define ALU_N alpha_instr_ins"); break;
213 }
214 printf("%s", sizechar[size]);
215 if (lo)
216 printf("l");
217 else
218 printf("h");
219 if (imm)
220 printf("_imm");
221 printf("\n");
222 if (imm)
223 printf("#define ALU_IMM\n");
224 switch (size) {
225 case 0: printf("#define ALU_B\n"); break;
226 case 1: printf("#define ALU_W\n"); break;
227 case 2: printf("#define ALU_L\n"); break;
228 case 3: printf("#define ALU_Q\n"); break;
229 }
230 if (lo)
231 printf("#define ALU_LO\n");
232 printf("#include \"cpu_alpha_instr_alu.c\"\n");
233 switch (size) {
234 case 0: printf("#undef ALU_B\n"); break;
235 case 1: printf("#undef ALU_W\n"); break;
236 case 2: printf("#undef ALU_L\n"); break;
237 case 3: printf("#undef ALU_Q\n"); break;
238 }
239 switch (msk) {
240 case 0: printf("#undef ALU_MSK\n"); break;
241 case 1: printf("#undef ALU_EXT\n"); break;
242 case 2: printf("#undef ALU_INS\n"); break;
243 }
244 if (lo)
245 printf("#undef ALU_LO\n");
246 if (imm)
247 printf("#undef ALU_IMM\n");
248 printf("#undef ALU_N\n");
249 }
250
251 /*
252 * Normal load/store:
253 */
254 for (llsc=0; llsc<=1; llsc++)
255 for (aligncheck=0; aligncheck<=1; aligncheck++)
256 for (load=0; load<=1; load++)
257 for (zero=0; zero<=1; zero++)
258 for (size=0; size<4; size++) {
259 if (llsc && size < 2)
260 continue;
261 if (aligncheck)
262 printf("#define LS_ALIGN_CHECK\n");
263 if (zero)
264 printf("#define LS_IGNORE_OFFSET\n");
265 if (load)
266 printf("#define LS_LOAD\n");
267 if (llsc)
268 printf("#define LS_LLSC\n");
269 switch (size) {
270 case 0: printf("#define LS_B\n"); break;
271 case 1: printf("#define LS_W\n"); break;
272 case 2: printf("#define LS_L\n"); break;
273 case 3: printf("#define LS_Q\n"); break;
274 }
275 printf("#define LS_GENERIC_N alpha_generic_");
276 if (load)
277 printf("ld");
278 else
279 printf("st");
280 printf("%s", sizechar[size]);
281 if (llsc)
282 printf("_llsc");
283 printf("\n");
284 printf("#define LS_N alpha_instr_");
285 if (load)
286 printf("ld");
287 else
288 printf("st");
289 printf("%s", sizechar[size]);
290 if (zero)
291 printf("_0");
292 if (aligncheck)
293 printf("_aligncheck");
294 if (llsc)
295 printf("_llsc");
296 printf("\n");
297 printf("#include \"cpu_alpha_instr_loadstore.c\"\n");
298 printf("#undef LS_N\n");
299 printf("#undef LS_GENERIC_N\n");
300 switch (size) {
301 case 0: printf("#undef LS_B\n"); break;
302 case 1: printf("#undef LS_W\n"); break;
303 case 2: printf("#undef LS_L\n"); break;
304 case 3: printf("#undef LS_Q\n"); break;
305 }
306 if (load)
307 printf("#undef LS_LOAD\n");
308 if (llsc)
309 printf("#undef LS_LLSC\n");
310 if (zero)
311 printf("#undef LS_IGNORE_OFFSET\n");
312 if (aligncheck)
313 printf("#undef LS_ALIGN_CHECK\n");
314 }
315
316 /*
317 * Unaligned load/store:
318 */
319 printf("#define LS_UNALIGNED\n");
320 for (load=0; load<=1; load++) {
321 size = 3;
322 if (load)
323 printf("#define LS_LOAD\n");
324 printf("#define LS_Q\n");
325 printf("#define LS_GENERIC_N alpha_generic_");
326 if (load)
327 printf("ld");
328 else
329 printf("st");
330 printf("%s", sizechar[size]);
331 printf("_u"); /* NOTE: unaligned */
332 printf("\n");
333 printf("#define LS_N alpha_instr_");
334 if (load)
335 printf("ld");
336 else
337 printf("st");
338 printf("%s", sizechar[size]);
339 printf("_u"); /* NOTE: unaligned */
340 printf("\n");
341 printf("#include \"cpu_alpha_instr_loadstore.c\"\n");
342 printf("#undef LS_N\n");
343 printf("#undef LS_GENERIC_N\n");
344 printf("#undef LS_Q\n");
345 if (load)
346 printf("#undef LS_LOAD\n");
347 }
348 printf("#undef LS_UNALIGNED\n");
349
350 /* Lookup table for most normal loads/stores: */
351 printf("\n\nvoid (*alpha_loadstore[64])(struct cpu *, struct "
352 "alpha_instr_call *) = {\n");
353
354 for (llsc = 0; llsc <= 1; llsc ++)
355 for (aligncheck=0; aligncheck<=1; aligncheck++)
356 for (load=0; load<=1; load++)
357 for (zero=0; zero<=1; zero++)
358 for (size=0; size<4; size++) {
359 printf("\talpha_instr_");
360 if (llsc && (size != 2 && size != 3)) {
361 printf("nop");
362 } else {
363 if (load)
364 printf("ld");
365 else
366 printf("st");
367 printf("%s", sizechar[size]);
368 if (zero)
369 printf("_0");
370 if (aligncheck)
371 printf("_aligncheck");
372 if (llsc)
373 printf("_llsc");
374 }
375 if (++n < 64)
376 printf(",");
377 printf("\n");
378 }
379
380 printf("};\n\n");
381
382 for (ra = 0; ra < 32; ra ++)
383 for (rc = 0; rc < 31; rc ++)
384 if (ra != rc) {
385 printf("static void alpha_instr_mov_%i_%i(struct cpu"
386 " *cpu, struct alpha_instr_call *ic)\n", ra, rc);
387 printf("{ cpu->cd.alpha.r[%i] = ", rc);
388 if (ra == 31)
389 printf("0");
390 else
391 printf("cpu->cd.alpha.r[%i]", ra);
392 printf("; }\n");
393 }
394
395 printf("\n\nvoid (*alpha_mov_r_r[32*31])(struct cpu *, struct "
396 "alpha_instr_call *) = {\n");
397 n = 0;
398 for (rc = 0; rc < 31; rc ++)
399 for (ra = 0; ra < 32; ra ++) {
400 if (ra == rc)
401 printf("\talpha_instr_nop");
402 else
403 printf("\talpha_instr_mov_%i_%i", ra, rc);
404 if (++n < 31*32)
405 printf(",");
406 printf("\n");
407 }
408
409 printf("};\n\n");
410
411 return 0;
412 }
413

  ViewVC Help
Powered by ViewVC 1.1.26