trunk/src/memory_rw.c

/*
 *  Copyright (C) 2003-2007  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright
 *     notice, this list of conditions and the following disclaimer in the
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: memory_rw.c,v 1.102 2007/04/16 15:13:44 debug Exp $
 *
 *  Generic memory_rw(), with special hacks for specific CPU families.
 *
 *  Example for inclusion from memory_mips.c:
 *
 *      MEMORY_RW should be mips_memory_rw
 *      MEM_MIPS should be defined
 */


/*
 *  memory_rw():
 *
 *  Read or write data from/to memory.
 *
 *      cpu             the cpu doing the read/write
 *      mem             the memory object to use
 *      vaddr           the virtual address
 *      data            a pointer to the data to be written to memory, or
 *                      a placeholder for data when reading from memory
 *      len             the length of the 'data' buffer
 *      writeflag       set to MEM_READ or MEM_WRITE
 *      misc_flags      CACHE_{NONE,DATA,INSTRUCTION} | other flags
 *
 *  If the address indicates access to a memory mapped device, that device'
 *  read/write access function is called.
 *
 *  This function should not be called with cpu == NULL.
 *
 *  Returns one of the following:
 *      MEMORY_ACCESS_FAILED
 *      MEMORY_ACCESS_OK
 *
 *  (MEMORY_ACCESS_FAILED is 0.)
 */
int MEMORY_RW(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
        unsigned char *data, size_t len, int writeflag, int misc_flags)
{
#ifdef MEM_ALPHA
        const int offset_mask = 0x1fff;
#else
        const int offset_mask = 0xfff;
#endif

#ifndef MEM_USERLAND
        int ok = 1;
#endif
        uint64_t paddr;
        int cache, no_exceptions, offset;
        unsigned char *memblock;
        int dyntrans_device_danger = 0;

        no_exceptions = misc_flags & NO_EXCEPTIONS;
        cache = misc_flags & CACHE_FLAGS_MASK;


#ifdef MEM_USERLAND
#ifdef MEM_ALPHA
        paddr = vaddr;
#else
        paddr = vaddr & 0x7fffffff;
#endif
#else   /*  !MEM_USERLAND  */
        if (misc_flags & PHYSICAL || cpu->translate_v2p == NULL) {
                paddr = vaddr;
        } else {
                ok = cpu->translate_v2p(cpu, vaddr, &paddr,
                    (writeflag? FLAG_WRITEFLAG : 0) +
                    (no_exceptions? FLAG_NOEXCEPTIONS : 0)
#ifdef MEM_ARM
                    + (misc_flags & MEMORY_USER_ACCESS)
#endif
                    + (cache==CACHE_INSTRUCTION? FLAG_INSTR : 0));

                /*
                 *  If the translation caused an exception, or was invalid in
                 *  some way, then simply return without doing the memory
                 *  access:
                 */
                if (!ok)
                        return MEMORY_ACCESS_FAILED;
        }

#endif  /*  !MEM_USERLAND  */


#ifndef MEM_USERLAND
        /*
         *  Memory mapped device?
         *
         *  TODO: if paddr < base, but len enough, then the device should
         *  still be written to!
         */
        if (paddr >= mem->mmap_dev_minaddr && paddr < mem->mmap_dev_maxaddr) {
                uint64_t orig_paddr = paddr;
                int i, start, end, res;

#if 0

TODO: The correct solution for this is to add RAM devices _around_ the
dangerous device. The solution below incurs a slowdown for _everything_,
not just the device in question.

                /*
                 *  Really really slow, but unfortunately necessary. This is
                 *  to avoid the folowing scenario:
                 *
                 *      a) offsets 0x000..0x123 are normal memory
                 *      b) offsets 0x124..0x777 are a device
                 *
                 *      1) a read is done from offset 0x100. the page is
                 *         added to the dyntrans system as a "RAM" page
                 *      2) a dyntranslated read is done from offset 0x200,
                 *         which should access the device, but since the
                 *         entire page is added, it will access non-existant
                 *         RAM instead, without warning.
                 *
                 *  Setting dyntrans_device_danger = 1 on accesses which are
                 *  on _any_ offset on pages that are device mapped avoids
                 *  this problem, but it is probably not very fast.
                 *
                 *  TODO: Convert this into a quick (multi-level, 64-bit)
                 *  address space lookup, to find dangerous pages.
                 */
                for (i=0; i<mem->n_mmapped_devices; i++)
                        if (paddr >= (mem->devices[i].baseaddr & ~offset_mask)&&
                            paddr <= ((mem->devices[i].endaddr-1)|offset_mask)){
                                dyntrans_device_danger = 1;
                                break;
                        }
#endif

                start = 0; end = mem->n_mmapped_devices - 1;
                i = mem->last_accessed_device;

                /*  Scan through all devices:  */
                do {
                        if (paddr >= mem->devices[i].baseaddr &&
                            paddr < mem->devices[i].endaddr) {
                                /*  Found a device, let's access it:  */
                                mem->last_accessed_device = i;

                                paddr -= mem->devices[i].baseaddr;
                                if (paddr + len > mem->devices[i].length)
                                        len = mem->devices[i].length - paddr;

                                if (cpu->update_translation_table != NULL &&
                                    !(ok & MEMORY_NOT_FULL_PAGE) &&
                                    mem->devices[i].flags & DM_DYNTRANS_OK) {
                                        int wf = writeflag == MEM_WRITE? 1 : 0;
                                        unsigned char *host_addr;

                                        if (!(mem->devices[i].flags &
                                            DM_DYNTRANS_WRITE_OK))
                                                wf = 0;

                                        if (writeflag && wf) {
                                                if (paddr < mem->devices[i].
                                                    dyntrans_write_low)
                                                        mem->devices[i].
                                                        dyntrans_write_low =
                                                            paddr &~offset_mask;
                                                if (paddr >= mem->devices[i].
                                                    dyntrans_write_high)
                                                        mem->devices[i].
                                                        dyntrans_write_high =
                                                            paddr | offset_mask;
                                        }

                                        if (mem->devices[i].flags &
                                            DM_EMULATED_RAM) {
                                                /*  MEM_WRITE to force the page
                                                    to be allocated, if it
                                                    wasn't already  */
                                                uint64_t *pp = (uint64_t *)mem->
                                                    devices[i].dyntrans_data;
                                                uint64_t p = orig_paddr - *pp;
                                                host_addr =
                                                    memory_paddr_to_hostaddr(
                                                    mem, p & ~offset_mask,
                                                    MEM_WRITE);
                                        } else {
                                                host_addr = mem->devices[i].
                                                    dyntrans_data +
                                                    (paddr & ~offset_mask);
                                        }

                                        cpu->update_translation_table(cpu,
                                            vaddr & ~offset_mask, host_addr,
                                            wf, orig_paddr & ~offset_mask);
                                }

                                res = 0;
                                if (!no_exceptions || (mem->devices[i].flags &
                                    DM_READS_HAVE_NO_SIDE_EFFECTS))
                                        res = mem->devices[i].f(cpu, mem, paddr,
                                            data, len, writeflag,
                                            mem->devices[i].extra);

                                if (res == 0)
                                        res = -1;

                                /*
                                 *  If accessing the memory mapped device
                                 *  failed, then return with a DBE exception.
                                 */
                                if (res <= 0 && !no_exceptions) {
                                        debug("%s device '%s' addr %08lx "
                                            "failed\n", writeflag?
                                            "writing to" : "reading from",
                                            mem->devices[i].name, (long)paddr);
#ifdef MEM_MIPS
                                        mips_cpu_exception(cpu, EXCEPTION_DBE,
                                            0, vaddr, 0, 0, 0, 0);
#endif
                                        return MEMORY_ACCESS_FAILED;
                                }
                                goto do_return_ok;
                        }

                        if (paddr < mem->devices[i].baseaddr)
                                end = i - 1;
                        if (paddr >= mem->devices[i].endaddr)
                                start = i + 1;
                        i = (start + end) >> 1;
                } while (start <= end);
        }


#ifdef MEM_MIPS
        /*
         *  Data and instruction cache emulation:
         */

        switch (cpu->cd.mips.cpu_type.mmu_model) {
        case MMU3K:
                /*  if not uncached addess  (TODO: generalize this)  */
                if (!(misc_flags & PHYSICAL) && cache != CACHE_NONE &&
                    !((vaddr & 0xffffffffULL) >= 0xa0000000ULL &&
                      (vaddr & 0xffffffffULL) <= 0xbfffffffULL)) {
                        if (memory_cache_R3000(cpu, cache, paddr,
                            writeflag, len, data))
                                goto do_return_ok;
                }
                break;
        default:
                /*  R4000 etc  */
                /*  TODO  */
                ;
        }
#endif  /*  MEM_MIPS  */


        /*  Outside of physical RAM?  */
        if (paddr >= mem->physical_max) {
#ifdef MEM_MIPS
                if ((paddr & 0xffffc00000ULL) == 0x1fc00000) {
                        /*  Ok, this is PROM stuff  */
                } else if ((paddr & 0xfffff00000ULL) == 0x1ff00000) {
                        /*  Sprite reads from this area of memory...  */
                        /*  TODO: is this still correct?  */
                        if (writeflag == MEM_READ)
                                memset(data, 0, len);
                        goto do_return_ok;
                } else
#endif /* MIPS */
                {
                        if (paddr >= mem->physical_max && !no_exceptions)
                                memory_warn_about_unimplemented_addr
                                    (cpu, mem, writeflag, paddr, data, len);

                        if (writeflag == MEM_READ) {
                                /*  Return all zeroes? (Or 0xff? TODO)  */
                                memset(data, 0, len);

#ifdef MEM_MIPS
                                /*
                                 *  For real data/instruction accesses, cause
                                 *  an exceptions on an illegal read:
                                 */
                                if (cache != CACHE_NONE && cpu->machine->
                                    dbe_on_nonexistant_memaccess &&
                                    !no_exceptions) {
                                        if (paddr >= mem->physical_max &&
                                            paddr < mem->physical_max+1048576)
                                                mips_cpu_exception(cpu,
                                                    EXCEPTION_DBE, 0, vaddr, 0,
                                                    0, 0, 0);
                                }
#endif  /*  MEM_MIPS  */
                        }

                        /*  Hm? Shouldn't there be a DBE exception for
                            invalid writes as well?  TODO  */

                        goto do_return_ok;
                }
        }

#endif  /*  ifndef MEM_USERLAND  */


        /*
         *  Uncached access:
         *
         *  1)  Translate the physical address to a host address.
         *
         *  2)  Insert this virtual->physical->host translation into the
         *      fast translation arrays (using update_translation_table()).
         *
         *  3)  If this was a Write, then invalidate any code translations
         *      in that page.
         */
        memblock = memory_paddr_to_hostaddr(mem, paddr & ~offset_mask,
            writeflag);
        if (memblock == NULL) {
                if (writeflag == MEM_READ)
                        memset(data, 0, len);
                goto do_return_ok;
        }

        offset = paddr & offset_mask;

        if (cpu->update_translation_table != NULL && !dyntrans_device_danger
#ifdef MEM_MIPS
            /*  Ugly hack for R2000/R3000 caches:  */
            && (cpu->cd.mips.cpu_type.mmu_model != MMU3K ||
            !(cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & MIPS1_ISOL_CACHES))
#endif
#ifndef MEM_MIPS
/*          && !(misc_flags & MEMORY_USER_ACCESS)  */
#ifndef MEM_USERLAND
            && !(ok & MEMORY_NOT_FULL_PAGE)
#endif
#endif
            && !no_exceptions)
                cpu->update_translation_table(cpu, vaddr & ~offset_mask,
                    memblock, (misc_flags & MEMORY_USER_ACCESS) |
#if !defined(MEM_MIPS) && !defined(MEM_USERLAND)
                    (cache == CACHE_INSTRUCTION?
                        (writeflag == MEM_WRITE? 1 : 0) : ok - 1),
#else
                    (writeflag == MEM_WRITE? 1 : 0),
#endif
                    paddr & ~offset_mask);

        /*
         *  If writing, or if mapping a page where writing is ok later on,
         *  then invalidate code translations for the (physical) page address:
         */
        if ((writeflag == MEM_WRITE
#if !defined(MEM_USERLAND)
            || ok == 2
#endif
            ) && cpu->invalidate_code_translation != NULL)
                cpu->invalidate_code_translation(cpu, paddr, INVALIDATE_PADDR);

        if ((paddr&((1<<BITS_PER_MEMBLOCK)-1)) + len > (1<<BITS_PER_MEMBLOCK)) {
                printf("Write over memblock boundary?\n");
                exit(1);
        }

        /*  And finally, read or write the data:  */
        if (writeflag == MEM_WRITE)
                memcpy(memblock + offset, data, len);
        else
                memcpy(data, memblock + offset, len);

do_return_ok:
        return MEMORY_ACCESS_OK;
}

1	/*
2	* Copyright (C) 2003-2007 Anders Gavare. All rights reserved.
3	*
4	* Redistribution and use in source and binary forms, with or without
5	* modification, are permitted provided that the following conditions are met:
6	*
7	* 1. Redistributions of source code must retain the above copyright
8	* notice, this list of conditions and the following disclaimer.
9	* 2. Redistributions in binary form must reproduce the above copyright
10	* notice, this list of conditions and the following disclaimer in the
11	* documentation and/or other materials provided with the distribution.
12	* 3. The name of the author may not be used to endorse or promote products
13	* derived from this software without specific prior written permission.
14	*
15	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25	* SUCH DAMAGE.
26	*
27	*
28	* $Id: memory_rw.c,v 1.102 2007/04/16 15:13:44 debug Exp $
29	*
30	* Generic memory_rw(), with special hacks for specific CPU families.
31	*
32	* Example for inclusion from memory_mips.c:
33	*
34	* MEMORY_RW should be mips_memory_rw
35	* MEM_MIPS should be defined
36	*/
37
38
39	/*
40	* memory_rw():
41	*
42	* Read or write data from/to memory.
43	*
44	* cpu the cpu doing the read/write
45	* mem the memory object to use
46	* vaddr the virtual address
47	* data a pointer to the data to be written to memory, or
48	* a placeholder for data when reading from memory
49	* len the length of the 'data' buffer
50	* writeflag set to MEM_READ or MEM_WRITE
51	* misc_flags CACHE_{NONE,DATA,INSTRUCTION} \| other flags
52	*
53	* If the address indicates access to a memory mapped device, that device'
54	* read/write access function is called.
55	*
56	* This function should not be called with cpu == NULL.
57	*
58	* Returns one of the following:
59	* MEMORY_ACCESS_FAILED
60	* MEMORY_ACCESS_OK
61	*
62	* (MEMORY_ACCESS_FAILED is 0.)
63	*/
64	int MEMORY_RW(struct cpu cpu, struct memory mem, uint64_t vaddr,
65	unsigned char *data, size_t len, int writeflag, int misc_flags)
66	{
67	#ifdef MEM_ALPHA
68	const int offset_mask = 0x1fff;
69	#else
70	const int offset_mask = 0xfff;
71	#endif
72
73	#ifndef MEM_USERLAND
74	int ok = 1;
75	#endif
76	uint64_t paddr;
77	int cache, no_exceptions, offset;
78	unsigned char *memblock;
79	int dyntrans_device_danger = 0;
80
81	no_exceptions = misc_flags & NO_EXCEPTIONS;
82	cache = misc_flags & CACHE_FLAGS_MASK;
83
84
85	#ifdef MEM_USERLAND
86	#ifdef MEM_ALPHA
87	paddr = vaddr;
88	#else
89	paddr = vaddr & 0x7fffffff;
90	#endif
91	#else /* !MEM_USERLAND */
92	if (misc_flags & PHYSICAL \|\| cpu->translate_v2p == NULL) {
93	paddr = vaddr;
94	} else {
95	ok = cpu->translate_v2p(cpu, vaddr, &paddr,
96	(writeflag? FLAG_WRITEFLAG : 0) +
97	(no_exceptions? FLAG_NOEXCEPTIONS : 0)
98	#ifdef MEM_ARM
99	+ (misc_flags & MEMORY_USER_ACCESS)
100	#endif
101	+ (cache==CACHE_INSTRUCTION? FLAG_INSTR : 0));
102
103	/*
104	* If the translation caused an exception, or was invalid in
105	* some way, then simply return without doing the memory
106	* access:
107	*/
108	if (!ok)
109	return MEMORY_ACCESS_FAILED;
110	}
111
112	#endif /* !MEM_USERLAND */
113
114
115	#ifndef MEM_USERLAND
116	/*
117	* Memory mapped device?
118	*
119	* TODO: if paddr < base, but len enough, then the device should
120	* still be written to!
121	*/
122	if (paddr >= mem->mmap_dev_minaddr && paddr < mem->mmap_dev_maxaddr) {
123	uint64_t orig_paddr = paddr;
124	int i, start, end, res;
125
126	#if 0
127
128	TODO: The correct solution for this is to add RAM devices _around_ the
129	dangerous device. The solution below incurs a slowdown for _everything_,
130	not just the device in question.
131
132	/*
133	* Really really slow, but unfortunately necessary. This is
134	* to avoid the folowing scenario:
135	*
136	* a) offsets 0x000..0x123 are normal memory
137	* b) offsets 0x124..0x777 are a device
138	*
139	* 1) a read is done from offset 0x100. the page is
140	* added to the dyntrans system as a "RAM" page
141	* 2) a dyntranslated read is done from offset 0x200,
142	* which should access the device, but since the
143	* entire page is added, it will access non-existant
144	* RAM instead, without warning.
145	*
146	* Setting dyntrans_device_danger = 1 on accesses which are
147	* on _any_ offset on pages that are device mapped avoids
148	* this problem, but it is probably not very fast.
149	*
150	* TODO: Convert this into a quick (multi-level, 64-bit)
151	* address space lookup, to find dangerous pages.
152	*/
153	for (i=0; i<mem->n_mmapped_devices; i++)
154	if (paddr >= (mem->devices[i].baseaddr & ~offset_mask)&&
155	paddr <= ((mem->devices[i].endaddr-1)\|offset_mask)){
156	dyntrans_device_danger = 1;
157	break;
158	}
159	#endif
160
161	start = 0; end = mem->n_mmapped_devices - 1;
162	i = mem->last_accessed_device;
163
164	/* Scan through all devices: */
165	do {
166	if (paddr >= mem->devices[i].baseaddr &&
167	paddr < mem->devices[i].endaddr) {
168	/* Found a device, let's access it: */
169	mem->last_accessed_device = i;
170
171	paddr -= mem->devices[i].baseaddr;
172	if (paddr + len > mem->devices[i].length)
173	len = mem->devices[i].length - paddr;
174
175	if (cpu->update_translation_table != NULL &&
176	!(ok & MEMORY_NOT_FULL_PAGE) &&
177	mem->devices[i].flags & DM_DYNTRANS_OK) {
178	int wf = writeflag == MEM_WRITE? 1 : 0;
179	unsigned char *host_addr;
180
181	if (!(mem->devices[i].flags &
182	DM_DYNTRANS_WRITE_OK))
183	wf = 0;
184
185	if (writeflag && wf) {
186	if (paddr < mem->devices[i].
187	dyntrans_write_low)
188	mem->devices[i].
189	dyntrans_write_low =
190	paddr &~offset_mask;
191	if (paddr >= mem->devices[i].
192	dyntrans_write_high)
193	mem->devices[i].
194	dyntrans_write_high =
195	paddr \| offset_mask;
196	}
197
198	if (mem->devices[i].flags &
199	DM_EMULATED_RAM) {
200	/* MEM_WRITE to force the page
201	to be allocated, if it
202	wasn't already */
203	uint64_t pp = (uint64_t )mem->
204	devices[i].dyntrans_data;
205	uint64_t p = orig_paddr - *pp;
206	host_addr =
207	memory_paddr_to_hostaddr(
208	mem, p & ~offset_mask,
209	MEM_WRITE);
210	} else {
211	host_addr = mem->devices[i].
212	dyntrans_data +
213	(paddr & ~offset_mask);
214	}
215
216	cpu->update_translation_table(cpu,
217	vaddr & ~offset_mask, host_addr,
218	wf, orig_paddr & ~offset_mask);
219	}
220
221	res = 0;
222	if (!no_exceptions \|\| (mem->devices[i].flags &
223	DM_READS_HAVE_NO_SIDE_EFFECTS))
224	res = mem->devices[i].f(cpu, mem, paddr,
225	data, len, writeflag,
226	mem->devices[i].extra);
227
228	if (res == 0)
229	res = -1;
230
231	/*
232	* If accessing the memory mapped device
233	* failed, then return with a DBE exception.
234	*/
235	if (res <= 0 && !no_exceptions) {
236	debug("%s device '%s' addr %08lx "
237	"failed\n", writeflag?
238	"writing to" : "reading from",
239	mem->devices[i].name, (long)paddr);
240	#ifdef MEM_MIPS
241	mips_cpu_exception(cpu, EXCEPTION_DBE,
242	0, vaddr, 0, 0, 0, 0);
243	#endif
244	return MEMORY_ACCESS_FAILED;
245	}
246	goto do_return_ok;
247	}
248
249	if (paddr < mem->devices[i].baseaddr)
250	end = i - 1;
251	if (paddr >= mem->devices[i].endaddr)
252	start = i + 1;
253	i = (start + end) >> 1;
254	} while (start <= end);
255	}
256
257
258	#ifdef MEM_MIPS
259	/*
260	* Data and instruction cache emulation:
261	*/
262
263	switch (cpu->cd.mips.cpu_type.mmu_model) {
264	case MMU3K:
265	/* if not uncached addess (TODO: generalize this) */
266	if (!(misc_flags & PHYSICAL) && cache != CACHE_NONE &&
267	!((vaddr & 0xffffffffULL) >= 0xa0000000ULL &&
268	(vaddr & 0xffffffffULL) <= 0xbfffffffULL)) {
269	if (memory_cache_R3000(cpu, cache, paddr,
270	writeflag, len, data))
271	goto do_return_ok;
272	}
273	break;
274	default:
275	/* R4000 etc */
276	/* TODO */
277	;
278	}
279	#endif /* MEM_MIPS */
280
281
282	/* Outside of physical RAM? */
283	if (paddr >= mem->physical_max) {
284	#ifdef MEM_MIPS
285	if ((paddr & 0xffffc00000ULL) == 0x1fc00000) {
286	/* Ok, this is PROM stuff */
287	} else if ((paddr & 0xfffff00000ULL) == 0x1ff00000) {
288	/* Sprite reads from this area of memory... */
289	/* TODO: is this still correct? */
290	if (writeflag == MEM_READ)
291	memset(data, 0, len);
292	goto do_return_ok;
293	} else
294	#endif /* MIPS */
295	{
296	if (paddr >= mem->physical_max && !no_exceptions)
297	memory_warn_about_unimplemented_addr
298	(cpu, mem, writeflag, paddr, data, len);
299
300	if (writeflag == MEM_READ) {
301	/* Return all zeroes? (Or 0xff? TODO) */
302	memset(data, 0, len);
303
304	#ifdef MEM_MIPS
305	/*
306	* For real data/instruction accesses, cause
307	* an exceptions on an illegal read:
308	*/
309	if (cache != CACHE_NONE && cpu->machine->
310	dbe_on_nonexistant_memaccess &&
311	!no_exceptions) {
312	if (paddr >= mem->physical_max &&
313	paddr < mem->physical_max+1048576)
314	mips_cpu_exception(cpu,
315	EXCEPTION_DBE, 0, vaddr, 0,
316	0, 0, 0);
317	}
318	#endif /* MEM_MIPS */
319	}
320
321	/* Hm? Shouldn't there be a DBE exception for
322	invalid writes as well? TODO */
323
324	goto do_return_ok;
325	}
326	}
327
328	#endif /* ifndef MEM_USERLAND */
329
330
331	/*
332	* Uncached access:
333	*
334	* 1) Translate the physical address to a host address.
335	*
336	* 2) Insert this virtual->physical->host translation into the
337	* fast translation arrays (using update_translation_table()).
338	*
339	* 3) If this was a Write, then invalidate any code translations
340	* in that page.
341	*/
342	memblock = memory_paddr_to_hostaddr(mem, paddr & ~offset_mask,
343	writeflag);
344	if (memblock == NULL) {
345	if (writeflag == MEM_READ)
346	memset(data, 0, len);
347	goto do_return_ok;
348	}
349
350	offset = paddr & offset_mask;
351
352	if (cpu->update_translation_table != NULL && !dyntrans_device_danger
353	#ifdef MEM_MIPS
354	/* Ugly hack for R2000/R3000 caches: */
355	&& (cpu->cd.mips.cpu_type.mmu_model != MMU3K \|\|
356	!(cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & MIPS1_ISOL_CACHES))
357	#endif
358	#ifndef MEM_MIPS
359	/* && !(misc_flags & MEMORY_USER_ACCESS) */
360	#ifndef MEM_USERLAND
361	&& !(ok & MEMORY_NOT_FULL_PAGE)
362	#endif
363	#endif
364	&& !no_exceptions)
365	cpu->update_translation_table(cpu, vaddr & ~offset_mask,
366	memblock, (misc_flags & MEMORY_USER_ACCESS) \|
367	#if !defined(MEM_MIPS) && !defined(MEM_USERLAND)
368	(cache == CACHE_INSTRUCTION?
369	(writeflag == MEM_WRITE? 1 : 0) : ok - 1),
370	#else
371	(writeflag == MEM_WRITE? 1 : 0),
372	#endif
373	paddr & ~offset_mask);
374
375	/*
376	* If writing, or if mapping a page where writing is ok later on,
377	* then invalidate code translations for the (physical) page address:
378	*/
379	if ((writeflag == MEM_WRITE
380	#if !defined(MEM_USERLAND)
381	\|\| ok == 2
382	#endif
383	) && cpu->invalidate_code_translation != NULL)
384	cpu->invalidate_code_translation(cpu, paddr, INVALIDATE_PADDR);
385
386	if ((paddr&((1<<BITS_PER_MEMBLOCK)-1)) + len > (1<<BITS_PER_MEMBLOCK)) {
387	printf("Write over memblock boundary?\n");
388	exit(1);
389	}
390
391	/* And finally, read or write the data: */
392	if (writeflag == MEM_WRITE)
393	memcpy(memblock + offset, data, len);
394	else
395	memcpy(data, memblock + offset, len);
396
397	do_return_ok:
398	return MEMORY_ACCESS_OK;
399	}
400