--- trunk/src/memory_rw.c 2007/10/08 16:18:31 11 +++ trunk/src/memory_rw.c 2007/10/08 16:18:38 12 @@ -25,7 +25,7 @@ * SUCH DAMAGE. * * - * $Id: memory_rw.c,v 1.38 2005/06/27 07:03:39 debug Exp $ + * $Id: memory_rw.c,v 1.57 2005/08/12 21:57:02 debug Exp $ * * Generic memory_rw(), with special hacks for specific CPU families. * @@ -68,28 +68,26 @@ int MEMORY_RW(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags) { +#ifdef MEM_ALPHA + const int offset_mask = 0x1fff; +#else + const int offset_mask = 0xfff; +#endif + #ifndef MEM_USERLAND int ok = 1; #endif uint64_t paddr; int cache, no_exceptions, offset; unsigned char *memblock; -#ifdef BINTRANS +#ifdef MEM_MIPS int bintrans_cached = cpu->machine->bintrans_enable; - int bintrans_device_danger = 0; #endif + int bintrans_device_danger = 0; + no_exceptions = cache_flags & NO_EXCEPTIONS; cache = cache_flags & CACHE_FLAGS_MASK; -#ifdef MEM_PPC - if (cpu->cd.ppc.bits == 32) - vaddr &= 0xffffffff; -#endif - -#ifdef MEM_ARM - vaddr &= 0x3fffffff; -#endif - #ifdef MEM_X86 /* Real-mode wrap-around: */ if (REAL_MODE && !(cache_flags & PHYSICAL)) { @@ -150,28 +148,21 @@ } #endif /* X86 */ -#ifdef MEM_URISC - { - uint64_t mask = (uint64_t) -1; - if (cpu->cd.urisc.wordlen < 64) - mask = ((int64_t)1 << cpu->cd.urisc.wordlen) - 1; - vaddr &= mask; - } -#endif - #ifdef MEM_MIPS -#ifdef BINTRANS if (bintrans_cached) { if (cache == CACHE_INSTRUCTION) { cpu->cd.mips.pc_bintrans_host_4kpage = NULL; cpu->cd.mips.pc_bintrans_paddr_valid = 0; } } -#endif #endif /* MEM_MIPS */ #ifdef MEM_USERLAND +#ifdef MEM_ALPHA + paddr = vaddr; +#else paddr = vaddr & 0x7fffffff; +#endif goto have_paddr; #endif @@ -195,6 +186,26 @@ if (cache_flags & PHYSICAL || cpu->translate_address == NULL) { paddr = vaddr; + +#ifdef MEM_ALPHA + /* paddr &= 0x1fffffff; For testalpha */ + paddr &= 0x000003ffffffffffULL; +#endif + +#ifdef MEM_ARM + paddr &= 0x3fffffff; +#endif + +#ifdef MEM_IA64 + /* For testia64 */ + paddr &= 0x3fffffff; +#endif + +#ifdef MEM_PPC + if (cpu->cd.ppc.bits == 32) + paddr &= 0xffffffff; +#endif + } else { ok = cpu->translate_address(cpu, vaddr, &paddr, (writeflag? FLAG_WRITEFLAG : 0) + @@ -255,14 +266,12 @@ #ifdef MEM_MIPS /* TODO: How about bintrans vs cache emulation? */ -#ifdef BINTRANS if (bintrans_cached) { if (cache == CACHE_INSTRUCTION) { cpu->cd.mips.pc_bintrans_paddr_valid = 1; cpu->cd.mips.pc_bintrans_paddr = paddr; } } -#endif #endif /* MEM_MIPS */ @@ -276,12 +285,9 @@ * to a device to */ if (paddr >= mem->mmap_dev_minaddr && paddr < mem->mmap_dev_maxaddr) { -#ifdef BINTRANS uint64_t orig_paddr = paddr; -#endif int i, start, res; -#ifdef BINTRANS /* * Really really slow, but unfortunately necessary. This is * to avoid the folowing scenario: @@ -300,16 +306,13 @@ * on _any_ offset on pages that are device mapped avoids * this problem, but it is probably not very fast. */ - if (bintrans_cached) { - for (i=0; in_mmapped_devices; i++) - if (paddr >= (mem->dev_baseaddr[i] & ~0xfff) && - paddr <= ((mem->dev_baseaddr[i] + - mem->dev_length[i] - 1) | 0xfff)) { - bintrans_device_danger = 1; - break; - } - } -#endif + for (i=0; in_mmapped_devices; i++) + if (paddr >= (mem->dev_baseaddr[i] & ~offset_mask) && + paddr <= ((mem->dev_baseaddr[i] + + mem->dev_length[i] - 1) | offset_mask)) { + bintrans_device_danger = 1; + break; + } i = start = mem->last_accessed_device; @@ -324,36 +327,35 @@ if (paddr + len > mem->dev_length[i]) len = mem->dev_length[i] - paddr; -#ifdef BINTRANS - if (bintrans_cached && mem->dev_flags[i] & - MEM_BINTRANS_OK) { + if (cpu->update_translation_table != NULL && + mem->dev_flags[i] & MEM_DYNTRANS_OK) { int wf = writeflag == MEM_WRITE? 1 : 0; if (writeflag) { if (paddr < mem-> - dev_bintrans_write_low[i]) + dev_dyntrans_write_low[i]) mem-> - dev_bintrans_write_low - [i] = - paddr & ~0xfff; - if (paddr > mem-> - dev_bintrans_write_high[i]) + dev_dyntrans_write_low + [i] = paddr & + ~offset_mask; + if (paddr >= mem-> + dev_dyntrans_write_high[i]) mem-> - dev_bintrans_write_high - [i] = paddr | 0xfff; + dev_dyntrans_write_high + [i] = paddr | + offset_mask; } if (!(mem->dev_flags[i] & - MEM_BINTRANS_WRITE_OK)) + MEM_DYNTRANS_WRITE_OK)) wf = 0; - update_translation_table(cpu, - vaddr & ~0xfff, - mem->dev_bintrans_data[i] + - (paddr & ~0xfff), - wf, orig_paddr & ~0xfff); + cpu->update_translation_table(cpu, + vaddr & ~offset_mask, + mem->dev_dyntrans_data[i] + + (paddr & ~offset_mask), + wf, orig_paddr & ~offset_mask); } -#endif res = 0; if (!no_exceptions || (mem->dev_flags[i] & @@ -414,33 +416,6 @@ goto do_return_ok; } break; -#if 0 -/* Remove this, it doesn't work anyway */ - case MMU10K: - /* other cpus: */ - /* - * SUPER-UGLY HACK for SGI-IP32 PROM, R10000: - * K0 bits == 0x3 means uncached... - * - * It seems that during bootup, the SGI-IP32 prom - * stores a return pointers a 0x80000f10, then tests - * memory by writing bit patterns to 0xa0000xxx, and - * then when it's done, reads back the return pointer - * from 0x80000f10. - * - * I need to find the correct way to disconnect the - * cache from the main memory for R10000. (TODO !!!) - */ -/* if ((cpu->cd.mips.coproc[0]->reg[COP0_CONFIG] & 7) == 3) { */ -/* - if (cache == CACHE_DATA && - cpu->r10k_cache_disable_TODO) { - paddr &= ((512*1024)-1); - paddr += 512*1024; - } -*/ - break; -#endif default: /* R4000 etc */ /* TODO */ @@ -465,13 +440,21 @@ { if (paddr >= mem->physical_max) { char *symbol; -#ifdef MEM_MIPS + uint64_t old_pc; uint64_t offset; + +#ifdef MEM_MIPS + old_pc = cpu->cd.mips.pc_last; +#else + /* Default instruction size on most + RISC archs is 32 bits: */ + old_pc = cpu->pc - sizeof(uint32_t); #endif + /* This allows for example OS kernels to probe memory a few KBs past the end of memory, without giving too many warnings. */ - if (!quiet_mode && paddr >= + if (!quiet_mode && !no_exceptions && paddr >= mem->physical_max + 0x40000) { fatal("[ memory_rw(): writeflag=%i ", writeflag); @@ -499,28 +482,30 @@ data[i]); debug("}"); } -#ifdef MEM_MIPS + + fatal(" paddr=0x%llx >= physical_max" + "; pc=", (long long)paddr); + if (cpu->is_32bit) + fatal("0x%08x",(int)old_pc); + else + fatal("0x%016llx", + (long long)old_pc); symbol = get_symbol_name( &cpu->machine->symbol_context, - cpu->cd.mips.pc_last, &offset); -#else - symbol = "(unimpl for non-MIPS)"; -#endif - -/* TODO: fix! not mips.pc_last for for example ppc */ - - fatal(" paddr=%llx >= physical_max pc=" - "0x%08llx <%s> ]\n", - (long long)paddr, - (long long)cpu->cd.mips.pc_last, - symbol? symbol : "no symbol"); + old_pc, &offset); + fatal(" <%s> ]\n", + symbol? symbol : " no symbol "); } if (cpu->machine->single_step_on_bad_addr) { fatal("[ unimplemented access to " - "0x%016llx, pc = 0x%016llx ]\n", - (long long)paddr, - (long long)cpu->pc); + "0x%llx, pc=0x",(long long)paddr); + if (cpu->is_32bit) + fatal("%08x ]\n", + (int)old_pc); + else + fatal("%016llx ]\n", + (long long)old_pc); single_step = 1; } } @@ -573,10 +558,9 @@ offset = paddr & ((1 << BITS_PER_MEMBLOCK) - 1); -#ifdef BINTRANS - if (bintrans_cached && !bintrans_device_danger) - update_translation_table(cpu, vaddr & ~0xfff, - memblock + (offset & ~0xfff), + if (cpu->update_translation_table != NULL && !bintrans_device_danger) + cpu->update_translation_table(cpu, vaddr & ~offset_mask, + memblock + (offset & ~offset_mask), #if 0 cache == CACHE_INSTRUCTION? (writeflag == MEM_WRITE? 1 : 0) @@ -584,18 +568,21 @@ #else writeflag == MEM_WRITE? 1 : 0, #endif - paddr & ~0xfff); -#endif + paddr & ~offset_mask); if (writeflag == MEM_WRITE) { - if (len == sizeof(uint32_t) && (offset & 3)==0) + /* Ugly optimization, but it works: */ + if (len == sizeof(uint32_t) && (offset & 3)==0 + && ((size_t)data&3)==0) *(uint32_t *)(memblock + offset) = *(uint32_t *)data; else if (len == sizeof(uint8_t)) *(uint8_t *)(memblock + offset) = *(uint8_t *)data; else memcpy(memblock + offset, data, len); } else { - if (len == sizeof(uint32_t) && (offset & 3)==0) + /* Ugly optimization, but it works: */ + if (len == sizeof(uint32_t) && (offset & 3)==0 + && ((size_t)data&3)==0) *(uint32_t *)data = *(uint32_t *)(memblock + offset); else if (len == sizeof(uint8_t)) *(uint8_t *)data = *(uint8_t *)(memblock + offset); @@ -605,13 +592,11 @@ #ifdef MEM_MIPS if (cache == CACHE_INSTRUCTION) { cpu->cd.mips.pc_last_host_4k_page = memblock - + (offset & ~0xfff); -#ifdef BINTRANS + + (offset & ~offset_mask); if (bintrans_cached) { cpu->cd.mips.pc_bintrans_host_4kpage = cpu->cd.mips.pc_last_host_4k_page; } -#endif } #endif /* MIPS */ }