25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: memory_rw.c,v 1.102 2007/04/16 15:13:44 debug Exp $ |
* $Id: memory_rw.c,v 1.107 2007/06/12 03:49:11 debug Exp $ |
29 |
* |
* |
30 |
* Generic memory_rw(), with special hacks for specific CPU families. |
* Generic memory_rw(), with special hacks for specific CPU families. |
31 |
* |
* |
33 |
* |
* |
34 |
* MEMORY_RW should be mips_memory_rw |
* MEMORY_RW should be mips_memory_rw |
35 |
* MEM_MIPS should be defined |
* MEM_MIPS should be defined |
36 |
|
* |
37 |
|
* |
38 |
|
* TODO: Cleanup the "ok" variable usage! |
39 |
*/ |
*/ |
40 |
|
|
41 |
|
|
74 |
#endif |
#endif |
75 |
|
|
76 |
#ifndef MEM_USERLAND |
#ifndef MEM_USERLAND |
77 |
int ok = 1; |
int ok = 2; |
78 |
#endif |
#endif |
79 |
uint64_t paddr; |
uint64_t paddr; |
80 |
int cache, no_exceptions, offset; |
int cache, no_exceptions, offset; |
98 |
ok = cpu->translate_v2p(cpu, vaddr, &paddr, |
ok = cpu->translate_v2p(cpu, vaddr, &paddr, |
99 |
(writeflag? FLAG_WRITEFLAG : 0) + |
(writeflag? FLAG_WRITEFLAG : 0) + |
100 |
(no_exceptions? FLAG_NOEXCEPTIONS : 0) |
(no_exceptions? FLAG_NOEXCEPTIONS : 0) |
|
#ifdef MEM_ARM |
|
101 |
+ (misc_flags & MEMORY_USER_ACCESS) |
+ (misc_flags & MEMORY_USER_ACCESS) |
|
#endif |
|
102 |
+ (cache==CACHE_INSTRUCTION? FLAG_INSTR : 0)); |
+ (cache==CACHE_INSTRUCTION? FLAG_INSTR : 0)); |
103 |
|
|
104 |
/* |
/* |
239 |
"writing to" : "reading from", |
"writing to" : "reading from", |
240 |
mem->devices[i].name, (long)paddr); |
mem->devices[i].name, (long)paddr); |
241 |
#ifdef MEM_MIPS |
#ifdef MEM_MIPS |
242 |
mips_cpu_exception(cpu, EXCEPTION_DBE, |
mips_cpu_exception(cpu, |
243 |
|
cache == CACHE_INSTRUCTION? |
244 |
|
EXCEPTION_IBE : EXCEPTION_DBE, |
245 |
0, vaddr, 0, 0, 0, 0); |
0, vaddr, 0, 0, 0, 0); |
246 |
#endif |
#endif |
247 |
return MEMORY_ACCESS_FAILED; |
return MEMORY_ACCESS_FAILED; |
304 |
/* Return all zeroes? (Or 0xff? TODO) */ |
/* Return all zeroes? (Or 0xff? TODO) */ |
305 |
memset(data, 0, len); |
memset(data, 0, len); |
306 |
|
|
307 |
|
#if 0 |
308 |
|
/* |
309 |
|
* NOTE: This code prevents a PROM image from a real 5000/200 from booting. |
310 |
|
* I think I introduced it because it was how some guest OS (NetBSD?) detected |
311 |
|
* the amount of RAM on some machine. |
312 |
|
* |
313 |
|
* TODO: Figure out if it is not needed anymore, and remove it completely. |
314 |
|
*/ |
315 |
#ifdef MEM_MIPS |
#ifdef MEM_MIPS |
316 |
/* |
/* |
317 |
* For real data/instruction accesses, cause |
* For real data/instruction accesses, cause |
318 |
* an exceptions on an illegal read: |
* an exceptions on an illegal read: |
319 |
*/ |
*/ |
320 |
if (cache != CACHE_NONE && cpu->machine-> |
if (cache != CACHE_NONE && !no_exceptions && |
321 |
dbe_on_nonexistant_memaccess && |
paddr >= mem->physical_max && |
322 |
!no_exceptions) { |
paddr < mem->physical_max+1048576) { |
323 |
if (paddr >= mem->physical_max && |
mips_cpu_exception(cpu, |
324 |
paddr < mem->physical_max+1048576) |
EXCEPTION_DBE, 0, vaddr, 0, |
325 |
mips_cpu_exception(cpu, |
0, 0, 0); |
|
EXCEPTION_DBE, 0, vaddr, 0, |
|
|
0, 0, 0); |
|
326 |
} |
} |
327 |
#endif /* MEM_MIPS */ |
#endif /* MEM_MIPS */ |
328 |
|
#endif |
329 |
} |
} |
330 |
|
|
331 |
/* Hm? Shouldn't there be a DBE exception for |
/* Hm? Shouldn't there be a DBE exception for |
365 |
&& (cpu->cd.mips.cpu_type.mmu_model != MMU3K || |
&& (cpu->cd.mips.cpu_type.mmu_model != MMU3K || |
366 |
!(cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & MIPS1_ISOL_CACHES)) |
!(cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & MIPS1_ISOL_CACHES)) |
367 |
#endif |
#endif |
|
#ifndef MEM_MIPS |
|
|
/* && !(misc_flags & MEMORY_USER_ACCESS) */ |
|
368 |
#ifndef MEM_USERLAND |
#ifndef MEM_USERLAND |
369 |
&& !(ok & MEMORY_NOT_FULL_PAGE) |
&& !(ok & MEMORY_NOT_FULL_PAGE) |
370 |
#endif |
#endif |
|
#endif |
|
371 |
&& !no_exceptions) |
&& !no_exceptions) |
372 |
cpu->update_translation_table(cpu, vaddr & ~offset_mask, |
cpu->update_translation_table(cpu, vaddr & ~offset_mask, |
373 |
memblock, (misc_flags & MEMORY_USER_ACCESS) | |
memblock, (misc_flags & MEMORY_USER_ACCESS) | |
374 |
#if !defined(MEM_MIPS) && !defined(MEM_USERLAND) |
#if !defined(MEM_USERLAND) |
375 |
(cache == CACHE_INSTRUCTION? |
(cache == CACHE_INSTRUCTION? |
376 |
(writeflag == MEM_WRITE? 1 : 0) : ok - 1), |
(writeflag == MEM_WRITE? 1 : 0) : ok - 1), |
377 |
#else |
#else |
383 |
* If writing, or if mapping a page where writing is ok later on, |
* If writing, or if mapping a page where writing is ok later on, |
384 |
* then invalidate code translations for the (physical) page address: |
* then invalidate code translations for the (physical) page address: |
385 |
*/ |
*/ |
386 |
|
|
387 |
if ((writeflag == MEM_WRITE |
if ((writeflag == MEM_WRITE |
388 |
#if !defined(MEM_USERLAND) |
#if !defined(MEM_USERLAND) |
389 |
|| ok == 2 |
|| (ok == 2 && cache == CACHE_DATA) |
390 |
#endif |
#endif |
391 |
) && cpu->invalidate_code_translation != NULL) |
) && cpu->invalidate_code_translation != NULL) |
392 |
cpu->invalidate_code_translation(cpu, paddr, INVALIDATE_PADDR); |
cpu->invalidate_code_translation(cpu, paddr, INVALIDATE_PADDR); |